KR920004224Y1 - Camera circuit - Google Patents

Abstract

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Description

Camera shutter speed priority circuit

1 is a circuit diagram of the present invention.

2 and 3 is a circuit diagram of one embodiment of the present invention.

4 is a schematic diagram showing the electronic shutter speed and the state of the aperture.

5 is a waveform diagram of each part of the present invention.

6 is an optical accumulation schematic diagram of a normal mode and an electronic shutter mode.

* Explanation of symbols for main parts of the drawings

1: Iris drive voltage detection and drive circuit 2: HS drive detector

3: up / down counter 4: up / down counter

5: comparator and decoder 6: end gate

9: subtractor

The present invention relates to a shutter speed priority circuit of a camera that detects the aperture driving voltage of a video camera to obtain a clearer picture quality by varying the shutter speed when photographing a subject having a certain illumination level.

In video cameras of general purpose, the image sensor uses CCD (CHARGE COUPLED DEVICE) as the image sensor to accumulate light for a certain period of time and then read it. In case of NTSC, optical accumulation time is 1 vertical period. This means that for PAL the photometric time is It will be about seconds.

Therefore, since the aperture is always open and the shutter speed is fixed, the amount of incident light changes according to the driving of the aperture.

In other words, by closing the iris for a bright subject and opening the iris for a dark subject, the amount of incident light was constantly adjusted.

However, if the optical accumulation time is shortened, a sharper image can be obtained, such as a higher shutter speed of a general still camera, which is called a high speed electronic shutter.

In other words, the present invention incorporates a high-speed electronic shutter function in a video camera using a CCD so that a sharper image can be taken.

As described above, the present invention will be described in detail with reference to the accompanying drawings to obtain a clearer image by varying the shutter speed when photographing a subject having a predetermined illuminance even in a video camera as the shutter speed of the still camera is increased.

FIG. 1 is an arc diagram of the present invention, which comprises an aperture driving voltage detection and driving circuit 1 for detecting an aperture driving voltage and driving an aperture, and employing a CCD, wherein the aperture driving voltage detection and driving circuit ( The HS drive detector 2 for sensing the illuminance imaged using the aperture drive voltage of 1) and the operation of holding the up / down count operation and the count value in accordance with the output of the HS drive detector 2 are performed. Optical accumulation period is adjusted by comparing the up / down counter 3 to be performed, the up counter 4 reset every vertical period, and the outputs of the up / down counter 3 and the up counter 4. A comparator and decoder 5 for outputting a pulse, an end gate 6 for logically multiplying the output of the comparator and decoder 5 with the HS pulse, and an output of the end gate 6 to amplify the CCD substrate voltage. Amplifier on (VSUB) It consists of (7).

2 is a circuit diagram of an embodiment of the present invention, the HS driving detector 2 includes a comparator 21 and 22 for comparing the aperture driving voltage with a reference voltage set by the resistors R ₁ -R ₃ , and the comparator ( And a comparator 23 for comparing the outputs of the comparators 21 and 22 by applying a micom hold detection signal by logically combining the outputs of the 21 and 22 output signals.

The output of the octal up / down counter 3 is configured to be compared with the comparator 54 after being converted to DC level through the digital analog converter 51 and 52 together with the output of the up counter 4. The output of the up / down counter 3 is configured to be switched by the output of the EVR: ELECTRIC VARIABLE RESISTER: 53 to which the microcomputer data is applied and by the mode selection signal of the microcomputer at the analog switch SW ₁ .

3 is another embodiment of the present invention, in which the output of the noar gate 24 is configured to be applied to the up / down counter 3, and the output of the up / down counter 3 and the output of the up counter 4 are subtractors. (9) it is configured to be applied to the end gate 6 after being subtracted.

4 is a schematic diagram showing the electronic shutter speed and the state of the aperture, FIG. 5 is a waveform diagram of each part of the embodiment, and FIG. 6 is a schematic view of the optical accumulation of the normal mode and the electronic shutter mode.

In the present invention configured as described above, first, the difference between the optical accumulation of the battery shutter mode and the normal mode of the NTSC and the readout for reading the same will be briefly described according to FIG.

Normal mode will lead out after accumulating light for 1 feed (1 vertical period), but in electronic shutter mode, if the accumulated charge is reset after some time of optical accumulation, it will accumulate again from there. Since only the light (hatched) is outputted, it is the same as the shutter control.

At this time, the accumulated charge can be used to change the electronic reset mode by changing the reset point to an arbitrary position.

With this in mind If you set the reset period by dividing the second into about 256 using 8 bits, You can get an electronic shutter of seconds and actually on the camera Seconds are enough, so there is no problem in practical use.

That is, as shown in the schematic diagram of FIG. 4, the solid line indicates the state when the illuminance becomes bright, and the dotted line indicates the state when the illuminance decreases.

1 is a circuit diagram of the present invention, which detects an aperture driving voltage by detecting a luminance signal input level, detects an aperture driving voltage for driving an aperture according to the detected aperture driving voltage, and detects an aperture driving voltage of a driving circuit 1 The output detected by the HS drive detector 2 that senses the imaged illuminance is applied to the 8-bit up / down counter 3 and to the microcomputer to detect the case of the appropriate electronic shutter mode in the microcomputer. .

At this time, the up / down counter 3 up / down counts the clock signal CLK, which is a horizontal period pulse, according to the output of the HS driving detector 2 and applies the comparator and the decoder 5 to the microcomputer set control. The signal is applied and set to a constant value. In the case of an appropriate electronic shutter mode, the microcomputer applies a hold signal (HOLD) that holds the up / down counter (3).

In the up counter 4 to which the reset pulse RESET of the vertical period which resets the counter every 1 vertical period is applied, the up counter 4 up-counts the clock signal CLK, which is a horizontal period pulse, to be applied to the comparator and the decoder 5. do.

The comparator and the decoder 5 compare the outputs of the up / down counter 3 and the up counter 4 to output a pulse in which a period for accumulating the optical signal during the electronic shutter mode is determined.

The output waveforms of the comparator and decoder 5 are multiplied by the HS pulse input and the AND gate 6 to be amplified enough to reset the CCD in the amplifier 7, and then loaded on the substrate voltage VSUB of the CCD. To be authorized.

The present invention will be described in detail with reference to the embodiment of FIG. 3 and then the embodiment of FIG.

3 is a circuit diagram of an embodiment of the present invention, and the aperture driving voltage detected by the aperture driving voltage detection circuit 1 includes the non-inverting terminal (+) of the comparator 21 of the HS driving detector 2 and the comparator ( 22 is applied to the inverting terminal (-), and the inverting terminal (-) of the comparator 21 and the non-inverting terminal (+) of the comparator 22 are set by resistors R ₁ (R ₂ ) (R ₃ ). The applied reference voltage V ₁ (V ₂ ) is applied.

At this time, the reference voltage (V ₁ ) is And the reference voltage (V ₂ ) Becomes

Therefore, when the aperture driving voltage is greater than the reference voltage (V ₁ ) (that is, when the illuminance is low), the comparator 21 outputs a high level and when the aperture driving voltage is lower than the reference voltage (V ₂ ) (that is, when the illumination is high). ) The comparator 22 outputs a high level, and the output of the comparator 21 is applied to the inverting terminal (-) of the comparator 23 and the output of the comparator 22 is applied to the non-inverting terminal (+) of the comparator 23. Therefore, the output of the comparator 23 outputs a high level when the illuminance is high and a low level when the illuminance is low.

The outputs of the comparators 21 and 22 are applied to the input side of the NOA gate 24, and the outputs of the NOA gate 24 and the comparator 23 are applied to the up / down counter 3.

In this case, the truth table for the function of the up / down counter 30 by the outputs of the comparators 21, 22, 23 and the noah gate 24 and the outputs of the comparators 21-23 and the noah gate 24 are shown. Is as follows.

That is, when the aperture driving voltage is greater than the reference voltage (V ₂ ) or less than the reference voltage (V ₁ ), the output of the NOA gate 24 becomes high level, and the up / down counter 3 stops counting. When the aperture driving voltage is lower than the reference voltage (V ₂ ) (high intensity), the output of the comparator 23 becomes the high level, and the up / down counter 3 up counts, and the aperture driving voltage is When it is higher than the reference voltage V ₁ (low illumination), the output of the comparator 23 becomes low level, and the up / down counter 3 counts down.

At this time, the up / down counter 3 is applied with a clock signal of a horizontal period as in (c) of FIG. 5, and such a clock signal is also applied to the counter 4, and the up counter 4 is shown in FIG. The up count is performed only after each period is reset by the pulse of the vertical period as shown in FIG.

The counter counts a clock signal of a horizontal period. Since one horizontal period is 63.5 μsec, the counter can vary by 63.5 μsec in one bit change, and 8 bits can be arbitrarily changed to 28 = 256 bits.

On the other hand, the output of the 8-bit up / down counter 3 is applied to one terminal (+) of the subtractor 9 and the output of the up counter 4 is applied to the other terminal (-) of the subtractor 9 (+). Terminal input-(-) terminal input is executed, and if the result value is (+), it is configured to output high level and (-) to output low level every vertical period until it is equal to the value of up / down counter (3). The subtractor 9 outputs a high level and then a low level in comparison with the up counter 4, which is reset. Therefore, the subtractor 9 outputs a pulse as shown in d of FIG. do.

Since the output of the subtractor 9 is applied to the AND gate 6 and logically multiplied with the HS pulse as shown in a of FIG. 5, the output side of the AND gate 6 outputs the same pulse as in FIG. The output pulse of the AND gate 6 is amplified enough to reset the CCD in the amplifier 7 and then loaded on the CCD substrate voltage VSUB through the DC coupling capacitor 8.

That is, in the waveform (E) of FIG. 5, the place where the pulse is continuously resets and the pulse only measures the signal, thereby achieving the object of the present invention.

In addition, the present invention is a shutter speed priority circuit because the whole organically continues to operate with negative feedback and operates in preference to the aperture driving.

As described above, although an exemplary circuit of the present invention that does not receive a microcomputer control has been described, an exemplary embodiment of the present invention will be described by receiving a microcomputer control according to FIG. 2.

FIG. 2 is characterized in that the overall operation is the same as that of FIG. 3, but can be controlled by the microcomputer, and that a simple comparator 54 is used without using the subtractor 9.

That is, the aperture drive voltage of the aperture drive voltage detection circuit 1 is detected by the H.S drive detector 2 in the same manner as in the third method, but the output of the noah gate 24 is applied to the microcomputer.

The outputs of the up / down up counter 3 and the counter 4 are converted to the DC level through the digital analog converters 51 and 52 and then applied to the comparator 54 to be output.

Therefore, when the output of the uptowner 4 becomes larger than the output of the up / down counter 4, the comparator 54 outputs a low level.

(See Figure 5d Figure Waveform)

At this time, the up counter 4 is reset every vertical period as in the third degree.

The output of the up / down counter 3 converted to DC level through the digital analog converter 51 is applied to one end of the analog switch SW _{1 and} the output of the EVR 53 (ELECTRIC VARIABLE RESISTER) receiving the microcomputer data is also analog. It is applied to _one end of the switch SW ₁ to be selected by the mode selection signal.

That is, since the analog switch SW ₁ is switched by the signal selection signal of the microcomputer, the output of the up / down counter 3 or the output of the EVR 53 is selectively applied to the non-inverting terminal (+) of the comparator 54. Will be.

At this time, the EVR 53 receives data from the microcomputer and outputs the DC level. Therefore, if the microcomputer applies the programmed value to the EVR 53 and selects the EVR 53 in the analog switch SW ₁ , the HS driving selector Regardless of the operation of (2), the operation is performed at the programmed electronic shutter speed.

As described above, the present invention detects the illuminance of the photographing state as a driving voltage by using an electronic shutter priority circuit and prioritizes to an appropriate electronic shutter mode to change the electronic shutter speed when capturing a subject with a certain illuminance to obtain a clearer picture quality. It can be effective.

Claims (4)

In a video camera in which an aperture driving voltage detection and driving circuit 1 for driving an aperture by detecting an aperture driving voltage is driven and using a CCD, photographing using the aperture driving voltage and the aperture detection voltage of the driving circuit 1 is performed. An up / down counter for performing an up / down count operation and a holding operation for holding a count value according to the HS drive detection unit 2 for sensing the illuminance being applied and the detected output of the HS drive detection unit 2 ( 3) and an up-counter 4 which is reset every vertical period and up-counts the clock signal of the horizontal period, and the outputs of the up-down counter 3 and the up-counter 4 are compared. A comparator and decoder 5 for outputting a pulse for adjusting the period, an AND gate 6 for logically multiplying the HS pulses of the horizontal period and the output of the comparator and decoder 5, and the output of the end gate 6 Amplification A shutter speed priority circuit of a camera composed of an amplifier (7) that carries a plate voltage (VSUB). 2. The HS driving detector 2 connects the aperture driving voltage to the reference voltage set by the resistors R ₁ , R ₂ , and R ₃ so as to be compared in the comparators 21 and 22. The outputs of the comparators 21 and 22 are applied to the NOA gate 24 and connected to the comparator 23 and the output of the NOA gate 24 is applied to the holding voltage of the up / down counter 3. A camera and shutter speed priority circuit constructed by connecting the output of the comparator 23 to control the counting operation of the up / down counter 23. The method of claim 1, wherein the outputs of the up / down counter 3 and the up counter 4 are converted to the DC level by the digital analog converters 51 and 52, and then applied to the comparator 54. The output of (3) is a shutter speed priority circuit of the camera configured to be switched and applied by the output of the EVR 53 which receives the data of the microcomputer and the analog selection signal SW ₁ by the mode selection signal of the microcomputer. 2. The output of up / down counter 3 and up counter 4 is applied to subtractor 9 until the output of up counter 4 is equal to the output of up / down counter 3. A shutter speed priority circuit of a camera configured to output a pulse for resetting the optical accumulation and output a signal for accumulating light when the output of the up counter (4) is equal to or greater than the output of the up / down counter (3).