JP2007036457A - Imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus the driving method of the imaging section of which is adjusted in a way that the noise canceling capability of a CDS (correlation double sampling) circuit is enhanced and the image quality can be maintained. <P>SOLUTION: The imaging apparatus changes the phase of sample hold timing or decreases drive frequency of a CCD sensor under a condition wherein imaging drive frequency is high and each block of the imaging section is susceptible to receiving effects of load variations in the other blocks so as to enhance the noise cancel capability of the CDS circuit and to maintain the image quality. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an imaging apparatus such as a digital still camera.

  Conventionally, there are many examples of prior applications aimed at reducing power consumption. In the embodiment of the present invention, a digital camera equipped with a CCD sensor is cited as an imaging apparatus using a solid-state imaging device. In recent years, CCD sensors have been reduced in size and increased in pixel count, and the drive frequency of the CCD sensor tends to increase with the increase in pixel count. As the drive frequency increases, the power consumption increases. This is because if the drive frequency is increased, it is necessary to increase the drive current value for operating the drive target.

Here, there is Patent Literature 1 as a prior example. The object of the present invention is to provide a short recovery time and low consumption by slowly driving the CCD and its drive circuit when it is not necessary to use the CCD output, such as during flash charging, menu mode, image playback, and card writing. An object of the present invention is to provide an image pickup apparatus that achieves both power. As described above, the drive frequency of the CCD sensor does not always require a constant frequency, and in a predetermined operation mode, power consumption is reduced by lowering the drive frequency.
Japanese Unexamined Patent Publication No. 2004-23442 (FIG. 6)

  Patent Document 1 cited in the background art reduces the drive frequency of the CCD sensor in accordance with a predetermined operation mode to reduce the power consumption. When used, the drive frequency is not lowered. Under the condition where the CCD drive frequency is high, a large load fluctuation affects the power supply fluctuation of the image pickup unit when driving the optical system and the like, and the ability to cancel the low frequency noise is lowered when the CCD output is sampled and held by the CDS circuit. Noise may appear in the image.

  In order to solve this problem, the present invention operates a solid-state imaging device, a drive signal generation circuit, a driving frequency variable circuit, a correlated double sampling (CDS) circuit, and an A / D conversion circuit that are supplied to the solid-state imaging device in order to read out pixel signals. Imaging that can increase the noise cancellation capability of the CDS circuit and maintain image quality by lowering the drive frequency or changing the phase of the sample and hold timing under operating conditions where fluctuations in the power supply (load fluctuation) become large An object is to provide an apparatus.

  In the present invention, the noise of the CDS circuit is changed by changing the phase of the sample and hold timing or lowering the driving frequency of the CCD sensor under the operating condition in which the fluctuation of the operating power supply (load fluctuation) of the imaging unit becomes large. The driving method of the imaging unit is adjusted so that the canceling ability can be improved and the image quality can be maintained.

In order to solve the above problems, an imaging apparatus according to the present invention provides:
A solid-state imaging device that converts an optical image of a subject into an analog electrical signal, a sample / hold circuit that samples / holds an analog electrical signal after photoelectric conversion read from the solid-state imaging device, and the photoelectric from the solid-state imaging device A drive pulse for reading out the converted analog electric signal, and a drive signal generation circuit for generating a sample / hold pulse to be supplied to the sample / hold circuit,
Under the condition that the load fluctuation is large, the timing of the sample / hold pulse is changed.

  Another feature of the present invention is that the pixel readout rate is changed under conditions of large load fluctuations.

  Another feature of the present invention is that a frequency variable circuit capable of varying the drive frequency of the drive signal generation circuit is further provided, and the drive frequency of the drive signal generation circuit is lowered under a large load fluctuation condition. It is characterized by.

Another feature of the present invention is that
The condition under which the load variation is large is that the optical system is driven.

Another feature of the present invention is that
The condition under which the load variation is large is that the recording medium is being accessed.

Another feature of the present invention is that
The condition with a large load fluctuation is characterized by the fact that the flash is being charged.

Furthermore, as an imaging device of another form of the present invention,
A solid-state image sensor that converts an optical image of a subject into an analog electric signal, a sample / hold circuit that samples / holds an analog electric signal after photoelectric conversion read from the solid-state image sensor, and the sample / hold output Generates an A / D conversion circuit for analog / digital conversion of the signal, a drive pulse for reading out the analog electric signal after photoelectric conversion from the solid-state imaging device, and a sample / hold pulse to be supplied to the sample / hold circuit A drive signal generation circuit, and a solid-state imaging device, the sample / hold circuit, the A / D conversion circuit, and a power supply voltage detection unit of the drive signal generation circuit,
The timing of the sample / hold pulse is changed according to the result of the power supply voltage detecting means.

Another feature of the present invention is that
The pixel readout rate is changed according to the power supply voltage detection result.

Another feature of the present invention is that
The imaging apparatus further includes a frequency variable circuit that can vary a drive frequency of the drive signal generation circuit, and lowers the drive frequency of the drive signal generation circuit according to the power supply voltage detection result.

  According to the present invention, the sampling / hold timing phase is changed or the CCD sensor driving frequency is lowered under an operating condition in which the imaging driving frequency is high and the operation power supply fluctuation (load fluctuation) of the imaging unit is greatly affected. As a result, the noise cancellation capability of the CDS circuit can be enhanced and image quality can be maintained.

  The following six are given as embodiments of the present invention.

  A first embodiment will be described.

  FIG. 1 is a block diagram showing the overall configuration of a digital camera using a CCD sensor as a solid-state image sensor.

  101 is a lens for forming an object on the image plane, 102 is a mechanical diaphragm for controlling the amount of image plane light from the lens, and a zoom mechanism, and 103 is incident on the image plane of light from the lens only for a necessary time. A mechanical shutter 104 for irradiating is a solid-state image sensor for converting an image of the formed light into an electrical signal, and here a CCD sensor is used.

  Reference numeral 105 denotes a timing pulse generation circuit. The types of generated pulses include a read drive pulse necessary for driving the CCD sensor with respect to the CCD sensor, and a CCD output with respect to the CDS circuit 106. Sample / hold pulse for sampling, clamp pulse for clamping the OB (optical black) pixel serving as the black reference of the image to the reference voltage for the clamp circuit 108, and for the AD conversion circuit 109, A pulse for converting the analog imaging signal output from the PGA circuit 107 into a digital signal, and the like are generated.

  A CDS circuit 106 performs correlated double sampling on the CCD output. Reference numeral 107 denotes a PGA circuit for amplifying the output signal of the CDS circuit. A clamp circuit 108 clamps the OB voltage value to a reference voltage. Reference numeral 109 denotes an AD conversion circuit that converts an analog imaging signal output from the PGA circuit 107 into a digital signal.

  Reference numeral 110 denotes a video processing circuit, a video signal processing circuit 111 that processes an imaging signal converted into a digital signal into a luminance and color video signal, a photometric circuit 112 that measures a photometric amount from the level of an input CCD signal, Although not shown in the drawing, it is constituted by a WB circuit that measures the color temperature of a subject from an input CCD signal and extracts information necessary for white balance of the video signal processing circuit.

  Reference numeral 114 denotes a CPU that controls the camera. Based on the information of the photometry circuit, a command for changing the gain of the PGA circuit is issued in order to control sensitivity and exposure, and how the exposure is given to the optical system control circuit 116. And a function for reading out a value adjusted for the camera set from the ROM 117 and setting each part of the digital camera under each condition.

  Reference numeral 117 denotes a memory (ROM) used for various setting information of the digital camera or calculation. A liquid crystal (LCD) 123 is a medium for displaying the video output from the video signal processing circuit 111. Similarly, reference numeral 124 denotes a medium for displaying video output, and a video monitor used as an external output of the imaging apparatus. Reference numeral 115 denotes a power switch of the imaging apparatus.

  Reference numerals 119 and 120 denote shutter switches, which are normally in two stages. SW1 119 is a switch detected in the half-pressed state, and SW2 120 is a switch detected when the switch is pressed to the end. When the switch is pushed to SW1, the digital camera determines the focus, the shutter time for the main exposure, and the aperture opening. The exposure condition is determined from the CCD output when the finder is driven when SW1 is pressed. When SW2 is pressed, actual exposure shooting is performed. The exposure condition at that time is determined by the aperture value and shutter time determined at the time of pressing SW1, and the aperture value is the aperture diameter of the mechanical aperture 102 and the shutter time. The exposure time is determined by the electronic shutter pulse of the CCD, and is determined by the shutter time that ends when the mechanical shutter 103 is closed.

  Reference numeral 121 denotes a power supply battery for operating the imaging apparatus. Similarly, as another operation method, 122 is an AC power source for causing the imaging apparatus to operate. Reference numeral 125 denotes a strobe that emits light to compensate for brightness when the subject is low in luminance. Reference numeral 113 denotes a memory for storing the image processed by the video signal processing circuit 111, and reference numeral 118 denotes a recording medium that outputs the image data stored in the memory 113. Examples include compact flash (registered trademark) and smart media.

  Here, as described in the problem to be solved by the invention, the operation from reading out the pixel signal from the CCD sensor and sampling the read out analog electric signal will be described.

  First, a solid-state imaging device using a four-phase drive interline type all-photodiode readout solid-state imaging device will be described as an example with reference to FIGS. 2, 3, and 4.

  FIG. 2 shows a schematic diagram of an interline type all-photodiode readout solid-state imaging device.

  Reference numeral 201 denotes a photodiode, 202 denotes a vertical charge transfer path, 203 denotes a horizontal charge transfer path, 204 denotes an output unit, and 205 denotes a signal output terminal. The signal charge photoelectrically converted by the photodiode 201 is sent to the vertical charge transfer path 202 by a read pulse, and sequentially transferred in the direction of the horizontal charge transfer path 203 by four-phase drive pulses φV1, φV2, φV3, and φV4. The horizontal charge transfer path 203 transfers the signal charges for one row transferred from the vertical charge transfer path 202 to the output unit 204 by the two-phase drive pulses φH1 and φH2, and a reset gate signal generated on the basis of one pixel. After adding RG at the output unit 204, it is converted into a voltage and output from the signal output terminal 205.

  FIG. 3 shows a part of the color filter array used in the solid-state imaging device of FIG.

  A case is shown in which the first color filter is red (R), the second color filter is green (G), the third color filter is green (G), and the fourth color filter is blue (B). . This array of color filter arrays is called a Bayer array, among the primary color filter arrays, and is a color filter array having high resolution and excellent color reproducibility.

  FIG. 4 schematically shows a part of the solid-state imaging device of FIG. 2, and the color filter array shown in FIG. 2 is arranged in the photodiode 201.

  In the vertical charge transfer path 202, transfer electrodes to which four-phase drive pulses φV1, φV2, φV3, and φV4 are applied are indicated by electrodes V1, V2, V3, and V4, respectively, and in the horizontal charge transfer path 203, a two-phase drive pulse φH1 is provided. And φH2 transfer electrodes are indicated by electrodes H1 and H2. Here, the transfer direction of the vertical charge transfer path 202 is downward, and the transfer direction of the horizontal charge transfer path 203 is leftward. Further, a pulse for reading the signal charge photoelectrically converted by the photodiode 1 to the vertical charge transfer path 202 is applied to V1 which serves as both the vertical charge transfer electrode and the read electrode.

  The above is an example of a method for driving a solid-state imaging device such as a CCD sensor. Here, the driving frequency of the solid-state imaging device is the driving frequency of the two-phase driving pulses φH1 and φH2. Since this frequency is a frequency of one pixel cycle, the frame rate is determined by the driving frequencies of φH1 and φH2. If the two-phase drive pulses φH1 and φH2 are increased, the frame rate is increased, and if it is decreased, the frame rate is decreased.

  Next, a CDS circuit that samples an analog electrical signal photoelectrically converted from a CCD sensor will be described.

  FIG. 5 shows details of the solid-state imaging device 104, the CDS circuit 106, the PGA circuit 107, the clamp circuit 108, and the timing generation circuit 105 in the imaging apparatus of FIG.

  First, an analog electrical signal 501 output from a CCD is input to a circuit 502 called a CDS (correlated double sampling) circuit to remove reset noise, and then input to an offset addition circuit 503 to generate a predetermined offset voltage. After the addition, the offset addition output is input to the variable amplifier 504.

  The operation of the CDS circuit 502 will be described in detail.

  FIG. 6 schematically shows a CCD output signal from the CCD_out 501 and represents two pixels.

  The CCD output signal includes a reset unit 601 added by a reset gate signal RG, a feed-through unit 602 that serves as a black reference for an image, and a signal unit 603 that represents the luminance level of the subject. BLK_SH and SIG_SH are negative pulse signals. BLK_SH is active in the feedthrough section, and SIG_SH is active in the signal section.

  Returning to FIG. 5, when this operation is applied, the CCD output signal from the CCD_out 501 performs the following operation by the sample and hold pulses BLK_SH and SIG_SH output from the timing generator TG510. When BLK_SH is input, the switch 511 is turned on, and the capacitor 512 is charged with the voltage of the feed-through portion serving as the black reference for the CCD pixel signal. This level and a reference voltage VREF 506 described later are compared by BLK_AMP 515 to determine the image black level.

  On the other hand, when SIG_SH is input, the switch 513 is turned on, and the capacitor 514 is charged with the voltage of the signal level of the CCD pixel signal. The difference between this level and the aforementioned image black level is taken as a signal component. This function is performed by CDS_AMP 516. In CDS_AMP 516, since the signal component is obtained by taking the difference between the feed-through portion serving as the black reference of the image and the signal portion, the low-frequency noise superimposed on CCD_out is ideally removed.

  The CDS circuit 502 forms a CDS circuit that uses the predetermined reference voltage VREF input from the reference numeral 506 as a reference for the feedthrough portion of the imaging signal. Similarly, the variable amplifier 504 uses the reference voltage VREF as a direct current of the imaging signal. It constitutes a DC amplifier that is used as a reference for amplification.

  The variable amplifier 504 is a gain variable means for correcting the output sensitivity variation of the CCD_out 501 and switching the sensitivity setting of the imaging apparatus.

  On the one hand, the amplified output signal from the variable amplifier 504 is input to an image processing / recording / display circuit (not shown), and on the other hand, input to the sample hold circuit 507 and read timing of the OB pixel input from 509. The OB level sampled and held by the OB clamp pulse synchronized with the OB is input to the integrating amplifier 505a. The OB pixel refers to a pixel output that is shielded from light in the light receiving pixel portion of the image sensor and does not depend on incident light.

  The integrating amplifier 505a has a predetermined integration time constant by a capacitor 505b and a resistor 505c, and a differential voltage (clamp error voltage) between the sampled and held OB level and a predetermined reference voltage VREF input from the 506. Is integrated with the integration time constant, and the output (deviation amount from the voltage VREF) is input to the offset addition circuit 503 and subtracted by negative feedback control.

  The above is the readout of the pixel signal from the solid-state imaging device and the signal component extraction operation in the correlated double sampling (CDS) circuit. Ideally, the CDS_AMP 516 uses the difference between the feed-through part that is the black reference of the image and the signal part to produce a signal component, so the low-frequency noise superimposed on the CCD_out is ideally removed. The

  Here, the noise cancellation capability in the CDS circuit becomes higher as the active period of the sample and hold pulses BLK_SH and SIG_SH in FIG. 6 becomes longer. When the driving frequency of a solid-state imaging device such as a CCD sensor is increased, the sample and hold is performed at the same frequency. Therefore, the active period of BLK_SH and SIG_SH is shortened, which is a severe condition for the noise canceling capability of CDS. In addition, there is no timing margin in the phase design of the sample and hold pulse, and the settable timing is limited. If the sample and hold pulse cannot properly set the feedthrough part and the signal part, the peak of the signal component is not picked up, or the gradation of the signal component is impaired.

  In addition to this background, when the power supply for the imaging block, such as the power supply for the solid-state image sensor, the timing generation circuit, the correlated double sampling (CDS) circuit, and the A / D conversion circuit, is affected by other external power fluctuations When the power supply fluctuation drives each block of the imaging unit, and the DC level of the CCD pixel signal is greatly disturbed by any of the power supply fluctuations, the CDS circuit 106 cannot perform noise cancellation.

  FIG. 7 is a flowchart illustrating the first embodiment.

  The timing pulse generation circuit 105 supplies a sample / hold pulse of BLK_SH to the feed-through portion of the output signal of the CCD and SIG_SH to the signal portion representing the luminance level of the subject to the CDS circuit 106. As for the phase of the sample and hold pulse, it is assumed that the CCD output signal is properly picked up and noise cancellation is supplied at an effective timing (step 701).

  Here, it is assumed that the user presses the power SW 115 and does not end the camera operation (step 702).

  Here, it is detected whether the mechanical aperture / zoom 102 and the mechanical shutter 103 are driven (step 703). When the optical system is operating, the power load fluctuation of the optical system is large, and the influence of the power fluctuation on other blocks including the imaging block is large. Therefore, when the CPU 114 outputs a control signal to the optical system control circuit 116, it is regarded as a condition in which each power supply fluctuation of the imaging block is large, and the phase of the sample and hold pulse is determined by the power supply fluctuation to the CDS circuit 106. The phase setting is switched so that noise can be reduced (step 704).

  When the CPU 114 stops the control signal to the optical system control circuit 116, it is assumed that the optical system has been stopped (step 705), and the sample / hold pulse timing when the optical system is stopped is set again. Thereafter, the operation of this flowchart is repeated under the condition that the camera operation is continued and the optical system is operating.

  When the camera operation is terminated, the process exits from this flowchart (step 702). When the optical system is not operated, the sample / hold pulse setting is not changed (step 703).

  In the first embodiment, the noise canceling capability of the CDS circuit is improved by changing the phase of the sample and hold timing under the operating condition in which the imaging unit is greatly affected by the power supply fluctuation (load fluctuation) of the optical system, and the image quality is improved. The purpose is to keep.

  The imaging apparatus according to the second embodiment uses FIG. The difference from FIG. 1 used in the first embodiment is that the timing pulse generation circuit 105 has a function of switching the frequency of drive pulses supplied to the solid-state imaging device 104 and the CDS circuit 106.

  Reference numeral 801 denotes a lens for forming an object on the image plane, 802 denotes a mechanical aperture for controlling the amount of image plane light from the lens, and a zoom mechanism, and 803 denotes incidence of light from the lens on the image plane only for a necessary time. A mechanical shutter 804 for irradiating is a solid-state image sensor for converting an image of the imaged light into an electrical signal. Here, a CCD sensor is used.

  Reference numeral 805 denotes a timing pulse generation circuit. The types of pulses generated include a read drive pulse necessary for driving the CCD sensor with respect to the CCD sensor, and a CCD output with respect to the CDS circuit 806. Sample / hold pulse for sampling, clamp pulse for OB (optical black) pixel serving as a black reference of the image to the reference voltage for the clamp circuit 808, and for AD conversion circuit 809, A pulse for converting the analog imaging signal output from the PGA circuit 807 into a digital signal, and the like are generated.

  Reference numeral 826 denotes a drive frequency variable circuit having a function of switching the frequency of drive pulses supplied from the timing pulse generation circuit 805 to the solid-state imaging device 804, the CDS circuit 806, the clamp circuit 808, and the AD conversion circuit 809. A CDS circuit 806 performs correlated double sampling on the CCD output. Reference numeral 807 denotes a PGA circuit for amplifying the output signal of the CDS circuit. Reference numeral 808 denotes a clamp circuit for clamping the OB voltage value to a reference voltage. Reference numeral 809 denotes an AD conversion circuit that converts an analog imaging signal output from the PGA circuit 807 into a digital signal.

  Reference numeral 810 denotes a video processing circuit, a video signal processing circuit 811 that processes an imaging signal converted into a digital signal into a luminance and color video signal, a photometric circuit 812 that measures a photometric amount from the level of an input CCD signal, Although not shown in the drawing, it is constituted by a WB circuit that measures the color temperature of a subject from an input CCD signal and extracts information necessary for white balance of the video signal processing circuit.

  A CPU 814 controls the camera, and issues a command to change the gain of the PGA circuit to control sensitivity and exposure based on the information of the photometry circuit, and how to set the exposure to the optical system control circuit 816. And a function for reading out the value adjusted for the camera set from the ROM 817 and setting each part of the digital camera under each condition.

  Reference numeral 817 denotes a memory (ROM) used for various setting information of the digital camera or calculation. Reference numeral 823 denotes a liquid crystal (LCD) that is a medium for displaying a video output from the video signal processing circuit 811. 824 is a medium for displaying a video output in the same manner, and is a video monitor used as an external output of the imaging apparatus. Reference numeral 815 denotes a power switch of the imaging apparatus.

  Reference numerals 819 and 820 denote shutter switches, which are normally in two stages. SW1 819 is a switch detected in the half-pressed state, and SW2 820 is a switch detected when the switch is pressed to the end. When the switch is pushed to SW1, the digital camera determines the focus, the shutter time for the main exposure, and the aperture opening. The exposure condition is determined from the CCD output when the finder is driven when SW1 is pressed. When SW2 is pressed, actual exposure shooting is performed. The exposure condition at that time is determined by the aperture value and shutter time determined when SW1 is pressed, and the aperture value is the aperture diameter of the mechanical aperture 802 and the shutter time. The exposure time is determined by the electronic shutter pulse of the CCD, and is determined by the shutter time that ends when the mechanical shutter 803 is closed.

  Reference numeral 821 denotes a power supply battery for operating the imaging apparatus. Similarly, as another operation method, reference numeral 822 denotes an AC power source for causing the imaging apparatus to operate. Reference numeral 825 denotes a strobe that emits light to compensate for brightness when the subject is low in brightness. Reference numeral 813 denotes a memory for storing an image processed by the video signal processing circuit 811. Reference numeral 818 denotes a recording medium, which outputs image data stored in the memory 813. Examples include compact flash (registered trademark) and smart media.

  In the second embodiment, the difference from the first embodiment is a means that can be taken to maintain the image quality under the operating condition in which the imaging unit is greatly affected by the power supply fluctuation (load fluctuation) of the optical system. The other camera operations are the same as those in the first embodiment, and are therefore omitted.

  FIG. 9 is a flowchart illustrating the second embodiment.

  The timing pulse generation circuit 805 is a readout drive pulse necessary for driving the CCD sensor with respect to the CCD sensor, a sample hold pulse for correlated double sampling of the CCD output with respect to the CDS circuit 806, and A clamp pulse for clamping an OB (optical black) pixel serving as a black reference of an image to a reference voltage to the clamp circuit 808, and an analog imaging signal output from the PGA circuit 807 to the AD conversion circuit 809 It is assumed that pulses for conversion to a digital signal, etc. are generated based on a reference clock (for example, 30 MHz). This reference clock is set to High_clock (step 901).

  The CDS circuit 806 is supplied with a sample / hold pulse of BLK_SH for the feedthrough portion of the output signal of the CCD and SIG_SH for the signal portion representing the luminance level of the subject. As for the phase of the sample and hold pulse, it is assumed that the CCD output signal is properly picked up and noise cancellation is supplied at an effective timing (step 902).

  Here, it is assumed that the user does not end the camera operation by pressing the power SW 115 (step 903). Here, it is detected whether the mechanical aperture / zoom 802 and the mechanical shutter 803 are driven (step 904). When the optical system is operating, the power load fluctuation of the optical system is large, and the influence of the power fluctuation on other blocks including the imaging block is large. Therefore, when the CPU 814 outputs a control signal to the optical system control circuit 816, it is regarded as a condition that each power supply fluctuation of the imaging block is large, and the reference clock of the timing pulse generation circuit 805 is lowered (for example, 15 MHz).

  This reference clock is set to Low_clock. It is assumed that the drive frequency variable circuit 826 has a function of lowering the reference clock. As the reference clock is lowered, the drive frequency of the two-phase drive pulses φH1 and φH2 of the CCD sensor is lowered. Since this frequency is a frequency of one pixel cycle, the frame rate is lowered.

  As the drive frequency of the CCD sensor decreases, the frequency of the sample and hold pulse for the CDS circuit 806 also decreases, and the phase setting is switched again so that the noise of the sample and hold pulse can be mitigated by power supply fluctuations. (Step 906). As shown in FIG. 6, the noise cancellation capability in the CDS circuit increases as the active period of the sample / hold pulses BLK_SH and SIG_SH increases.

  When the CPU 814 stops the control signal to the optical system control circuit 816, it is detected that the optical system has stopped (step 907), and the timing pulse generation circuit 805 again at the drive frequency (High_clock) when the optical system is stopped. To set the sample and hold pulse timing when the optical system is stopped (High_clock). Thereafter, the operation of this flowchart is repeated under the condition that the camera operation is continued and the optical system is operating.

  If the camera operation is terminated, the process exits this flowchart (step 903). If the optical system is not operated, the driving frequency and sample / hold pulse setting of the timing pulse generation circuit 805 are not changed (step). 904).

  The second embodiment lowers the frequency of the sample-and-hold pulse by lowering the pixel reading rate of the CCD sensor under the operating condition in which the imaging unit is greatly affected by the power supply fluctuation (load fluctuation) of the optical system. The purpose is to increase the noise canceling ability of the CDS circuit and maintain the image quality by widening the hold active section and switching the phase.

  The third embodiment is different from the second embodiment in an operating condition in which the imaging unit is greatly affected by power supply fluctuation (load fluctuation). Since the imaging apparatus and camera operation used in the third embodiment are the same as those in the second embodiment, the description thereof is omitted.

  FIG. 10 is a flowchart illustrating the third embodiment.

  The timing pulse generation circuit 805 is a readout drive pulse necessary for driving the CCD sensor with respect to the CCD sensor, a sample hold pulse for correlated double sampling of the CCD output with respect to the CDS circuit 806, and A clamp pulse for clamping an OB (optical black) pixel serving as a black reference of an image to a reference voltage to the clamp circuit 808, and an analog imaging signal output from the PGA circuit 807 to the AD conversion circuit 809 It is assumed that pulses for conversion to a digital signal, etc. are generated based on a reference clock (for example, 30 MHz).

  This reference clock is set to High_clock (step 10a).

  The CDS circuit 806 is supplied with a sample / hold pulse of BLK_SH for the feedthrough portion of the output signal of the CCD and SIG_SH for the signal portion representing the luminance level of the subject. As for the phase of the sample and hold pulse, it is assumed that the CCD output signal is properly picked up and noise cancellation is also supplied at an effective timing (step 10b).

  Here, it is assumed that the user does not end the camera operation by pressing the power SW 115 (step 10c). Here, it is detected whether the recording medium is accessed (step 10d). When the recording medium is accessed, the operating power load fluctuation of the recording medium is large, and the influence of the power fluctuation on other blocks including the imaging block is large. Therefore, when the CPU 814 outputs a control signal to the recording medium 818 so as to output the image data stored in the memory 813 or the like, the timing pulse generation circuit 805 considers that each power fluctuation of the imaging block is large. The reference clock is reduced (for example, 15 MHz).

  This reference clock is set to Low_clock (step 10e). It is assumed that the drive frequency variable circuit 826 has a function of lowering the reference clock. As the reference clock is lowered, the drive frequency of the two-phase drive pulses φH1 and φH2 of the CCD sensor is lowered. Since this frequency is a frequency of one pixel cycle, the frame rate is lowered.

  As the drive frequency of the CCD sensor decreases, the frequency of the sample and hold pulse for the CDS circuit 806 also decreases, and the phase setting is switched again so that the noise of the sample and hold pulse can be mitigated by power supply fluctuations. (Step 10f).

  As shown in FIG. 6, the noise cancellation capability in the CDS circuit increases as the active period of the sample / hold pulses BLK_SH and SIG_SH increases. When the CPU 814 stops the control signal for the recording medium 818, it is assumed that the recording medium access has been stopped (step 10g), and the timing pulse generation circuit 805 is driven again at the driving frequency (High_clock) at the time of the stop. The sample / hold pulse timing when the recording medium access is stopped (High_clock) is set. Thereafter, the operation of this flowchart is repeated under the condition that the camera operation is continued and the recording medium is accessed.

  If the camera operation is terminated, the process exits this flowchart (step 10c). If the recording medium is not accessed, the driving frequency and sample / hold pulse setting of the timing pulse generation circuit 805 are not changed (step). 10d).

  In the third embodiment, the frequency of the sample and hold pulse is lowered by lowering the pixel reading rate of the CCD sensor under the operating condition in which the imaging unit is greatly affected by power supply fluctuation (load fluctuation) when accessing the recording medium. An object is to increase the noise canceling ability of the CDS circuit and maintain the image quality by widening the sample-and-hold active section and switching the phase.

  The third embodiment is also applicable to the embodiment in which the phase of the sample and hold pulse described in the first embodiment is switched.

  The fourth embodiment is different from the second embodiment in operating conditions in which the imaging unit is greatly affected by power supply fluctuation (load fluctuation). Since the imaging apparatus and camera operation used in the fourth embodiment are the same as those in the second embodiment, the description thereof is omitted.

  FIG. 11 is a flowchart illustrating the fourth embodiment.

  The timing pulse generation circuit 805 is a readout drive pulse necessary for driving the CCD sensor with respect to the CCD sensor, a sample hold pulse for correlated double sampling of the CCD output with respect to the CDS circuit 806, and A clamp pulse for clamping an OB (optical black) pixel serving as a black reference of an image to a reference voltage to the clamp circuit 808, and an analog imaging signal output from the PGA circuit 807 to the AD conversion circuit 809 It is assumed that pulses for conversion to a digital signal, etc. are generated based on a reference clock (for example, 30 MHz). This reference clock is set to High_clock (step 11a).

  The CDS circuit 806 is supplied with a sample / hold pulse of BLK_SH for the feedthrough portion of the output signal of the CCD and SIG_SH for the signal portion representing the luminance level of the subject. As for the phase of the sample and hold pulse, it is assumed that the CCD output signal is properly picked up and noise cancellation is supplied at an effective timing (step 11b).

  Here, it is assumed that the user does not end the camera operation by pressing the power SW 115 (step 11c). Here, it is detected whether the strobe is being charged (step 11d). During strobe charging, the operating power supply load fluctuation is large, and the influence of power supply fluctuation on other blocks including the imaging block is large. Therefore, when the CPU 814 outputs a control signal to the strobe 825 so that the power supply fluctuation of each imaging block is large, the reference clock of the timing pulse generation circuit 805 is lowered (for example, 15 MHz).

  This reference clock is set to Low_clock (step 11e). It is assumed that the drive frequency variable circuit 826 has a function of lowering the reference clock. As the reference clock is lowered, the drive frequency of the two-phase drive pulses φH1 and φH2 of the CCD sensor is lowered. Since this frequency is a frequency of one pixel cycle, the frame rate is lowered.

  As the drive frequency of the CCD sensor decreases, the frequency of the sample and hold pulse for the CDS circuit 806 also decreases, and the phase setting is switched again so that the noise of the sample and hold pulse can be mitigated by power supply fluctuations. (Step 11f).

  As shown in FIG. 6, the noise cancellation capability in the CDS circuit increases as the active period of the sample / hold pulses BLK_SH and SIG_SH increases. When the CPU 814 stops the control signal for the strobe 825, it is assumed that the charging of the strobe is completed (step 11g), and the timing pulse generation circuit 805 is driven again at the driving frequency (High_clock) when the strobe charging is stopped. And set the sample-and-hold pulse timing during High_clock. Thereafter, the operation of this flowchart is repeated under the condition that the camera operation is continued and the strobe is charged.

  If the camera operation is terminated, the process exits this flowchart (step 11c). If the strobe is not charged, the drive frequency and sample / hold pulse setting of the timing pulse generation circuit 805 are not changed. (Step 10d).

  The fourth embodiment lowers the frequency of the sample and hold pulse by lowering the pixel reading rate of the CCD sensor under the operating condition in which the imaging unit is greatly affected by power supply fluctuation (load fluctuation) during strobe charging. An object is to increase the noise canceling ability of the CDS circuit and maintain the image quality by widening the sample and hold active section and switching the phase.

  The fourth embodiment is also applicable to the embodiment in which the phase of the sample and hold pulse described in the first embodiment is switched.

  In the fourth embodiment, the imaging apparatus of the first embodiment is used. In the first embodiment, the operating condition in which the imaging unit is greatly influenced by the power supply fluctuation (load fluctuation) is set to the time when the optical system is driven. In this embodiment, the CPU controls the power fluctuation of the imaging section. The difference is that the phase of the sample and hold pulse is changed depending on the result of detection and comparison with a predetermined threshold.

  In addition to the functions of the first embodiment, the imaging apparatus used in the fourth embodiment has the following functions.

  In the image pickup apparatus of FIG. 1, the CPU 114 can detect the operation power supply voltages of the solid-state image pickup element 104, the timing generation circuit 105, the CDS circuit 106, the PGA circuit 107, the clamp circuit 108, and the AD conversion circuit 109.

  Specifically, as shown in FIG. 12, the power supply lines of the solid-state imaging device 12a, the timing generation circuit 12b, the CDS circuit 12c, the PGA circuit 12d, the AD conversion circuit 12e, and the clamp circuit 12f are sequentially connected to AD [0], AD [ 1], AD [2], AD [3], AD [4], and AD [5] are input to assigned AD ports.

  FIG. 13 shows a correspondence table between the power supply voltage value [V] and each AD port, AD [x] (x = 0 to 5) [LSB]. As an example, each AD port has a resolution of 8 bits and a maximum input voltage of 4 [V].

  Here, it is assumed that the operation power supply voltage of the timing generation circuit 105, the CDS circuit 106, the PGA circuit 107, the clamp circuit 108, and the AD conversion circuit 109 is type 3.0V drive, and the solid-state imaging device 104 is type 12V drive. Since the operating power supply voltage of the solid-state imaging device is typ12V, when the resistor 12g is designed to be 300 kΩ and the resistor 12h is designed to be 100 kΩ to input to AD [0], the operating power supply value can be detected in the same manner as other ports. Of course, if the operating power supply voltage of the ports AD [1] to AD [4] exceeds the maximum input voltage of the AD port, the operating power supply can be detected by resistance division. In this case, it is necessary to design while examining the accuracy of the resistor, the relationship between the resistance divided voltage and the resolution.

  In addition, since the camera operation is the same as that of the first embodiment, a description thereof will be omitted.

  FIG. 14 is a flowchart illustrating the fifth embodiment.

  The timing pulse generation circuit 105 supplies a sample / hold pulse of BLK_SH to the feed-through portion of the output signal of the CCD and SIG_SH to the signal portion representing the luminance level of the subject to the CDS circuit 106. As for the phase of the sample and hold pulse, it is assumed that the CCD output signal is properly picked up and noise cancellation is supplied at an effective timing (step 14a).

  Here, it is assumed that the user presses the power SW 115 and does not end the camera operation (step 14b). Here, the operation power supply voltages of the solid-state imaging device 104, the timing generation circuit 105, the CDS circuit 106, the PGA circuit 107, the clamp circuit 108, and the AD conversion circuit 109 are detected by an AD port. As an example, the value of the power supply voltage fluctuation of the CDS circuit 106 is set as a condition for changing the phase of the sample and hold pulse.

  Assume that V_det = 230 [LSB] is detected by the port AD [2] in FIG. That is, the voltage value of the CDS circuit 106 is 3.984375 [V] (step 14c). Here, it is assumed that the CPU 114 has in advance a range of V_ref = 160 [LSB] to 224 [LSB] as the threshold range of the allowable power supply voltage value of the CDS circuit 106 in the ROM 117. That is, the allowable voltage value of the CDS circuit 106 is 2.5 [V] to 3.5 [V]. Since the previously detected value is V_det = 230 [LSB], it is assumed that it is outside the allowable power supply voltage range of the CDS circuit 106, and is subject to some large power supply fluctuation (step 14d).

  In this case, the phase setting of the sample / hold pulse is switched with respect to the CDS circuit 106 so that noise due to power supply fluctuation can be reduced (step 14e). Thereafter, the camera operation is continued and repeated, and the operation of this flowchart is repeated.

  If the camera operation is terminated, the process exits this flowchart (step 14b). If the allowable power supply voltage range is not exceeded, the sample / hold pulse setting is not changed (step 14d).

  In this embodiment, only the power fluctuation of the CDS circuit 106 is used as the sample / hold pulse phase switching condition. However, the solid-state imaging device 104, timing generation circuit 105, CDS circuit 106, PGA circuit 107, clamp circuit 108, AD It is free to determine which combination is set as the phase switching condition including the power supply fluctuation of the conversion circuit 109.

  In the fifth embodiment, after detecting whether or not the imaging unit is affected by some large power supply fluctuation (load fluctuation), when it is determined that the imaging section is affected by the power supply fluctuation, the phase of the sample and hold timing is changed, and the CDS circuit The purpose is to maintain image quality by enhancing the noise canceling ability.

  In the sixth embodiment, the imaging apparatus of the second embodiment is used. In the second embodiment, the operating condition in which the imaging unit is greatly affected by the power supply fluctuation (load fluctuation) is set to the time when the optical system is driven. In this embodiment, the CPU controls the power fluctuation of the imaging section. The difference is that the timing pulse generation circuit 805 has a function of switching the frequency of the drive pulse supplied to the solid-state imaging device 804 and the CDS circuit 806 depending on the result of detection and comparison with a predetermined threshold value.

  Other camera operations are the same as those in the fifth embodiment, and are therefore omitted.

  FIG. 15 is a flowchart illustrating the sixth embodiment.

  The timing pulse generation circuit 805 is a readout drive pulse necessary for driving the CCD sensor with respect to the CCD sensor, a sample hold pulse for correlated double sampling of the CCD output with respect to the CDS circuit 806, and A clamp pulse for clamping an OB (optical black) pixel serving as a black reference of an image to a reference voltage to the clamp circuit 808, and an analog imaging signal output from the PGA circuit 807 to the AD conversion circuit 809 It is assumed that pulses for conversion to a digital signal, etc. are generated based on a reference clock (for example, 30 MHz). This reference clock is set to High_clock (step 15a).

  The timing pulse generation circuit 805 supplies a sample / hold pulse of BLK_SH to the feedthrough portion of the output signal of the CCD and SIG_SH to the signal portion representing the luminance level of the subject to the CDS circuit 806. As for the phase of the sample and hold pulse, it is assumed that the CCD output signal is properly picked up and noise cancellation is supplied at an effective timing (step 15b).

  Here, it is assumed that the user presses the power SW 115 and does not end the camera operation (step 15c). Here, the operation power supply voltages of the solid-state imaging device 804, the timing generation circuit 805, the CDS circuit 806, the PGA circuit 807, the clamp circuit 808, and the AD conversion circuit 809 are detected by the AD port. As an example, the value of the power supply voltage fluctuation of the CDS circuit 806 is set as a condition for changing the phase of the sample and hold pulse.

  Assume that V_det = 230 [LSB] is detected by the port AD [2] in FIG. That is, the voltage value of the CDS circuit 806 is 3.984375 [V] (step 15d). Here, it is assumed that the CPU 814 previously has a range of V_ref = 160 [LSB] to 224 [LSB] as the threshold range of the allowable power supply voltage value of the CDS circuit 806 in the ROM 817. That is, the allowable voltage value of the CDS circuit 806 is 2.5 [V] to 3.5 [V]. Since the previously detected value is V_det = 230 [LSB], it is assumed that the value is outside the allowable power supply voltage range of the CDS circuit 806, and is assumed to have undergone some large power supply fluctuation (step 15e).

  In this case, it is considered that the power supply fluctuation is large, and the reference clock of the timing pulse generation circuit 805 is lowered (for example, 15 MHz). This reference clock is set to Low_clock (step 15f). It is assumed that the drive frequency variable circuit 826 has a function of lowering the reference clock. As the reference clock is lowered, the drive frequency of the two-phase drive pulses φH1 and φH2 of the CCD sensor is lowered. Since this frequency is a frequency of one pixel cycle, the frame rate is lowered.

  As the drive frequency of the CCD sensor decreases, the frequency of the sample and hold pulse for the CDS circuit 806 also decreases, and the phase setting is switched again so that the noise of the sample and hold pulse can be mitigated by power supply fluctuations. (Step 15g).

  As shown in FIG. 6, the noise cancellation capability in the CDS circuit increases as the active period of the sample / hold pulses BLK_SH and SIG_SH increases.

  Thereafter, the camera operation is continued and repeated, and the operation of this flowchart is repeated.

  If the camera operation is terminated, the process exits this flowchart (step 15c). If the allowable power supply voltage range is not exceeded, the sample / hold pulse setting is not changed (step 15e).

  In the sixth embodiment, after detecting whether the imaging unit is affected by some large power supply fluctuation (load fluctuation) and then determining that the power supply fluctuation has occurred, the pixel reading rate of the CCD sensor is lowered. An object of the present invention is to increase the noise canceling capability of the CDS circuit and maintain image quality by lowering the frequency of the sample and hold pulse, widening the sample and hold active period, and switching the phase.

It is a figure explaining the imaging device whole view concerning the 1st, 5th Example of this invention. It is a figure explaining the reading method of the CCD sensor which concerns on all the Examples of this invention. It is a figure explaining the reading method of the CCD sensor which concerns on all the Examples of this invention. It is a figure explaining the reading method of the CCD sensor which concerns on all the Examples of this invention. It is a figure explaining CDS operation concerning all the examples of the present invention. It is a figure explaining CDS operation concerning all the examples of the present invention. It is a flowchart which concerns on the 1st Example of this invention. It is a figure explaining the imaging device whole view concerning the 2nd, 3rd, 4th, 6th Example of this invention. It is a flowchart which concerns on the 2nd Example of this invention. It is a flowchart which concerns on the 3rd Example of this invention. It is a flowchart which concerns on the 4th Example of this invention. It is a figure explaining the power supply detection means which concerns on the 5th, 6th Example of this invention. It is a figure explaining the power supply detection means which concerns on the 5th, 6th Example of this invention. It is a flowchart which concerns on the 5th Example of this invention. It is a flowchart which concerns on the 6th Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Lens 102 Mechanical aperture / zoom 103 Mechanical shutter 104 Solid-state image sensor 105 Timing pulse generation circuit 106 CDS circuit 107 PGA circuit 108 Clamp circuit 109 AD conversion circuit 110 Video processing circuit 111 Video signal processing circuit 112 Photometry circuit 113 Memory 114 CPU
115 Power switch
116 Optical system control circuit 117 ROM
118 Recording medium 119 Shutter switch (SW1)
120 Shutter switch (SW2)
121 battery 122 AC power supply 123 LCD
124 Video OUT
125 Strobe 201 Photodiode 202 Vertical charge transfer path 203 Horizontal charge transfer path 204 Output unit 205 Signal output terminal 501 CCD output 502 CDS circuit 503 Offset addition circuit 504 Variable amplifier 505 Clamp circuit 505a Integration amplifier 505b Capacitor 505c Resistance 506 Reference voltage VREF
507 Sample hold circuit 508 Image processing / recording / display circuit 509 (not shown) OB clamp pulse 510 Timing generator (TG)
511 switch 512 capacitor 513 switch 514 capacitor 515 BLK_AMP
516 CDS_AMP
601 Reset unit 602 Feedthrough unit 603 Signal unit 801 Lens 802 Mechanical aperture / zoom 803 Mechanical shutter 804 Solid-state imaging device 805 Timing pulse generation circuit 806 CDS circuit 807 PGA circuit 808 Clamp circuit 809 AD conversion circuit 810 Video processing circuit 811 Video signal processing Circuit 812 Photometry circuit 813 Memory 814 CPU
815 Power SW
816 Optical system control circuit 817 ROM
818 Recording medium 819 Shutter switch (SW1)
820 Shutter switch (SW2)
821 Battery 822 AC power supply 823 LCD
824 Video OUT
825 Strobe 826 Drive frequency variable circuit 12a Solid-state imaging device 12b Timing generation circuit 12c CDS circuit 12d PGA circuit 12e AD conversion circuit 12f Clamp circuit 12g CPU

Claims (9)

A solid-state imaging device that converts an optical image of a subject into an analog electrical signal, a sample / hold circuit that samples / holds an analog electrical signal after photoelectric conversion read from the solid-state imaging device, and the photoelectric from the solid-state imaging device A drive pulse for reading out the converted analog electric signal, and a drive signal generation circuit for generating a sample / hold pulse to be supplied to the sample / hold circuit,
An image pickup apparatus, wherein the timing of the sample / hold pulse is changed under a condition with a large load fluctuation.   The imaging apparatus according to claim 1, wherein a pixel readout rate is changed under a condition where the load fluctuation is large.   The image pickup apparatus further includes a frequency variable circuit capable of changing a drive frequency of the drive signal generation circuit, and lowers the drive frequency of the drive signal generation circuit under a condition with a large load fluctuation. Imaging device.   The imaging apparatus according to claim 1, wherein the condition with a large load fluctuation is when an optical system is driven.   The imaging apparatus according to claim 1, wherein the condition under which the load fluctuation is large is when a recording medium is accessed.   The imaging apparatus according to claim 1, wherein the condition under which the load fluctuation is large is during strobe charging. A solid-state image sensor that converts an optical image of a subject into an analog electric signal, a sample / hold circuit that samples / holds an analog electric signal after photoelectric conversion read from the solid-state image sensor, and the sample / hold output Generates an A / D conversion circuit for analog / digital conversion of the signal, a drive pulse for reading out the analog electric signal after photoelectric conversion from the solid-state imaging device, and a sample / hold pulse to be supplied to the sample / hold circuit A drive signal generation circuit, and a solid-state imaging device, the sample / hold circuit, the A / D conversion circuit, and a power supply voltage detection unit of the drive signal generation circuit,
An image pickup apparatus, wherein the timing of the sample / hold pulse is changed according to the result of the power supply voltage detection means.   8. The imaging apparatus according to claim 7, wherein a pixel readout rate is changed according to the power supply voltage detection result.   The image pickup apparatus further includes a frequency variable circuit capable of changing a drive frequency of the drive signal generation circuit, and lowers the drive frequency of the drive signal generation circuit according to the power supply voltage detection result. The imaging device described.

Images