JPH0514470B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a fixed imaging device, and particularly to a solid-state imaging device that performs exposure control on a solid-state imaging device such as a CCD.

(b) Conventional technology Exposure control of an imaging device, such as a television camera, is
Normally, the iris control circuit controls the mechanical diaphragm mechanism inside the lens barrel, which has been a factor in increasing costs.

For this reason, in solid-state imaging devices such as television cameras that use CCD solid-state imaging devices, attempts have been made to electronically control automatic exposure (auto iris) by utilizing the driving principle of solid-state imaging devices.

For example, in Utility Model Application No. 61-139527, in a frame transfer type CCD solid-state image sensor, in the middle of the photoelectric conversion period, the image charge that has been photoelectrically converted and accumulated in the light receiving area of this element is read out as an image signal. It has been proposed to provide an exposure control means that transfers and discharges image charges in the opposite direction to the transfer direction for this purpose, and accumulates image charges only during the remaining photoelectric conversion period (effective photoelectric conversion period). Therefore, according to such an exposure control means, a good exposure state can be obtained by changing the timing of reverse charge transfer according to the brightness of the subject.

However, in such conventional devices, one vertical scanning line period corresponds to one photoelectric conversion period, and the reverse transfer timing is always set for each period, so the effective photoelectric conversion period is Vertical blanking period was limited to below.

Therefore, although the conventional apparatus is equipped with an auto-iris function, it has the disadvantage of resulting in insufficient exposure when imaging a dark subject.

(c) Problems to be Solved by the Invention The present invention has been made in view of the above-mentioned disadvantages, and provides a fixed imaging device equipped with an auto-iris function that allows unlimited expansion of the effective photoelectric conversion period and completely eliminates underexposure. It provides equipment.

(d) Means for Solving the Problems The solid-state imaging device of the present invention includes an imaging element that obtains an image signal by photoelectrically converting a received image;
A drive circuit that reads and drives the photoelectric conversion charge of the solid-state image sensor after discharging it, and a control circuit that sets the charge discharge drive timing and the charge readout drive timing of this drive circuit and controls the effective photoelectric conversion period between the two timings. This control circuit includes a first up-down counter that variably sets the charge discharge drive timing during a specific vertical scanning line period using a horizontal scanning line period number, and a charge readout drive timing after the charge discharge drive timing. a second up-down counter in which the number of vertical scanning line periods is variably set; The first up-down counter counts up when the value of the first up-down counter cycles from the maximum value to the minimum value.

(E) Effects According to the present invention, the first up-down counter variably sets the charge discharge drive timing during a specific vertical scanning line period using the horizontal scanning line period number, and the charge readout drive after the charge discharge drive timing. A second up-down counter is provided in which the number of vertical scanning line periods up to the timing is variably set, and the second up-down counter is configured so that the value of the first up-down counter during countdown cycles from a minimum value to a maximum value. Since the first up-down counter during counting up cycles from the maximum value to the minimum value, it counts down, so the period between the charge discharge drive timing and the charge readout drive timing, that is, The effective photoelectric conversion period can be set for a long time over multiple vertical blanking periods, and even over multiple vertical blanking periods, the effective photoelectric conversion period can be set in units of horizontal scanning line periods, or in units of an appropriate number of horizontal scanning line periods. The length of the conversion period can be expanded or contracted.

(F) Embodiment FIG. 1 shows the configuration of an embodiment of the solid-state imaging device of the present invention.

In the same figure, S is light receiving area 1 and storage area 2.
It is a frame transfer type CCD solid-state image sensor consisting of a horizontal register 3 and a light receiving area 1.
After the image charges obtained by photoelectric conversion in units of one screen are once transferred and accumulated in the storage area 2, they are output as image signals via the horizontal register 3 in units of one scanning line during the horizontal blanking period. This image signal is subjected to signal processing such as sample hold and amplification in the signal processing circuit 4, and is output as a video signal.

The CCD solid-state image sensor S is driven by a clock, and the light receiving area 1 is provided with a four-phase forward transfer clock Φ _F from a readout transfer clock generation circuit 5 or a discharge transfer clock generation circuit 6.
A four-phase reverse transfer clock _ΦB is supplied at predetermined timing. (These timings will be described later.) On the other hand, the storage area 2 is supplied with a four-phase transfer clock _ΦS from the storage and transfer clock generation circuit 7, and the horizontal register 3 is supplied with a four-phase transfer clock ΦS from the horizontal transfer clock generation circuit 8. A two-phase transfer clock Φ _H is supplied. Note that these clock generation circuits 5, 6, 7, and 8 operate based on a basic clock from the same oscillation means (not shown), and also operate on the basis of a horizontal blanking pulse generation means (not shown) based on this basic clock. ) is the horizontal blanking pulse
A vertical blanking pulse generating means (not shown) generates _{a vertical blanking pulse P V based} on the horizontal blanking pulse P _H.

Furthermore, 40 is an integrating circuit that integrates one screen worth of image signal Y(t) [luminance signal or luminance components of R, G, B signals including this] from the signal processing circuit 4, and this integrated value are compared with predetermined reference values in first and second comparison circuits 9 and 10, respectively.
That is, the first comparison circuit 9 compares the above integral value with a reference value Vr1 indicating the upper limit of the appropriate exposure range, and stores the comparison result in the first flip-flop 11. Further, the second comparison circuit 10 compares the integrated value with a reference value Vr2 indicating the lower limit of the appropriate exposure range, and converts the comparison result into a second comparison circuit.
The data is stored in the flip-flop 12 of the flip-flop 12.

A decoder 13 decodes the 2-bit stored value of the first and second flip-flops, and outputs an exposure limit signal CLOSE when the exposure state is above the proper exposure range, and outputs an exposure promotion signal when the exposure state is below the proper exposure range. OPEN is output, and when the exposure is within the appropriate range, no signal is output to maintain the current status.

The feature of the apparatus according to the embodiment of the present invention shown in FIG. .

The control circuit Q sets the number n of vertical scanning line periods of the effective photoelectric conversion period E spanning a plurality of vertical scanning line periods nV, that is, the number n of vertical blanking pulses R _V until the solid-state image sensor S is read and driven. A V register counter 19 configured as an up-down counter, a V counter 20 that counts vertical blanking pulses R _V , and a read drive timing signal T _F for detecting coincidence between these two counters and activating the read transfer clock generation circuit 5 for a predetermined period. The first V comparator circuit 21 of the effective photoelectric conversion period is provided.
An H register counter 1 having an up-down counter configuration sets a horizontal scanning line number m indicating a horizontal blanking period during which the fixed image pickup element S is ejected and driven in a vertical scanning line period V of , in steps of, for example, V/32.
4. An H counter 15 that counts horizontal blanking pulses P _H , and an H comparison circuit 16 that detects coincidence between these two counters and outputs a discharge drive timing signal T _B for starting the discharge transfer clock generation circuit 6 for a predetermined period. We are prepared.

In the control circuit Q having such a counter configuration, the exposure limit signal CLOSE obtained from the decoder 13,
and the exposure promotion signal OPEN become the up signal U and down signal D of the H register counter 14, respectively. Furthermore, the AND18 signal of the ripple carry signal C output when the value of this H register counter 14 counts up from the maximum value [FF] to the minimum value [00] and the above exposure limit signal CLOSE, and the maximum value from the minimum value [00]. The AND17 signal of the ripple borrow signal B output when counting down to [FF] and the exposure promotion signal OPEN becomes the down signal D and up signal U of the V register counter 19, respectively. On the other hand, the H counter 15 that counts the horizontal blanking pulses P _H and the V counter 20 that counts the vertical blanking pulses P _V are both up counters that stop while holding this value when they count up to the maximum value. It is configured to be reset by the read drive timing signal T _F obtained from the V comparison circuit 21. Incidentally, this timing signal _TF also functions as a signal acquisition clock for the flip-flops 11 and 12, and is also used as a trigger for a write signal of a memory circuit 23, which will be described later.

Next, the operation will be explained based on the timing diagram of FIG. In the operation example shown in the figure, the exposure is within the proper range at the effective photoelectric conversion period E which is shorter than the first vertical scanning line period V, the exposure becomes insufficient at timing t ₀ , and the underexposure is detected at timing t ₁ and the exposure is promoted. The figure shows a case where appropriate exposure is detected during an effective photoelectric conversion period E which is longer than one vertical scanning line period V at timing _t2 . Further, in the case of the figure, for convenience of understanding, a system is used in which the value of the H register counter 14 is increased or decreased in steps of V/4, and the effective photoelectric conversion period E is expanded or contracted in steps of V/4.

In the proper exposure state up to timing t ₀ , the horizontal scanning line number corresponding to 3V/4 for each period V is stored in the H register counter 14, and [1] is stored in the V register counter, and it is stable in this state. are doing. That is, at the 3V/4 point in each period V, the H register counter 14 and the H counter 15 match, and the H comparator circuit 16 outputs the discharge drive timing signal T _B , which causes the discharge transfer clock generation circuit 6
The reverse transfer clock Φ _B from the solid-state image sensor S
The imaging charge that has been photoelectrically converted in the light receiving area 1 is discharged to the outside and is destroyed. and a vertical blanking pulse after a period of V/4.
When the V counter 20 counts up from [0] to [1] at P _V , this value matches the value of the V register counter 19, and the V comparator circuit 21 outputs the read drive timing signal T _F. Therefore, the forward transfer clock Φ _F from the read transfer clock generation circuit 5 is supplied to the solid-state image sensor S, and the image pickup charge photoelectrically converted during the effective photoelectric conversion period E of V/4 in the light receiving area 1 is stored in the storage area. transferred to 2,
In the next period V, from the horizontal register 3 to the signal processing circuit 4
A video signal Y(t) shown in V waveforms (a) and (b) in the appropriate exposure range is obtained through the video signal Y(t). These V waveforms (A) and (B) are within the appropriate exposure range, and as a result of the comparison process of their integral values, there is no signal output from the decoder 13, so the values stored in both register counters 14 and 19 are not increased or decreased. . As a result, the period E in the next period V is not expanded or contracted, and E=V/4 is maintained.

In such a proper exposure state, if the illuminance of the subject decreases at timing t ₀ during period V of the V waveform (b) and the exposure becomes insufficient, the V waveform of the next period V
(C) results in a significant decrease in brightness.

Insufficient exposure is detected during the vertical blanking period at timing t ₁ following this V waveform (c), and the decoder 13
outputs the exposure promotion signal OPEN and decreases the value of the H register counter 14 by V/4. As a result, the discharge drive timing T _B in the next period V is advanced by V/4, so the effective photoelectric conversion period E=V/
It becomes 2.

When the value of the H register counter 14 continues to decrease in this way and the effective photoelectric conversion period E extends to E=Vm, that is, when the H register counter 14 counts down from the minimum value [00] to [FF], H
Ripple borrow signal B from register counter 14
is output and the V register counter 19 is counted up to become the value [2]. Therefore, the first vertical blanking pulse P _V that occurs immediately after this
At the next point, the discharge drive timing signal T _B is not obtained from the V comparator circuit 21, and the next second pulse
Since this discharge drive timing signal T _F is obtained for the first time at P _V , the forward transfer clock Φ _F from the read transfer clock generation circuit 5 is supplied to the solid-state image sensor S at this timing. As a result, the imaged charge photoelectrically converted in the light receiving area 1 during the effective photoelectric conversion period E=V is transferred to the storage area 2, and is transferred to the storage area 2 during the effective photoelectric conversion period E=V.
V from the horizontal register 3 through the signal processing circuit 4.
A video signal Y(t) shown in waveform (g) is output. still,
Since the read drive timing signal T _F is not obtained at the time of the first vertical blanking pulse R _V mentioned above, during the period V until the read drive timing signal T _F is obtained by the second pulse P _V. Since no image signal is output, there is no V waveform in the video signal Y(t) from the signal processing circuit 4.

If the underexposure condition continues further, as long as the exposure promotion signal OPEN is output from the decoder 13, the value of the H register counter 14 will further decrease by V/4 minutes, and the effective photoelectric conversion period E will be extended by V/4 minutes. . Therefore, the level of the V waveform of the video signal Y(t) will gradually increase.

Now, if the V waveform (H) reaches the appropriate exposure range, _this V waveform will be
(H) The appropriate exposure is detected, and the decoder 13 stops outputting the exposure promotion signal OPEN. Therefore, the value of the H register counter 14 holds the horizontal scanning line number corresponding to 3V/2, and the V register counter 19 also holds [2], so the effective photoelectric conversion period E is 3V/2. is set to

As described above, the no-signal period V of the video signal Y(t) subjected to long-time exposure processing is interpolated by the interpolation means consisting of the A/D converter 22, the memory circuit 23, and the D/A converter 24. That is, the memory circuit 23 uses the read drive timing signal T _F as a trigger to control V for a period of 1V.
While storing the waveform, the stored V waveform is output for each period V, and through this interpolation process, the V waveform of the video signal Y(t) in FIG. No signal V following
A video signal Y(t) is obtained in which these V waveforms are repeatedly inserted during the period.

In the operation example shown in FIG. 2 described above, the V register counter 19 is counted up in conjunction with the countdown operation of the H register counter 14 in an underexposure state, but in an overexposure state, the H register counter 19 is counted up. The V register counter 19 is counted down in conjunction with the count up operation of 14, and this overexposure state is resolved.

(G) Effects of the Invention As is clear from the above description, the solid-state imaging device of the present invention divides the period between the charge discharge drive timing and the charge readout drive timing, that is, the effective photoelectric conversion period into a plurality of vertical scanning line periods. Moreover, even though the photoelectric conversion period extends over a plurality of vertical scanning line periods, this period can be controlled in units of horizontal scanning line periods or in units of an appropriate number of horizontal scanning line periods. Therefore, according to the present invention, it is possible to properly control the iris from extremely dark objects to bright objects, and furthermore, it is possible to perform delicate iris control in steps finer than the vertical scanning line period.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the solid-state imaging device of the present invention, and FIG. 2 is a signal timing diagram. S...solid-state image sensor, Q...control circuit, 5...
Read transfer clock generation circuit, 6...Ejection transfer clock generation circuit, 7...Storage transfer clock generation circuit, 8...Horizontal transfer clock generation circuit, 9, 10
... Comparison circuit, 11, 12 ... Flip-flop, 13 ... Decoder, 14 ... H register counter, 15 ... H counter, 16 ... H comparison circuit, 19 ... V register counter, 20 ... V counter, 21...V comparison circuit.

Claims (1)

[Scope of Claims] 1. An image sensor that obtains an image signal by photoelectrically converting a received image, a drive circuit that performs readout drive after discharging photoelectric conversion charges of the solid-state image sensor, and It consists of a control circuit that sets the charge discharge drive timing and the charge readout drive timing and controls the effective photoelectric conversion period between the two timings, and the control circuit horizontally controls the charge discharge drive timing between specific vertical scanning lines. A first up-down counter that is variably set by the scanning line number, and a first up-down counter that counts up when the value of the first up-down counter during counting cycles from the minimum value to the maximum value, and the first up-down counter that is counting up. and a second up-down counter that counts down when the counter value circulates from the maximum value to the minimum value and variably sets the number of vertical scanning line periods from the charge discharge drive timing to the charge readout drive timing. A fixed imaging device characterized by: