JP2664577B2 - Video camera - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera which electronically controls an iris (aperture) at the time of normal photographing using a variable speed electronic shutter function of a solid-state image pickup device.

[0002]

2. Description of the Related Art Conventionally, in a video camera having a solid-state image pickup device such as a CCD, a photographing operation is performed by effectively utilizing a limited dynamic range of the image pickup device, and in order to reproduce an appropriate image, continuous photographing of a moving image state is performed. In the normal photographing operation, the photographing light amount is automatically controlled to an appropriate value by iris control.

Conventionally, the control of the photographing light amount has been performed by mechanical iris control using an auto iris lens or the like, but at present, it is significantly more expensive than mechanical iris control in various aspects such as price and reliability. This is done with excellent electronic iris control.

This electronic iris control is described in pages 63-64 of the magazine "Nikkei Microdevices, October 1987" (published by Nikkei BP) and in the magazine "Television Engineering, 1988".
Charge using the variable speed electronic shutter function of the solid-state imaging device described on pages 49 to 54 of “November Issue (No. 448)” (published by Electronic Technology Publishing Co., Ltd.) in units of horizontal scanning period for each field. This is performed by changing the sweeping period of and variably adjusting the signal charge accumulation time.

[0005] Next, the solid-state imaging device is replaced with an interline C
A conventional video camera which performs iris control by a variable-speed electronic shutter function that discharges unnecessary charge to a CCD substrate in the same manner as a vertical overflow drain (VOFD) every horizontal blanking period as a CD, with reference to FIGS. explain.

As shown in FIG. 2, a photographed image signal (CCD output) of each field formed by receiving light by the CCD 1 is
After the unnecessary components are removed by the sample / hold circuit 2, the video signal is supplied to the video processing circuit 4 via the AGC amplifier 3, processed into a video signal by the circuit 4, and supplied from the video output terminal 5 to the subsequent recording circuit and the like. Is done.

Further, the CCD of the sample / hold circuit 2
The output signal is also supplied to the iris signal processing circuit 6, and the signal of the CCD 1 is amplified by the signal amplification, inversion, and detection of the processing circuit 6.
An iris signal having a voltage level corresponding to the photographing light amount (incident light amount) is formed. It should be noted that the level of the iris signal changes inversely to the amount of photographing light based on the inversion processing.

The iris signal is supplied to an iris output terminal 7 and an electronic iris control circuit 8, and the control circuit 8
Is based on an iris signal and a timing pulse such as a vertical blanking pulse and a horizontal blanking pulse of the timing control circuit 9, and detects an excessive or insufficient amount of photographing light from an appropriate range in each field and excessively increases the shutter speed (too fast). ,
Determine if it is too small (too late).

Further, the control circuit 8 determines (corrects) the shutter speed based on the result of this determination, and forms and outputs one electronic shutter pulse in each horizontal blanking period for sweeping out unnecessary charges in each field. . This pulse is usually about +5 V based on the output rating of the control circuit 8 having an IC configuration.

Therefore, the electronic shutter pulse of the control circuit 8 is amplified by the electronic shutter drive circuit 10 to about ten and several volts necessary for driving the CCD and supplied to the CCD 1. The CCD 1 is driven by a vertical and horizontal shift register drive, a reset gate drive, and a drive circuit 10 of the CCD drive circuit 11.
, An image signal of each field is taken out.

That is, during the unnecessary charge sweeping period of each field, the light receiving charge of the CCD 1 is swept out by the electronic shutter pulse in units of a horizontal scanning period, and the light receiving charge of the CCD 1 during the remaining period (signal accumulation period) after the sweeping out period. It is extracted as a photographed image signal.

[0012] Depending on the length of the unnecessary charge sweeping period in which the electronic shutter pulse is supplied, for example, in the case of the NTSC system, the shutter speed is 1/60 second (one field).
The iris at the time of normal photographing is automatically controlled by closed loop control so that the photographing light amount becomes an appropriate amount in a range of up to 63.5 μsec (one horizontal scanning period) for each field in units of horizontal scanning period. You. When an electronic shutter pulse (sweep-out pulse) is generated outside the horizontal blanking period of the effective video period, noise of a fixed pattern is generated in that portion. Therefore, the generation timing of the electronic shutter pulse is determined by each horizontal blanking period and vertical blanking period. Limited to

The conventional electronic iris control circuit 8
Is formed by a level determination circuit 12A and a shutter pulse generation circuit 13 as shown in FIG. 3, and the iris signal of the voltage Vi that changes in reverse to the photographing light amount of the processing circuit 6 is compared with the lower limit side of the appropriate light amount range of the determination circuit 12A. The non-inverting input terminal (+) of the comparator 14 and the inverting input terminal (-) of the comparator 15 on the upper limit side are supplied in parallel.

Further, voltage dividing resistors R1, R2, R3 for setting a lower limit value and an upper limit value reference voltage of an appropriate light amount range are provided in series between the positive DC power supply terminal + B and the ground.
The lower-limit reference signal of the voltage V _r1 at the connection point between _R1 and R2 is the comparator 1
4 of the inverting input terminal (-) is supplied to the upper limit reference signal voltage V _r2 at the connection point of the resistors R2, R3 is supplied to the non-inverting input terminal (+) of the comparator 15. Note that the difference ΔV between the voltages V _r1 and V _r2 corresponds to the appropriate light amount range.

When the shutter speed is too fast and the photographing light amount becomes smaller than the appropriate light amount range, and the photographed image is blackened, Vi> V _r1 (> V _r2 ). Is "1", the shutter speed is too slow, the photographing light amount becomes larger than the appropriate light amount range, and when the light amount becomes saturated and the image becomes white, ( _Vr1 >) _Vr2 > Vi, the comparator 15
Is an output signal for judging that the speed is too low. When the shutter speed is appropriate and the photographing light amount is within the appropriate light amount range, _Vr1 ≧ Vi ≧ _Vr2 .
15 output signals are both "0".

Further, the shutter pulse generating circuit 13 to which the output signals of the comparators 14 and 15 are supplied comprises, for example, an up / down counter for determining a shutter speed and a down counter for generating an electronic shutter pulse.

The up / down counter uses the vertical blanking pulse of the timing pulse generating circuit 9 as a clock pulse, and the comparators 14, 1 every time this pulse is supplied.
The output signal of "1" of 5 is taken in as an up / down counting signal, and the output binary data is increased or decreased by 1 to determine the shutter speed. Note that the binary data is set to data of the initially set specified speed by, for example, resetting at the start of photographing.

The shutter speed is variably adjusted in units of one horizontal scanning period for each field so that the photographing light amount is brought into an appropriate light amount range by changing the increase / decrease of the binary data based on the photographing light amount of the immediately preceding field.

Further, the binary data of the up / down counter is supplied to the down counter, and this counter takes in the binary data using the vertical blanking pulse of the timing pulse generating circuit 9 as a preset pulse.

After the capture, the down counter uses the horizontal blanking pulse of the timing pulse generation circuit 9 as a clock pulse, and outputs one pulse of the electronic shutter pulse during the horizontal blanking period in which the number of binary data in each field is continuous. It supplies to CCD1 via 10.

[0021]

In the case of the above-mentioned conventional video camera, the iris control performs a hunting operation especially on the high-speed shutter side because the appropriate light amount range of the level determination circuit 12A is fixed by the voltage dividing resistors R1 to R3. Easily become unstable. That is, one step (1
The signal accumulation time T of the CCD 1 discretely changes in units of one horizontal scanning period (= 63.5 μsec) as shown in the equation (1) due to the variation of (stage).

[0022]

T = (63.5 × 10 ⁻⁶ ) × N + α [sec]

Note that N is a natural number indicating a shutter step, and α is a constant indicating a signal extraction position. In the case of the NTSC system, N <525/2, 0 ≦ α ≦ 63.5 × 10 ^−6.
become. Therefore, on the high-speed shutter side where N is close to 0,
The change rate of the signal accumulation time T per one step of the shutter speed, that is, the change rate of the photographing light amount is extremely larger than that of the low-speed shutter side, and in extreme cases, the photographing light amount is doubled by one step change of the shutter speed. Or halve.

When the photographing light quantity changes more than the appropriate light quantity range by changing the shutter speed by one step, the correction of the shutter speed to the high speed side and the correction of the shutter speed to the low speed side are alternately repeated for each field, and the iris is changed. A hunting operation of the control occurs.

In view of the above, conventionally, the hunting operation is prevented by setting the appropriate light amount range considerably wide. In this case, on the low-speed shutter side, blackening is caused due to unnecessary enlargement of the appropriate light amount range. Both an image and an image that has become too bright and have been overshadowed by white are allowed, and there is a problem in that the variation in brightness is increased and the image quality of the captured image is reduced. SUMMARY OF THE INVENTION It is an object of the present invention to prevent hunting operation of iris control without deteriorating image quality.

[0026]

In order to achieve the above object, in a video camera according to the present invention, a shutter is provided so that an appropriate light amount range for judging a shift in shutter speed is wider on a high speed side than on a low speed side. An appropriate range correcting means that varies according to the speed is provided.

[0027]

In the case of the video camera of the present invention configured as described above, the appropriate light amount range changes according to the shutter speed.
On the high shutter speed side, the appropriate light amount range is widened to prevent hunting operation of iris control, and on the low shutter speed side, the appropriate light amount range is not unnecessarily widened, and the brightness of the captured image is constant and its variation is Is prevented.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment will be described with reference to FIG. In FIG. 1, the same reference numerals as those in FIG. 3 denote the same or corresponding elements, and the points different from the configuration in FIG.
This is point b. a. A point that a level determination circuit 12B is provided instead of the level determination circuit 12A of FIG. b. The high-speed shutter identification signal Sc is issued from the shutter pulse generation circuit 13 to the level determination circuit 12B.

The judging circuit 12B is constructed by providing an appropriate range correcting means formed by a series circuit of the normally closed switch 16 and the correcting resistor R4 in parallel with the voltage dividing resistor R2. Also,
The high-speed shutter identification signal Sc is digitally compared, for example, between the binary data of the up / down counter of the generating circuit 13 and the preset high-speed shutter reference data, and is formed only at the time of the high-speed shutter when the binary data becomes equal to or more than the reference data. Release 16.

During the low-speed shutter, the switch 16 is closed and the voltage dividing resistor R2 and the correction resistor R4 are connected in parallel. Therefore, compared to the high-speed shutter in which the switch 16 is opened, the voltage V of the lower-limit reference signal is lower. _{As r1 decreases,} the voltage _Vr2 of the upper limit reference signal increases, and the difference Δ corresponding to the appropriate light amount range is obtained.
V decreases. Therefore, the appropriate light amount range is variably corrected in two stages according to the shutter speed so that the range is wider on the high-speed shutter side than on the low-speed shutter side.

Therefore, even if the difference .DELTA.V on the high-speed shutter side determined by the voltage dividing resistors R1 to R3 is increased so as not to cause a hunting operation and the appropriate light amount range is widened, the difference .DELTA.V on the low-speed shutter side becomes small. The appropriate light amount range is not unnecessarily widened, an image that is almost blackened or an image that is almost white is not allowed, and the brightness of the photographed image is constant and its variation is prevented.

In the above-described embodiment, the voltages V _r1 and V _r2 of both reference signals are varied by using the switch 16 and the correction resistor R4. _r1 and _Vr2 may be varied.

In the above embodiment, the appropriate light amount range is switched in two stages according to the shutter speed. For example, a plurality of series circuits corresponding to a series circuit of the switch 16 and the correction resistor R4 are connected in parallel to the voltage dividing resistor R2. In addition to the connection, the switches of each series circuit are sequentially or selectively opened according to the shutter speed, and the appropriate light amount range is switched in multiple stages according to the shutter speed. It is also possible to make the iris control smoother in these cases.

In addition to the case where the iris control is performed by the variable speed electronic shutter function of the VOFD type interline CCD type in which unnecessary charges are swept onto the CCD substrate in the same manner as the vertical VOFD in the horizontal blanking period as in the above embodiment, Of course, the present invention can be applied to a case where iris control is performed by various variable speed electronic shutter functions such as a pseudo frame interline CCD type variable speed electronic shutter function. The configuration of the shutter pulse generation circuit 13 and the like is not limited to the embodiment.

[0035]

Since the present invention is configured as described above, the following effects can be obtained. Since the appropriate light amount range for judging a shift in the shutter speed by the appropriate range correction means is changed in accordance with the shutter speed so as to be wider on the higher shutter speed side than on the lower shutter speed side, the variation of the shooting light amount on the low speed side is prevented. As a result, the hunting operation of the iris control on the high-speed side can be prevented, and the photographing performance can be significantly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of a video camera of the present invention.

FIG. 2 is a block diagram of a photographing circuit unit of a video camera equipped with a variable speed electronic shutter function.

FIG. 3 is a block diagram of a main part of a conventional example.

[Explanation of symbols]

 1 CCD 8 electronic iris control circuit 12B level judgment circuit 13 shutter pulse generation circuit

Claims (1)

(57) [Claims] 1. A variable speed electronic shutter function for variably adjusting a signal accumulation time of a solid-state image sensor, and comparing an iris signal based on a photographed image signal of the solid-state image sensor with upper and lower limits of an appropriate light amount range. To determine the shift of the shutter speed between the high-speed side and the low-speed side, and variably adjust the signal accumulation time by pulling the photographing light amount into the appropriate light amount range by changing the step speed of the shutter speed based on the result of the judgment. A video camera that performs iris control according to (1), further comprising an appropriate range correction unit that varies according to a shutter speed such that the appropriate light amount range is wider on a higher speed side than on a lower speed side.