JPH054851B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a data output circuit in a semiconductor integrated circuit, and particularly to a data output circuit such as a memory integrated circuit that requires high-speed data access. Regarding.

(Prior Art) When outputting data from a semiconductor integrated circuit such as a memory integrated circuit, it is necessary to charge and discharge the output load at high speed. However, as charging and discharging speed increases, disturbances in the power supply voltage V _DD and ground potential V _SS within the integrated circuit, that is, output noise, are more likely to occur, and this output noise often causes malfunction of semiconductor integrated circuits. . The disturbance in the voltage that occurs as the output load is charged and discharged is due to the temporal increment of the charging and discharging current.
Most of it is occupied by the product L·dI/dt of dI/dt and the inductance L parasitic on the charging/discharging current path.

FIG. 4 shows a conventional data output circuit provided in a memory integrated circuit or the like. 40 is an integrated circuit section, T1 is a data output terminal, T2 is a power supply voltage (V _DD ) terminal, and T3 is a ground potential (V _SS ).
terminals, 41 is an output transistor for outputting "1" level data, 42 is an output transistor for outputting "0" level data, 43 is a parasitic resistance of internal power supply wiring, 44 is a parasitic resistance of internal ground wiring, 45 is a terminal In the output buffer circuit, 46 is an inverter for output control. On the other hand, outside the integrated circuit, 47 is a DC power supply for supplying power voltage, 48 is a DC power supply stabilizing capacitor, 49 is an output load capacitor, 50 to 52 and 5
3 to 55 are the parasitic resistance and parasitic inductance of the external wiring, respectively.

In the above circuit, when outputting "0" data, the output d of the output buffer circuit 45 becomes a low level, the output (output transistor drive signal) N of the inverter 46 becomes a high level, and the data output terminal T1 and the ground terminal T3 are connected to each other. The output transistor 42 inserted between the two terminals becomes conductive, the load capacitor 49 is discharged, and the potential of the data output terminal T1 decreases. Each signal waveform in this series of operations is shown by a solid line in FIG. 5a. A large discharge current flows through the output transistor 42 due to the discharge of the load capacitor 49.
Id occurs, and the parasitic resistances 44, 51, 52 and parasitic inductances 54, 55 present in this current path cause an overshoot in the voltage of the ground terminal T3, which causes the voltage at the power supply terminal T3 to flow through the semiconductor substrate. Overshoot also occurs in the voltage of T2. The voltage waveforms at each of these terminals are shown in Figure 5b.
It is shown with a solid line inside.

Such overshoot becomes noticeable when a "0" level is simultaneously output to each output terminal in a memory integrated circuit having multiple data output terminals and corresponding multiple data output circuits. There is a high possibility that internal circuits such as input buffers may malfunction.

In the data output circuit described above, one "0" level output transistor is required for each data output terminal.
Only one is provided. Therefore, in order to reduce the occurrence of the above-mentioned overshoot, it is normal to reduce the channel width of the output transistor 42 or slow down the rising speed of the drive signal N in order to suppress the drive capability of the output transistor 42. It is. When the channel width of the output transistor is reduced as described above, the overshoot occurring at the ground terminal T3 and the ground terminal T2 can be reduced as shown by the dotted line in FIG. 5b. However, the data output at this time becomes slow as shown by the dotted line in FIG. 5a, and the high speed performance of the memory integrated circuit is greatly compromised.

On the other hand, in order to reduce the occurrence of overshoot as described above, the output transistor for "0" data output is divided into multiple (here, two) 42 ₁ and 42 ₂ as shown in FIG. and form
It is known to add a delay circuit 61 to drive the divided transistors 42 ₁ and 42 ₂ separately so that their conduction start times are different. In this case, the channel widths W(42 ₁ ) and W(42) ₂ of the divided transistors 42 ₁ and 42 ₂ are set to satisfy the specifications of the current output size and speed of the data output circuit. , W(42 ₁ )=W(42 ₂ )
It is.

In the data output circuit shown in Figure 6 above, “0”
When outputting data, the output d of the output buffer circuit 45 falls to a low level, and the inverter 46
The output N becomes high level, one transistor 42 ₁ becomes conductive, and the load capacitor (not shown) starts discharging. Subsequently, after a predetermined time delay, the delay circuit 61
The output N' rises to a high level, and the other transistor 42 ₂ becomes conductive. As a result, the load capacitance is discharged through the two transistors 42 ₁ and 42 ₂ . Each signal waveform in this series of operations is shown in Figure 7a, and potential fluctuations at the power supply terminal T2 and ground terminal T3 are shown in Figure 7b.
It is indicated by a solid line inside. In this case, as shown by the dotted line in FIG. 7b, one of the transistors 4
Since the fluctuation caused by the discharge current flowing through the transistor 2 ₁ is partially offset by the fluctuation caused by the discharge current flowing through the other transistor 42 ₂ , the output noise during data output is reduced over time. is canceled out and becomes smaller. Further, the data output circuit shown in FIG. 6 has a faster data output time than the case where the driving ability of the output transistor is suppressed as described above as a countermeasure against overshoot in the data output circuit shown in FIG. 4.

However, the data output circuit shown in FIG. 6 cannot cancel the initial noise that occurs when the output transistor first starts conducting, so the output noise cannot be suppressed sufficiently, and the delay circuit 61 causes a problem in that the data output time is reliably delayed by the signal delay time that delays the conduction time.

(Problems to be Solved by the Invention) As described above, the present invention is capable of sufficiently suppressing disturbances in the power supply potential and ground potential even by dividing the output transistor into a plurality of parts and shifting the conduction start time. This was done to solve the problem that the data output time is sacrificed when the power supply potential and ground potential cannot be output. The purpose is to provide a data output circuit without

[Structure of the invention]

(Means for Solving the Problems) The data output circuit of the present invention has a single conductivity type circuit in which one end of the current path is connected to the power supply wiring, the other end is connected to the data output terminal, and the gate is connected to the input terminal. 1
a second switch means of a conductivity type opposite to that of the first switch means, in which one end of the current path is connected to the ground wiring, the other end is connected to the data output terminal, and the gate is connected to the input terminal; , is provided. At least one of the first switch means and the second switch means is connected to at least two first and second switch means connected in parallel between the data output terminal and the power supply wiring or the ground wiring and having different channel widths. It consists of transistors. moreover,
Among these transistors, the gate of the transistor with a small channel width is connected to the input terminal via the first gate circuit, and the gate of the transistor with a large channel width is connected to the input terminal without substantially changing the signal level transition time. The second gate circuit is characterized in that it is connected to the input terminal via a second gate circuit whose output is delayed from the output of the first gate circuit.

(Function) When outputting data, at least two first and second
Since the times at which the transistors start conducting are dispersed, the output noise generated each time the transistor starts conducting is dispersed. In this case, the transistor that first becomes conductive has a small channel width and a low driving capability, so the amount of output noise generated when it starts to conduct is small. Therefore, disturbances in the power supply potential and ground potential are sufficiently suppressed, and occurrence of malfunctions in the internal circuits of the integrated circuit is sufficiently suppressed. In addition, transistors that start conduction slowly have a large channel width, so
It is possible to improve the driving ability during data output, and it is possible to speed up the data output time. Furthermore, input signals whose signal level transition times do not substantially change are supplied to the gates of the first and second transistors, so even if the conduction start times of the first and second transistors are dispersed, , the response speed from input to output does not deteriorate.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a data output circuit in a semiconductor integrated circuit, for example, a memory integrated circuit.
is a power supply terminal, 1 is a power supply wiring, 2 is a parasitic resistance of the power supply wiring, T3 is a ground terminal, 3 is a ground wiring, 4 is a parasitic resistance of the ground wiring, and T1 is a data output terminal. 5 is P channel MOS for “1” level output
It is a transistor, and is connected between the power supply wiring 1 and the data output terminal T1. 6 ₁ and 6 ₂ are divided N-channel MOS transistors for outputting "0" data whose respective drains and sources are connected in parallel between the data output terminal T1 and the ground wiring 3. Here, in the N-channel output transistors 6 ₁ and 6 ₂ , the channel width W(6 ₁ ) of one transistor 6 ₁ is set smaller than the channel width W(6 ₂ ) of the other transistor 6 ₂ . There is. The gate of the N-channel output transistor ₆₁ having the smaller channel width and the gate of the P-channel output transistor 5 are commonly connected, and the output N of the output control inverter 7 is applied to this gate. It will be done.
The output d of the output buffer circuit 8 is applied as an input to the inverter 7. The output d of the output buffer circuit 8 is input to a signal delay circuit 9, and the output N' of the signal delay circuit 9 is applied to the gate of the output transistor ₆₂ of the N channel having the larger channel width. The signal delay circuit 9 delays the input signal for a predetermined time and outputs the inverted signal, and a well-known CR time constant circuit or gate circuit using signal delay can be used as the delay means.

Next, the operation of the above data output circuit is shown in FIG.
This will be explained with reference to b. When outputting "0" data, the output signal d of the output buffer circuit 8 falls to a low level, and the output signal N of the inverter 7 rises to a high level. As a result, the P-channel transistor 5 becomes non-conductive, and the N-channel transistor ₆₁ , which has a smaller channel width, becomes conductive.
_The output load capacitance (not shown, data output terminal T1
(load capacitor connected to) starts discharging. Subsequently, after the delay time of the signal delay circuit 9, the output signal is
Due to N', the N channel transistor ₆₂ having the larger channel width also becomes conductive. This “0”
FIG. 2a shows the signal waveforms of various parts when data is output, and FIG. 2b shows the fluctuations in the potential of the ground terminal T3 and the potential of the power supply terminal T2.

On the other hand, when outputting "1" data, the output signal d of the output buffer circuit 8 rises to a high level, and the output signal N of the inverter 7 falls to a low level. As a result, P channel transistor 5
is conductive, the N-channel transistor 6 ₁ is rendered non-conductive, and charging of the output load capacitance begins via the P-channel transistor 5 which is rendered conductive. The signal delay circuit 9 is a circuit in which a delay occurs when the output buffer turns on, but output signals N and N' operate simultaneously when the output buffer changes from the on state to the off state. This prevents the N-channel transistors 6 ₁ and 6 ₂ from being turned on at the same time, and no DC through current is generated.

According to the data output circuit of the above embodiment, “0”
The data output transistor is divided into two, each having a different channel width, and the transistor with the smaller channel width is controlled to start conducting earlier than the other transistor when outputting "0" data. As a result, the disturbance of the ground potential due to the discharge current at the start of each conduction is reduced to the second
In addition to being canceled out as shown by the dotted line in Figure b, since the transistor drive current at the time of initial conduction is small, the output noise at that time is also reduced.
In addition, since the drive current of the transistor whose conduction start time is late is large, the data output operation becomes faster by that _amount , and as shown in _FIG . The data output time is shorter than that of the output circuit, and a data output speed equivalent to that of the data output circuit shown in FIG. 4 can be obtained.

In the above embodiment, the transistor for outputting "0" data is divided into two, but even if it is divided into three or more, at least one is controlled to start conducting earlier than the remaining transistors.
By setting the channel width of the transistor with the earliest conduction start time to be smaller than the channel widths of the remaining transistors, the same effects as in the above embodiment can be obtained.

In addition, in the above embodiment, the transistor for outputting "0" data is divided into multiple parts, but conversely, the transistor for outputting "1" data is divided into multiple parts.
The P-channel transistor for data output is divided into a plurality of transistors, at least one of which is controlled to start conducting earlier than the rest, and the channel width of the transistor with the fastest starting time of conducting is set to the channel width of the remaining transistors. By setting it smaller than the channel width, it becomes possible to reduce the undershoot of the power supply potential when outputting "1" data and to speed up the data output time.

Furthermore, the above-mentioned division of the transistor for outputting "0" data and division of the transistor for outputting "1" data may be used together, and as an example, the data output circuit when each is divided into two is It is shown in Figure 3. Here, 5 ₁ and 5 ₂ are divided P-channel transistors,
The output terminal of the output control inverter 7 is connected to the gate of the transistor 5 ₁ having a small channel width W(5 ₁ ), and the output terminal of the output buffer circuit 8 and the transistor 5 1 having a large channel width W(5 ₂ ) are connected. A signal delay circuit 10 is connected between the gate of No. 2 and the gate of No. ₂ . The other parts are the same as in FIG. 1 and are given the same reference numerals as in FIG. 1. Note that the signal delay circuit 10 has the same configuration as the signal delay circuit 9, and a single signal delay circuit may be used for both functions.

According to the data output circuit shown in FIG. 3 above, “0”
It is possible to reduce the overshoot of the ground potential during data output and the undershoot of the power supply potential when outputting "1" data, and also to speed up the data output time.

〔Effect of the invention〕

As described above, according to the data output circuit of the present invention, it is possible to sufficiently suppress disturbances in the power supply potential and ground potential during data output without impairing the high speed data output time of the semiconductor integrated circuit. It is especially suitable for use in memory integrated circuits that require high-speed data access.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the data output circuit of the present invention, and FIGS. 2a and 2b are signal waveform diagrams showing the "0" data output operation of the circuit in FIG. 1 and accompanying power fluctuations. FIG. 3 is a circuit diagram showing another embodiment of the present invention, FIGS. 4 and 6 are circuit diagrams showing conventional data output circuits, and FIGS. 5 a and b.
7a and 7b correspond to "0" of the data output circuit of FIG. 4 and the data output circuit of FIG. 6, respectively.
FIG. 3 is a signal waveform diagram showing a data output operation and accompanying power supply fluctuations. 1...Power wiring, 3...Grounding wiring, 5, 5 ₁ , 5 ₂ ...
P channel transistor, 6, _{6 1} , 6 ₂ ... N channel transistor, 7 ... Inverter, 8 ... Output buffer circuit, 9, 10 ... Signal delay circuit, T1 ... Data output terminal, T2 ... Power supply terminal, T3 ... Ground terminal.

Claims (1)

[Scope of Claims] 1. A first switch means of one conductivity type having one end of the current path connected to the power supply wiring, the other end connected to the data output terminal, and the gate connected to the input terminal; and one end of the current path. is connected to a ground wiring, the other end is connected to the data output terminal, and the gate is connected to the input terminal, and the second switch means is of a conductivity type opposite to that of the first switch means, At least one of the first switch means and the second switch means connects at least two first switches having different channel widths connected in parallel between the data output terminal and the power supply wiring or the ground wiring; The gate of the transistor with the smaller channel width is connected to the input terminal via the first gate circuit, and the gate of the transistor with the larger channel width is connected to the gate of the transistor with the smaller channel width. A data output circuit, characterized in that the data output circuit is connected to the input terminal via a second gate circuit that delays the output from the output of the first gate circuit without substantially changing the output.