JPH03171813A - Output circuit - Google Patents

Abstract

PURPOSE:To suppress the level of the output current of each FET in the initial stage of turning-on by connecting a first inverter, whose rise speed is slow, to the gate of a N n-channel FET and connecting a second converter, whose fall speed is low, to the gate of a P-channel FET. CONSTITUTION:A first inverter 14 whose rise speed is low is connected to the gate of an N-channel FET 8, and a second inverter 18 whose fall speed is low is connected to the gate of a P-channel FET 9. Consequently, though inputs of first and second inverters 14 and 18 are simultaneously changed, FETs 8 and 9 are in the turning-on state together in the initial stage of turning-on and charging to them is delayed because the output of one inverter is first changed and the output of the other is next changed, and the current flowing to FETs 8 and 9 in the initial stage of turning-on is reduced. Thus, the level of the output current at the time of turning-on is suppressed even at the time of speeding up the response speed to prevent the malfunction of the other circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an output circuit that is used in an integrated circuit or the like having a large number of output buses and is constituted by FETs (field effect transistors).

"Prior Art" Figure 5 shows an LSI (Large Scale Integrated Circuit) that has a large number of output buses, such as the address bus and data path of a CPU (Central Processing Unit), or the data path of a memory.
1 is a block diagram showing an example of the configuration of a conventional output circuit used for the like, and in this figure, l is a manual terminal to which data D is input, 2 is an enable signal input terminal to which an enable signal E is input, and 3 is a An inverter that inverts the enable signal E; 4 is a NAND gate in which the enable signal E is input to the first input terminal, and data D is input to the second input terminal; 5 is the output of the inverter 3 input to the first input terminal; , data D. to the second human power terminal. is Noah Gate, which is operated by humans.

Further, 6 is an inverter that inverts the output of the NAND gate 4, 7 is an inverter that inverts the output of the NOR gate 5, 8 is an N-channel MOS structure FET, 9 is a P-channel MOS structure CDFET, and 10 is a data page. is the output terminal where is output.

In such a configuration, when an enable signal E of level "I4" is input to the enable signal input terminal 2 and data D1 is input to the data input terminal I, inverted data b is output to the output terminal 10. is output, the enable signal E of "L" level is manually input to the enable signal terminal 1, and the data D1 is input manually to the data input terminal 2, and the output terminal 1 is input manually.
0 is high impedance.

"Problems to be Solved by the Invention" By the way, in the conventional output circuit described above, in order to increase the response speed, it is necessary to increase the size of the FETs 8 and 9.

However, if FETs 8 and 9 are made larger, when FET 8 or 9 is turned on, a large current flows through F'ET 8 or 9, as shown in FIG.

This current causes a potential difference due to wiring resistance between the output terminal and the power supply terminal or the ground terminal. This potential difference has the disadvantage of becoming a noise source and causing other circuits to malfunction.

In particular, in devices such as memories that have highly sensitive sense amplifiers, there is a high possibility that noise or malfunctions will occur.

The present invention has been made in view of the above-mentioned circumstances, and provides an output circuit that can suppress the level of output current when turned on even when the response speed is increased, and does not cause malfunction of other circuits. The purpose is to

"Means for solving the problem" The first invention consists of an N-channel FET and a P-channel FET.
ET, a first inverter with a slow falling speed is connected to the gate of the N-channel F'ET, and a first inverter with a slow falling speed is connected to the gate of the N-channel F'ET;
The feature is that a second inverter with a slow startup speed is connected to the gate of T.

In addition, the second invention includes a first output section composed of a first N-channel F'ET of small size and a first P-channel FET, and a second N-channel FET of large size. A second output section consisting of a second P-channel FET is connected in parallel, and the first and second output sections are connected in parallel.
The present invention is characterized in that a plurality of inverters are inserted between the gates of the N-channel FETs and between the gates of the first and second P-channel FETs.

"Operation" According to the first invention, even if the human power of the first and second inverters changes simultaneously, the output of one inverter changes first, and then the output of the other inverter changes. At the beginning of time, all FETs are in an off state, and charging to these is delayed, and the current flowing through the three FETs at the beginning of on time is small.

According to the second invention, the first N-channel FET
Since the size of the first P-channel FET is small, a large current does not flow through them initially when turned on.

In addition, since the input signal is delayed for a predetermined period by multiple inverters and then applied to the gates of the second N-channel FET and the second P-channel, the necessary current is secured and a sufficient output level can be obtained. It will be done.

"Embodiment" Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an output circuit according to an embodiment of the first invention. In this diagram, parts corresponding to those in FIG. 5 are given the same reference numerals, and their explanations will be omitted. In FIG. 1, in place of the inverter 6 in FIG. 5, an N-channel MOS structure FET II whose source is grounded, whose gate is connected to the output terminal of the NAND gate 4, and whose drain is connected to the gate of the FET 8; The source is connected to the gate of FET8, and the gate is connected to the power supply voltage V'
FETI of N-channel MOS structure with DD applied
2, the source is connected to the drain of FET I 2,
An inverter 14 is newly provided, which is composed of a P channel MOS structure FETI3 whose gate is connected to the output end of the NAND gate 4 and whose drain is applied with the power supply voltage VDD.

In addition, in place of the inverter 7, an N-channel MOS structure FET I5 whose source is grounded and whose gate is connected to the output terminal of the NOR gate 5, and a FET I5 whose source is connected to the drain of the FET I5 and whose gate is grounded are connected to the train. is F
P channel MO connected to the gate of E T 9
From an S-structure FE'l''l6 and a P-channel MOS-structure FETl7 whose source is connected to the drain of FETI6, whose gate is connected to the output terminal of NOR gate 5, and to which a power supply voltage V.0 is applied to the train. A new inverter 18 is provided.

In such a configuration, an enable signal E of "tr" level is inputted to the enable signal input terminal 2, and data D! of the "■1" level is inputted to the data input terminal 1. When done manually,
The outputs of NAND gate 4 and NOR gate 5 both become "L" level at the same time, and are input to inverters 14 and 287, respectively.

Now, the power supply voltage V is applied to the gate of FET I2. Since D is applied, FET l2 is always on. Therefore, compared to the case of only FETs I2 and I3, that is, the case of normal inverter 6,
The rise speed is slow. Note that the falling speed is the same as in the conventional case.

Also, since the gate of FET I6 is grounded,
FET I6 is always on. Therefore, FET
The falling speed of inverter 18 is slower than in the case of only I5 and 17, that is, compared to the case of normal inverter 7. Note that the falling speed is the same as in the conventional case.

As a result, even if the outputs of the NAND gate 4 and the NOR gate 5 become "L" level at the same time, the output of the inverter 18 becomes "H" level first, and then the output of the inverter 14 becomes "H" level.
Since the output of FET becomes "H" level, FET9 turns off first, and then FET8 turns on.
Since the ET 8 is not fully turned on, the current that initially flows when the FET 8 is turned on can be reduced, as shown in FIG. 2, compared to FIG. 6.

Incidentally, since the timing at which the FETs 8 and 9 are turned on and off hardly changes from normal timing, the influence on increasing the response speed is small.

In addition, the operation when the enable signal E at the "H" level is input to the enable signal input terminal 2 and the data D1 at the "L" level is input to the data input terminal I is different from the case described above. Since the operation of step 18 is simply reversed, its explanation will be omitted.

Furthermore, in the above explanation, an example was explained in which an N-channel FET was used for FET I2 and a P-channel FET was used for FETI6, but a P-channel FET was used for FET12, the gate was grounded, and the FET
I 6 to P channel FE Ko9l11+v=u-
L+-ma-Qtr'l:11? One seal hn l
F L 4q can be kept on at all times, or F
A P-channel FET is used for ETl2, and its gate is connected to the output terminal of NAND gate 4, and a P-channel FET is used for FET16.
Even if the gate is connected to the output terminal of the NOR gate 5 using a channel FET, the same effect as described above can be obtained.

Next, an embodiment of the second invention will be described.

FIG. 3 is a block diagram showing the configuration of an output circuit according to an embodiment of the second invention. In this diagram, parts corresponding to those in FIG. 5 are given the same reference numerals, and their explanations will be omitted. In FIG. 3, FETs 8 and 9 in FIG. 5 are replaced with FEs of a small N-channel MOS structure.
T I 9 and P channel MOS structure FET2
0 is newly provided.

In addition, an F of a large N-channel MOS structure whose source is grounded and whose drain is connected to the output terminal IO is also used.
ET21, the source is connected to the output terminal 10, and the power supply voltage VDD is applied to the drain.
Satna? DEL so → + L claw % J8C 臘: A new FET 22 is provided.

Further, the human power end is connected to the output end of the inverter 6, the output end is connected to the gate of FET2+, and the human power end is connected to the output end of the inverter 7, and the inverters 23 to 26 are connected in cascade to each other, and the output Inverters 27 to 30 whose ends are connected to the gate of FET 22 and which are cascade-connected to each other are newly provided.

In such a configuration, the enable signal E of the "I-1" level is input to the enable signal terminal 2, and the data D. of the "II" level is input to the data terminal 1. When inputted manually, the outputs of inverters 6 and 7 both become the "I1° level" and are applied to the gates of FETIs 9 and 20, respectively.

Now, FETs 9 and 20 are smaller in size than conventional FETs 8 and 9, so initially when turned on, the fourth
As shown in the figure, no large current flows.

Furthermore, the outputs of inverters 6 and 7 are both delayed for a predetermined period by cascade-connected inverters 23 to 26 and 27 to 30, and then applied to the gates of FETs 21 and 22, ensuring the necessary current and sufficient Output level V. t. , Voo are obtained, and the effect on increasing the response speed is small.

As explained above, the large current that causes noise flows only during the initial turn-on period, so by suppressing the current during this period as described above, noise can be suppressed without sacrificing faster response speed. can be reduced.

This can prevent other circuits from malfunctioning.

"Effects of the Invention" As explained above, according to the present invention, even if the response speed is increased, the level of the output current of each FET at the initial stage of ON can be suppressed.

This has the effect of suppressing the generation of noise.

Therefore, there is an effect that malfunctions of other circuits are not caused.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an output circuit according to an embodiment of the first invention, FIG. 2 is a diagram showing an example of the output current characteristics of the circuit of FIG. 1, and FIG. 3 is an embodiment of the second invention. 4 is a diagram showing an example of the output current characteristics of the circuit in FIG. 3, FIG. 5 is a circuit diagram showing an example of the configuration of a conventional output circuit, and FIG. 6 is a diagram showing an example of the output current characteristics of the circuit of FIG. 5. FIG. 1 1 to 13. 15-17, 19. 20
, 21. 22...I"ET, +4, l8, 23-30...Inverter.

Claims (2)

[Claims] (1) In an output circuit composed of an N-channel FET and a P-channel FET, a first inverter with a slow falling speed is connected to the gate of the N-channel FET, and a first inverter with a slow falling speed is connected to the gate of the P-channel FET. An output circuit characterized in that a second inverter having a slow startup speed is connected to the output circuit. (2) A first output section consisting of a small first N-channel FET and a first P-channel FET, and a second large-sized N-channel FET and a second P-channel FET. A second output section consisting of a FET is connected in parallel between the gates of the first and second N-channel FETs and a second output section consisting of a second N-channel FET.
An output circuit characterized in that a plurality of inverters are inserted between the gates of each of the P-channel FETs.