JPH01212023A - Data output circuit - Google Patents

Abstract

PURPOSE:To suppress the disturbance onto a power supply potential and a ground potential at data output without losing high speed for data output time by controlling the circuit so that the conduction of a MOS transistor(TR) with a small channel width is started fastest when plural split MOS TRs are conductive. CONSTITUTION:The conduction start time of plural MOS TRs is dispersed without conducting all of them at the same time in the data output. Thus, output noise caused at each start of conduction of the MOS TRs 61, 62 is dispersed. In this case, the channel width of the MOS TR 61 conducted at first is small and its drive capability is small, then the quantity of produced output noise at the start of conduction is less. Thus, the disturbance on the power supply potential and the ground potential is suppressed sufficiently and the occurrence of malfunction in the internal circuit of the integrated circuit is sufficiently suppressed. Since the channel width of the MOS TR 62 is large, the drive capability at data output is improved and high speed data output time is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Field of Industrial Application) The present invention relates to data output circuits in semiconductor integrated circuits, and in particular to high-speed two-data access. ! The present invention relates to data output circuits such as memory integrated circuits that are in demand.

(Prior Art) When outputting data from a semiconductor integrated circuit such as a memory integrated circuit, it is necessary to charge and discharge the output load at high speed.

However, the faster the charging and discharging speed is 11L, the faster the speed is 1NrV3.
disturbance of the voltage vDn of the voltage VDn and the voltage of the ground potential VSS,
That is, output noise is likely to occur, and this output noise often causes malfunctions of semiconductor integrated circuits. The disturbance in the 11L pressure that occurs with the charging and discharging of the output load is caused by the difference L-dI/dt between the temporal increment dI/dt of the charging and discharging current and the inductance parasitic on the charging and discharging current path. Most of them are occupied.

FIG. 4 shows a conventional data output circuit that is often provided in memory integrated circuits. 40 is an integrated circuit section, T is a data output terminal, and T2 is 'M[voltage (VDD)]
terminal, T3 is the ground potential (Vsg) terminal, 4 is the output transistor for @1 level data output, 42 is the output transistor for IO'' level data output, 43 is the parasitic resistance of the internal power supply wiring, 44 is the internal ground Parasitic resistance of distribution, 4
5 is an output buffer circuit, and 46 is an output control inverter. - On the other hand, outside the integrated circuit, 47 is a DC power supply for supplying power voltage, 48 is a DC power supply stabilizing circuit, 49 is an output load capacity, and 50 to 52 and 53 to 55 are for parasitic resistance of external wiring, respectively. This is the raw inductance.

In the above circuit, when outputting 10m data, the output d of the output cover circuit 45 is at a low level, the output (output transistor drive signal) of the inverter 46 is at a high level, and the data output terminal TI is at a low level. The output transistor 42 inserted between it and the ground terminal T3 becomes conductive, the load capacitor Ik49 is discharged, and the potential of the data output terminal T1 decreases. Figure 5 (a) shows each signal waveform in this series of operations.
) is indicated by a solid line. Due to the discharge of the load capacitor 49, a large discharge current Id is generated through the multi-output transistor 42, and the parasitic resistance 44.
51.52 and the parasitic inductance 54.55, an overflow and a current occur in the voltage of the ground terminal T3, and an overflow and a current also occur in the voltage of the power supply terminal T2 via the semiconductor substrate. . The voltage waveform of each of these terminals is shown by a solid line in Figure 51).

In a memory integrated circuit having multiple data output terminals and corresponding multiple data output circuits, such an overflow becomes noticeable when an ON level is output to each output terminal at the same time. , there is a high possibility that internal circuits such as the input buffer may malfunction.

In the data output circuit described above, only one '0' level output transistor is provided for each data output terminal.Therefore, in order to reduce the occurrence of overflow and -t as described above, it is necessary to In order to suppress the driving ability of the output transistor 42, it is usual to reduce its channel width or to slow down the rising speed of its drive signal N.When the channel width of the output transistor is reduced as described above, The overflow and -t generated at the ground terminal T3 and the power supply terminal T2 can be reduced as shown by the dotted line in Fig. 5(b).However, the data output at this time is shown by the dotted line in Fig. 5(a). However, if it is slow, the high speed performance of the memory integrated circuit will be significantly sacrificed.

On the other hand, in order to reduce the occurrence of the above-mentioned overflow, as shown in FIG.
Each divided transistor 4 is formed by dividing into 423 parts.
It is known that a delay circuit 61 is added to drive the circuits 21 and 421 separately so that their conduction start times are different. In this case, the divided transistors 421 and 42
．． channels -W(421), W(4,22) are f-
It is set to satisfy the current output size and speed specifications of the output circuit, and w(42t)=W(422)
It is.

When outputting @on data in the data output circuit shown in FIG. Continuity, load capacity (
(not shown) starts discharging. Subsequently, after a predetermined time delay, the output N' of the delay circuit 61 rises to a high level, and the other transistor 42! is conductive. As a result, the load capacitance is discharged through the two transistors 4z1 and 422. Each signal waveform in this series of operations is shown in FIG. In this case, as shown by the dotted line in Figure 7 (bJ),
The fluctuations caused by the discharge current flowing through one transistor 421 are partially offset by the fluctuations caused by the discharge current flowing through the other transistor 42, so the output noise during data output is reduced over time. are canceled out and become smaller. In addition, the data output circuit shown in FIG. 6 above has a faster output time compared to the case where the driving ability of the output transistor is suppressed as described above as a measure to reduce overshoot for the data output circuit shown in FIG. 4. Ru.

However, the data output circuit shown in FIG. 6 cannot cancel the initial noise that occurs when the output transistor first starts conducting, so the output noise cannot be suppressed sufficiently, and the delay circuit There is a problem in that the data output time is reliably delayed by the signal delay time that delays the conduction time due to the 6111C.

(Problems to be Solved by the Invention) As described above, in the present invention, disturbances in the power supply potential and the ground potential cannot be sufficiently suppressed even by dividing the output transistor into a plurality of parts and shifting the conduction start time. ,
This was developed to solve the problem of sacrificing the data output time, and it can sufficiently suppress the disturbances in the power supply potential and ground potential, and it does not impair the high speed of the data output time. The purpose is to provide a data output circuit.

[Structure of the Invention (Means for Solving Problem n)] The data output circuit of the present invention provides various connections between a power supply wiring and a data output terminal in a semiconductor integrated circuit, and between this data output terminal and a ground wiring. A MOS transistor of a first conductivity type for data output and a MOS transistor of a second conductivity type of a conductivity board opposite thereto are connected to the first conductivity type MOS transistor.
Conductivity type MOS transistor and second conductor 1! Type MO
S At least one of the transistors is a plurality of MOS
The MOS transistor is formed by being divided into transistors and connected in parallel, and at least one MOS transistor among the plurality of divided MOS transistors is set to have a smaller channel width than the remaining MOS transistors, The plurality of divided MOS transistors have a small channel width when the transistor is conductive.
It is characterized in that the transistor is controlled so that it starts conducting at the earliest.

(Function) At the time of data output, all of the plurality of MOS transistors are not made conductive at the same time, but the conduction start times are dispersed, so that the output noise generated each time the MOS transistors start conduction is dispersed.

In this case, since the MOS transistor that first becomes conductive has a small channel width and low driving capability, the amount of output noise generated when it starts to conduct is small. Therefore, disturbances in the power supply potential and ground potential are sufficiently suppressed, and occurrence of malfunctions in the internal circuits of the integrated circuit is sufficiently suppressed. Also,
Since the channel width of the MOS transistor whose conduction start time is late is large, it is possible to improve the driving capability at the time of data output9, and it is possible to speed up the data output time.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Diagram K1 shows a data output circuit in a semiconductor integrated circuit, such as a memory integrated circuit, and T2 is a power supply terminal;
is the power supply wiring, 2 is the parasitic resistance of the power supply wiring, TJ is the ground terminal, 3 is the ground wiring, the parasitic resistance of the 4Fi ground wiring, TJ
is a data output terminal. 5 is P for 11n level output
Channel MO8 transistor required, above power supply wiring WAX
and the data output terminal T1 are connected for a distance of Km. 61
and 6° are the data output terminals 1 and 3, which are divided nine N-channel MO8 transistors for data output whose respective drains and sources are connected in parallel between 1 and the ground wire 3. Here, in the N-channel output transistor 1p6M, the channel width W(6t) of one transistor 61 is set smaller than the channel width WC&*) of the other transistor 62. The r-to of the N-channel output transistor 1, which has the smaller channel width, and the dot of the P-channel output transistor 5 are commonly connected, and the r-) is used for output control. The output N of the inverter 2 is given. As the input of this inverter 7, the output d of the 7A circuit 8 is
is given. Also, the output d of this output buffer circuit 8
is input to the signal delay circuit 9, and the output y of the signal delay circuit 9 is applied to the output transistor rotor 2 of the N channel having the larger channel width. The signal delay circuit 9 delays the input signal for a predetermined time and outputs the inverted signal, such as a well-known CR time constant circuit or f-).
A device that utilizes signal delay in a circuit can be used as the delay means.

Next, the operation of the data output circuit is shown in FIG. 2(a).

This will be explained with reference to (b). When outputting data, the output signal d of the output 2277 circuit 8 falls to a low level, and the output signal N of the inverter 7 rises to a high level.As a result, the P-channel transistor 5 becomes non-conductive.
The N-channel transistor 61 with the smaller channel width becomes conductive, and the transistor 62 in this conductive state
The output load capacitor t (load capacitor connected to the data output terminal T, although not shown) starts discharging. Subsequently, after the delay time of the signal delay circuit 9, the output signal V is applied to the N-channel transistor 6!, which has the larger channel width! also becomes conductive. Figure 2 (&) shows the signal waveforms of each part when this 0'' data is output.
1).

On the other hand, when outputting "l" data, the output signal d of the converter circuit 8 rises to a high level, and the inverter 7
The output signal N of falls to a low level. This allows p
The channel transistor 5 becomes conductive and the N-channel transistor 61 becomes non-conductive, and charging of the output load capacitance starts via the P-channel transistor 5 which becomes conductive. The signal delay circuit 9 is a circuit in which a delay occurs when the converter 7a turns on, but output signals N and y operate simultaneously when it changes from the on state to the off state. This prevents the channel transistor and the N-channel transistor '1e6m from being turned on at the same time, so that no DC through current occurs.

According to the data output circuit of the above embodiment, the transistor for outputting "0" data is divided into two parts, each having a different channel width, and the transistor with the smaller channel width is used when outputting the "0" data. The transistor is controlled so that it starts conducting earlier than the other transistor.As a result, the disturbance in the ground potential caused by the discharge current when each transistor starts conducting is canceled out as shown by the dotted line in the 21st page. In addition, since the transistor drive current at the time when conduction starts for the first time is small, the output noise at that time is also small.Furthermore, since the drive current of the transistor whose conduction starts later is large, the data output operation is delayed by that much. As shown in FIG. 6, the data output time is shorter than that of the data output circuit in which the channel widths of the divided transistors 421 and 42 are the same, and the data output circuit is equivalent to the data output circuit shown in FIG. Data output speed is obtained.

In the above embodiment, the transistor for outputting '0' data is divided into two, but even if the transistor is divided into three or more, at least one should be controlled to start conducting earlier than the remaining transistors. By setting the channel width of the transistor whose conduction start time is earliest to be smaller than the channel widths of the remaining transistors, the same effect as in the above embodiment can be obtained.

Furthermore, in the above embodiment, the transistor for outputting "0" data is divided into a plurality of transistors, but conversely, the P-channel transistor for outputting "1" data is divided into a plurality of transistors, and at least one of them is By controlling the transistor to start conducting as quickly as possible, and by setting the channel width of the transistor with the quickest start time to be smaller than the channel widths of the remaining transistors, when outputting "1" data, This makes it possible to reduce the undershoot of the electric potential at , and to speed up the data output time.

Furthermore, division of the transistor for @0'' data output and division of the transistor for '1'' data output as described above may be used together.As an example, the data output circuit when each is divided into two is shown below. It is shown in Figure 3.

Here, 'l and 52 are divided P-channel transistors, transistors 5! and 52 with small channel width W<51). The output terminal of the output control inverter 7 is connected to the output terminal of the output control inverter 7, and a signal is connected between the output terminal of the output circuit 8 and the r-) of the P-channel transistor 52 having a large channel width W<5 m). A delay circuit 10 is connected. The other parts are the same as in Figure 1 (6J),
The same reference numerals as in FIG. 1 are given. Note that the signal delay circuit 10 has the same configuration as the signal delay circuit 9, and these may be combined into one signal delay circuit.

According to the data output circuit shown in FIG.
It is possible to reduce the undershoot of W and the source potential when 1" data is output, and it is also possible to speed up the data output time.

[Effects of the Invention] As described above, according to the data output circuit of the present invention, without sacrificing the high speed of data output of the half-body integrated circuit,
Since disturbances in the power supply potential and ground potential during data output can be sufficiently suppressed, the present invention is particularly suitable for use in memory integrated circuits that require high-speed data access.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an embodiment of the data output circuit of the present invention, and Figures 2 (a) and (b) are '0'' of the circuit in Figure g1.
FIG. 3 is a signal waveform diagram showing data output operation and accompanying power fluctuation; FIG. 3 is a circuit diagram showing another embodiment of the present invention; FIG.
Figures 5 and 6 are circuit diagrams showing conventional data output circuits, Figures 5 (a), (b), and Figure 7 (a), respectively.
, 0)) are signal waveform diagrams showing the 1" data output operation of the data output circuit of FIG. 4 and the data output circuit of FIG. piece, 3... grounding thigh, '*'l
*'! ...P channel transistor,' e 61
e'! ...N-channel transistor, 7...Inverter, 8...Output 2fufufu...Data output terminal, T2...Power supply terminal, T3...
・Ground terminal. Applicant's agent Patent attorney Takehiko Suzue (a) Figure 5 Figure 6

Claims (1)

[Claims] A first conductivity type MOS transistor for data output and a second conductivity type opposite conductivity type MOS transistor are connected between the power supply wiring and the data output terminal in the semiconductor integrated circuit and between the data output terminal and the ground wiring. MOS transistors of a conductivity type are connected, and at least one of the first conductivity type MOS transistor and the second conductivity type MOS transistor is divided into a plurality of MOS transistors and connected in parallel. Multiple M divided
At least one MOS transistor among the OS transistors is set to have a smaller channel width than the remaining MOS transistors, and the plurality of divided M
A data output circuit characterized in that when an OS transistor becomes conductive, the MOS transistor having a small channel width is controlled so as to start conduction earliest.