KR930000959B1 - Data output control circuit - Google Patents

Abstract

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Description

Data output circuit

1 is a circuit diagram showing a data output circuit according to an embodiment of the present invention.

2 (a) and 2 (b) are signal waveform diagrams showing the '0' data output operation of the data output circuit shown in FIG.

3 is a circuit diagram showing a data output circuit according to another embodiment of the present invention.

4 is a circuit diagram showing a conventional data output circuit.

5 (a) and 5 (b) are signal waveform diagrams showing the '0' data output operation of the data output circuit shown in FIG.

6 is a circuit diagram showing a conventional data output circuit.

7 (a) and 7 (b) are signal waveform diagrams showing the '0' data output operation of the data output circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

1: power supply wiring 3: grounding wiring

5, 5 ₁ , 5 ₂ : P-channel transistor 6, 6 ₁ , 6 ₂ : N-channel transistor

7 Inverter 8 Output Buffer Circuit

9, 10: Signal delay circuit T ₁ : Data output terminal

T ₂ : Power Terminal T ₃ : Ground Terminal

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data output circuits in semiconductor integrated circuits, and more particularly, to data output circuits such as memory integrated circuits requiring high speed data access.

[Traditional Technology and Problems]

When outputting data of a semiconductor integrated circuit such as a memory integrated circuit, the output load must be charged and discharged at a high speed. As the charge and discharge speeds up, the voltage of the power supply voltage (V _DD ) and the ground potential (V _SS ) in the integrated circuit is increased. Disturbance, or output noise, is likely to occur, and this output noise often causes malfunction of the semiconductor integrated circuit. The voltage disturbance caused by the charge / discharge of the output load is a product of the temporal increment (dI / dt) of the charge / discharge current and the inductance (L) parasitic in the charge / discharge transfer path (L · dI / dt). Is occupied by most.

4 shows a conventional data output circuit provided in a memory integrated circuit, etc., wherein reference numeral 40 is an integrated circuit portion, T ₁ is a data output terminal, T ₂ is a power supply voltage (V _DD ) terminal, T ₃ is the ground potential (V _SS ) terminal, 41 is the output transistor for ˝1˝ level data output, 42 is the output transistor for ˝0˝ level data output, 43 is the gas resistance of the internal power wiring, 44 is the parasitic resistance of the internal ground wiring 45 is an output buffer circuit, and 46 is an inverter for output control. On the other hand, outside the integrated circuit, reference numeral 47 denotes a DC power supply for power supply voltage, 48 denotes a DC power stabilized capacitance, 49 denotes an output load capacitance, and 50-52 and 53-55 denote parasitic resistance and parasitic inductance of the external wiring, respectively. Indicates.

In the conventional data output circuit as described above, when outputting the " 0 " data, the output N of the inverter 46 drives the output transistor N as the output d of the output buffer circuit 45 goes low. Signal) becomes high level, so that the output transistor 42 inserted between the data output terminal T ₁ and the ground terminal T ₃ conducts, and thus the output load capacitance 49 is discharged. The potential of (T ₁ ) is lowered. Each signal waveform resulting from such a series of operations is shown by the solid line in FIG. Since the large discharge current Id is generated through the output transistor 42 by the discharge of the load capacitance 49, the parasitic resistances 44, 51, 52 and parasitic inductances present in the current path. An overshoot occurs in the voltage of the ground terminal T ₃ by means of 54 and 55, and thus overshoot occurs in the voltage of the power supply terminal T ₂ through the semiconductor substrate. do. The voltage waveforms of these terminals T ₂ and T ₃ are shown by solid lines in FIG. 5 (b).

Such an overshoot is remarkable when a zero level is simultaneously output to each output terminal in a memory integrated circuit having a plurality of data output terminals and a plurality of data output circuits corresponding thereto. There is a high risk of causing a malfunction of an internal circuit such as an input buffer.

In the data output circuit described above, only one transistor for level 0 output is provided for one data output terminal. Therefore, in order to reduce the occurrence of the overshoot as described above, the driving ability of the output transistor 42 must be suppressed. Therefore, it is common to reduce the channel width or slow down the driving signal N. As described above, when the channel width of the output transistor 42 is reduced, the overshoot generated at the ground terminal T ₃ and the power supply terminal T ₂ is indicated by a dotted line in FIG. 5 (b). In this case, the data output is delayed as shown by a dotted line in FIG. 5 (a), so that high speed as a memory integrated circuit is greatly sacrificed.

On the other hand, as described above, in order to reduce the occurrence of overshoot, as shown in FIG. 6, the output transistors for data output are divided into a plurality of output transistors 42 ₁ and 42 _{2 in this case} . In addition, it is known that a delay circuit 61 is added to separately drive so that the conduction start times of the divided output transistors 42 ₁ and 42 ₂ are thus changed. In this case, the channel widths W (42 ₁ ) and W (42 ₂ ) of the divided output transistors 42 ₁ and 42 ₂ are set to satisfy the specification of the magnitude and speed of the current output of the data output circuit. It is W (42 ₁ ) = W (42 ₂ ).

In the data output circuit shown in FIG. 6, when the " 0 " data is outputted, the output d of the output buffer circuit 45 falls to the low level so that the output N of the inverter 46 becomes high. Level, and one of the output transistors 42 ₁ is turned on, so that the load capacity (not shown) starts discharging. Next, since the rise in the output (N ') to the high level of the predetermined is the time delay delay circuit 61 becomes conductive the output transistor (42 ₂₎ on the other side, so that the load capacity of the two output transistors ( 42 ₁ , 42 ₂ ) to discharge. Each signal waveform according to such a series of operations is shown by a solid line in FIG. 7 (a), and the potential variation of the power supply terminal T ₂ and the ground terminal T ₃ is shown by the solid line in FIG. 7 (b). Is shown. In this case, the seventh Fig. (B) As in indicated by the dotted line, the discharge current to the output transistor (42 ₁₎ the output of the variation in the other occurring, as the discharge current flowing through the transistor (42 ₂₎ in one flow Since the noise is partially canceled by the fluctuations that occur, the output noise at the time of data output is canceled in time and becomes small. In addition, the data output circuit shown in FIG. 6 has a longer data output time as a countermeasure for reducing the overshoot of the data output circuit shown in FIG. It becomes faster.

However, the data output circuit shown in FIG. 6 cannot sufficiently suppress the output noise because the first noise generated when the output transistor first starts conduction cannot be sufficiently suppressed, and the delay circuit 61 Has a problem in that the data output time is surely delayed by the delay time of the signal delaying the conduction time.

[Purpose of invention]

Accordingly, the present invention can solve the problem that the disturbance of the power potential and the ground potential cannot be sufficiently suppressed even if the output start time is divided into a plurality of output transistors as described above, but the data output time is sacrificed. It is an object of the present invention to provide a data output circuit capable of sufficiently suppressing the disturbance of the power supply potential and the ground potential, and not reducing the speed of the data output time.

[Configuration of Invention]

In order to achieve the above object, a data output circuit according to an embodiment of the present invention includes a first power supply wiring, a second power supply wiring, a data output terminal, a first connection connected between the first power supply wiring and the data output terminal. A first conductive MOS transistor, a second conductive second MOS transistor connected between the second power supply wiring and the data output terminal, a second conductive third MOS transistor connected in parallel with the second MOS transistor, and the third MOS transistor A data output circuit having a delay circuit for delaying a signal applied to a gate to start conduction of the third MOS transistor after the second MOS transistor starts conduction, wherein the channel width of the second MOS transistor is set to the width of the third MOS transistor. It is characterized by being smaller than the channel width.

In addition, a data output circuit according to another embodiment of the present invention may include a first conductive type first MOS transistor connected between a first power line, a second power line, a data output terminal, the first power line, and the data output terminal. A first conductive second MOS transistor connected in parallel with the first MOS transistor, a second conductive third MOS transistor connected between the second power supply wiring and the data output terminal, and a second connected in parallel with the third MOS transistor A conductive fourth delay transistor, a first delay circuit for delaying a signal applied to a gate of the second MOS transistor to start conduction of the second MOS transistor after the first MOS transistor starts conduction, and a gate of the fourth MOS transistor And a second delay circuit for delaying a signal applied to the third MOS transistor to start conduction of the fourth MOS transistor after the third MOS transistor starts conduction. In the data output circuit, the channel width of the first MOS transistor is smaller than the channel width of the second MOS transistor, and the channel width of the third MOS transistor is smaller than the channel width of the fourth MOS transistor.

[Action]

According to the data output circuit of the present invention configured as described above, since the conduction start time is dispersed without conducting all the plurality of MOS transistors at the same time in the data output, the output noise generated every conduction start of the MOS transistor is distributed. Will be. In this case, the first conducting MOS transistor has a small channel width, which lowers its driving ability, thereby reducing the amount of output insertion at the start of conduction. Therefore, the disturbance of the power supply potential and the ground potential is sufficiently suppressed, and the occurrence of malfunction of the internal circuit to the integrated circuit is sufficiently suppressed. In addition, since the channel width of the MOS transistor with a slow start time is large, the driving capability at the time of data output can be improved, thereby speeding up the data output time.

EXAMPLE

Hereinafter, each embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 shows a data output circuit in a semiconductor integrated circuit, for example, a memory integrated circuit, in which reference numeral T ₂ denotes a power supply terminal, 1 denotes a power supply wiring, 2 denotes a parasitic resistance of the power supply wiring 1, and T; ₃ denotes a ground terminal, 3 denotes a ground wire, 4 denotes a parasitic resistance portion of the ground line 3, and T ₁ denotes a data output terminal. Reference numeral 5 is a P-channel MOS transistor for level 1 output and is connected between the power supply wiring 1 and the data output terminal T ₁ , and 6 ₁ and 6 ₂ are connected to the data output terminal T ₁ . This is a divided N-channel MOS transistor for the '0' data output in which the respective drain and source are connected in parallel between the ground wirings 3. Here, the N chaenneol output transistors _{(61, 62)} is Chan neolpok Chan neolpok [W _(61)] the other output transistor ₍₆₂₎ of one output transistor ₍₆₁₎ [W ₍₆₂₎ Smaller than the channel width, the gate of the N-channel output transistor 6 ₁ having the smaller channel width and the gate of the P-channel output transistor 5 are connected in common, and the gates of these output transistors 5 are the same. Are connected in common, and the output N of the output control inverter 7 is supplied to the gates of these output transistors 6 ₁ and 5. The output d of the output buffer circuit 8 is supplied as an input of the output control inverter 7. The output d of this output buffer circuit 8 is input to the signal delay circuit 9, and the output N 'of this signal delay circuit 9 is the N-channel output transistor of the larger channel width. It is supplied to the gate of (6 ₂ ). The signal delay circuit 9 delays the input signal for a predetermined time and inverts the output signal. The signal delay circuit 9 can use a known CR time correction circuit or a signal delay of the gate circuit as a delay means.

Next, the operation of the data output circuit will be described with reference to FIGS. 2A and 2B.

First, when outputting the " 0 " data, the output signal d of the output buffer circuit 8 falls to the low level, so that the output signal N of the output control inverter 7 rises to the high level. Accordingly, the P-channel output transistor 5 is in a non-conducting state while the N-channel output transistor 6 ₁ with the smaller channel width is in a conducting state, and thus the N-channel output transistor 6 _{1 in} this conducting state. The output load capacity (not shown, but the load capacity connected to the data output terminal T ₁ ) will start discharging via the medium. Subsequently, after the delay time of the signal delay circuit 9, the N channel output transistor 6 ₁ with the larger channel width is brought into a conductive state by the output signal N '. The signal waveforms of the respective portions at the time of output of the " 0 " data are shown in FIG. 2 (a), and the potential variation of the ground terminal T ₃ and the low variation state of the power supply terminal T _{2 are} shown in FIG. b).

On the other hand, in the case of outputting # 1 data, the output signal d of the output buffer circuit 8 rises to a high level, so that the output signal N of the inverter 7 falls to a low level. Accordingly, the P channel output transistor 5 is in a conductive state while the N channel output transistor 6 ₁ is in a non-conducting state, so that the P channel output transistor 5 is in the conductive state to the output load capacity. Charging is initiated. The signal delay circuit 9 performs a delay operation when the output buffer circuit 8 is turned on, but outputs N and N 'simultaneously when the output buffer circuit 8 is turned off. The output transistors 6 ₁ and 6 ₂ are also prevented from being turned on at the same time so that no direct current flow occurs.

According to the data output circuit of the above embodiment, the channel widths of the? 0? Data output are divided into two channels so that the respective channel widths are different, and when the? 0˝ data is output, the output transistor whose channel width is smaller is smaller than that of the other output transistors. It is controlled to start conducting as soon as possible. Accordingly, the disturbance of the ground potential due to the discharge current at the start of each conduction is not only canceled as shown by the dotted line in Fig. 2B, but the output at that time because the output transistor drive current at the start of the conduction is small. Noise also becomes smaller. In addition, since the drive current of the output transistor having a slow conduction start time is large, the data output operation becomes faster by that amount, so that the data output time of the divided output transistors 42 ₁ and 42 ₂ is as shown in FIG. Since it is shorter than this data output circuit, the data output speed equivalent to the data output circuit shown in FIG. 4 can be obtained.

In the above embodiment, the output transistors for data output is divided into two, but even when divided into three or more, at least one output transistor is controlled to start conducting earlier than the remaining output transistors, and this conduction start time is the fastest. By setting the channel width of the output transistors to be smaller than the channel widths of the remaining output transistors, the same effect as in the above embodiment can be obtained.

In the above embodiment, the N channel output transistor for data output is divided into plural, but conversely, the P channel output transistor for data output is divided into plural and at least one of the output transistors conducts faster than the remaining output transistors. The conduction start time is set so that the channel width of the fastest output transistor is smaller than the channel widths of the remaining output transistors, thereby reducing the undershoot of the power potential during data output. In addition, the data output time can be increased.

Further, as described above, the division of the output transistor for data output and the division of the output transistor for data output may be used in combination. As an example, a data output circuit in the case of dividing into two pieces is shown in FIG. I did it. Here, reference numerals 5 ₁ and 5 ₂ in the drawings denote the divided P channel output transistors, and the output of the output control inverter 7 at the gate of the output transistor 5 ₁ having a small channel width W (5 ₁ ) ( N) is connected, and the signal delay circuit 10 is connected between the output terminal d of the output buffer circuit 8 and the gate of the P channel output transistor 5 ₂ having the large channel width W (5 ₂ ). It is. Other configurations are the same as those shown in FIG. 1, and therefore the same reference numerals are attached to FIG. In addition, the signal delay circuit 10 has the same configuration as the signal delay circuit 9, and these signal delay circuits 9 and 10 may be used as one signal delay circuit.

According to the data output circuit shown in FIG. 3, the overshoot of the ground potential at the time of # 0 'data output and the undershoot of the power potential at the time of # 1' data output can be reduced as well as the data output time. Speed can be increased.

On the other hand, reference numerals in the constituent elements of the scope of the claims of the present invention is for facilitating the understanding of the present invention, it is written with the intention to limit the technical scope of the present invention to the embodiments shown in the drawings no.

[Effects of the Invention]

As described above, according to the data output circuit of the present invention, since the disturbance of the electric potential and ground potential during data output can be sufficiently suppressed without degrading the high speed of the data output time of the semiconductor integrated circuit, in particular, high speed data It is suitable for employing a memory integrated circuit or the like requiring access.

Claims (2)

The first conductive type agent connected between the first power wiring 1, the second power wiring 3, the data output terminal T ₁ , and the first power wiring 1 and the data output terminal T ₁ . A 1MOS transistor 5, a second conductive type 2MOS transistor 6 ₁ connected between the second power supply wiring 3 and the data output terminal T ₁ and a second MOS transistor 6 ₁ connected in parallel The second conductive third MOS transistor 6 ₂ and the signal applied to the gate of the third MOS transistor 6 ₂ are delayed, so that the third MOS transistor 6 ₁ starts conduction after the second MOS transistor 6 ₁ starts to conduct. ₍₆₂₎ characterized in that in the data output circuit with a delay circuit 9 to start the conduction of, reducing the Chan neolpok of said 2MOS transistor ₍₆₁₎ than Chan neolpok of said 3MOS transistor ₍₆₂₎ Data output circuit. The first conductive type agent connected between the first power supply wiring 1, the second power supply wiring 3, the data output terminal T ₁ , and the first power supply wiring 1 and the data output terminal T ₁ . Between a ₁ MOS transistor 5 ₁ , a first conductive second MOS transistor 5 ₂ connected in parallel with the _first MOS transistor 5 ₁ , between the second power supply wiring 3 and the data output terminal T ₁ . the gate of the second conductivity type the 3 MOS transistor _(61), wherein the 3MOS transistor ₍₆₁₎ and a second conductivity type first 4MOS transistor _(62), wherein the 2MOS transistor ₍₅₂₎ connected in parallel connection A first delay circuit 10 for starting the conduction of the _second MOS transistor 5 ₂ after the first MOS transistor 5 ₁ starts conduction by delaying a signal applied to the second MOS transistor 5 ₂ and the fourth MOS transistor 6 _2. ) for delaying the signal applied to the gate, the conduction time of starting of the first 4MOS transistor ₍₆₂₎ after said first 3MOS transistor ₍₆₁₎ from the start of the conduction Key is in the second data output circuit with a delay circuit 9, wherein the 1MOS transistor ₍₅₁₎ Chan wherein 3MOS transistor with a box smaller than Chan neolpok of said 2MOS transistor ₍₅₂₎ to neolpok of ( The channel width of 6 ₁ ) is smaller than the channel width of the fourth MOS transistor (6 ₂ ).

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