KR100212159B1 - Output voltage compensated transfer gate - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output voltage compensated transfer gate, in particular a first transistor and a second transistor of the same type and having different transistor sizes are connected in parallel so that the first and second transistors are simultaneously turned on and the second transistor is It is turned off later than the first transistor by a predetermined time.

Therefore, the present invention can minimize the magnitude of the error voltage generated in the output voltage can be effectively used in analog application circuit.

Description

Output Voltage Compensated Transfer Gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type transfer gate, and more particularly, to an output voltage compensation type transfer gate in which an error voltage is minimized to output an output voltage equal to an input voltage.

In general, in a MOS type field effect transistor, electrons are attracted from a source to form a channel by a voltage applied between a gate, which is a metal electrode, and a semiconductor substrate, and electrons of the channel go to a drain. Therefore, since the formation and disappearance of the channel occurs at a high speed, it is mainly used as an amplifier or a switching device.

Fig. 1 is a circuit diagram showing a conventional MOS field effect transistor, which is composed of a capacitor C connected in series between an nMOS transistor 2 and ground.

FIG. 2 is a waveform diagram illustrating FIG. 1, where Φ is a clock signal for driving a gate of an nMOS transistor, Vin is an input voltage, and Vout is an output voltage.

Referring to FIGS. 1 and 2, when the nMOS transistor 2 is turned on in synchronization with the rising edge of the clock signal Φ, a certain amount of charge is present in a channel between the drain and the source. Is the same as

[Equation 1]

은 트랜지스터의 폭,

은 트랜지스터의 길이,

는 단위 면적당 게이트-옥사이드 커패시터,

는 트랜지스터의 게이트와 소오스사이 전압,

는 트랜지스터의 문턱전압을 나타낸다.In Equation 1

The width of the transistor,

The length of the transistor,

Is the gate-oxide capacitor per unit area,

Is the voltage between the gate and source of the transistor,

Represents the threshold voltage of the transistor.

On the other hand, when the nMOS transistor 2 is turned off, the charges in the channel exit to the source and drain of the transistor, and these charges act as an error voltage on the output voltage Vout, which is the voltage charged in the capacitor C. Accordingly, when the clock signal Φ is a falling edge, the output voltage Vout is output by adding an error voltage to the input voltage Vin. This phenomenon is called charge injection, and the nonlinear output voltage generated by such charge injection seriously affects the switching operation of the circuit.

Therefore, a dummy MOS field effect transistor or a complementary MOS field effect transistor as shown in FIGS. 3 and 4 is used to compensate for the charge injection phenomenon generated in the circuit.

3 is a circuit diagram illustrating a conventional dummy MOS field effect transistor, in which a first nMOS transistor 4, a source terminal and a drain terminal are commonly connected, and a second nMOS transistor 4 connected in series with the first nMOS transistor 4. 6) and the second nMOS transistor 6.

4 is a circuit diagram showing a conventional complementary MOS field effect transistor, which is composed of an nMOS transistor 8, a pMOS transistor 10 connected in parallel to the nMOS transistor 8, and a pMOS transistor 10.

)가 발생부위로부터 각 트랜지스터로 오는 동안 경로에 발생하는 지연 현상과 상보형 모스 전계 효과 트랜지스터에서 nMOS와 pMOS 트랜지스터의 트랜지스터 형이 다르므로 입력전압과 출력전압이 동일하지 않을 수 있다.However, the transistors as shown in FIGS. 3 and 4 have opposite clock signals Φ,

The delay between the path and the complementary MOS field effect transistor in the path from the generation site to each transistor, the transistor type of the nMOS and pMOS transistors are different, the input voltage and the output voltage may not be the same.

Therefore, since the charge generated in the channel of the transistor after the transistor is turned off is output as an error voltage in addition to the output voltage, there is a problem that the effect of the charge generated in the transistor cannot be completely eliminated even by the transistor compensating for this.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output voltage compensation type transfer gate which can minimize the influence of charges generated in a channel of a transistor in order to solve the above problems of the prior art.

In order to achieve the above object, the device of the present invention is of the same type and has a first transistor and a second transistor having different transistor sizes connected in parallel so that the first and second transistors are simultaneously turned on and the second transistor is connected to the first transistor. It is characterized in that the predetermined time is turned off later.

1 is a circuit diagram showing a conventional MOS field effect transistor.

FIG. 2 is a waveform diagram for explaining FIG. 1. FIG.

3 is a circuit diagram showing a conventional dummy MOS field effect transistor.

4 is a circuit diagram showing a conventional complementary MOS field effect transistor.

5 is a circuit diagram showing an output voltage compensation type transfer gate according to the present invention;

Figure 6 is a waveform diagram for explaining the operation of the output voltage compensation type transfer gate according to the present invention.

* Explanation of symbols for main parts of the drawings

20: first transistor. 22: second transistor.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

5 is a circuit diagram illustrating an embodiment of an output voltage compensation type transfer gate according to an embodiment of the present invention, in which a first nMOS transistor 20 and a 2 nMOS transistor having a length and a width smaller than the first nMOS transistor 20 are smaller. 22 is connected in parallel with the first nMOS transistor 20.

FIG. 6 is a waveform diagram illustrating FIG. 5, where Φ 1 is a clock signal supplied to the gate of the first nMOS transistor and Φ 2 is a clock signal supplied to the gate of the second nMOS transistor.

5 and 6, the first nMOS transistor 20 and the second nMOS transistor 22 are turned on at rising edges of the Φ 1 and Φ 2 clock signals input to the gate, respectively.

는 상기 트랜지스터(20)의 소오스와 드레인으로 빠져간다. 이때 상기 전하(

)는 접지와 제 1 nMOS 트랜지스터(20)와 제 2 nMOS 트랜지스터(22)가 공통 접속된 노드 사이에 접속된 커패시터(C)에 충전된 전압에 더해져 출력전압(Vout)에 오차전압으로 작용한다.Charge present in the channel of the first nMOS transistor 20 when the first nMOS transistor 20 is turned off in synchronization with the falling edge of the Φ 1 clock signal, that is,

Passes to the source and the drain of the transistor 20. Where the charge (

) Is added to the voltage charged in the capacitor C connected between the ground and the node where the first nMOS transistor 20 and the second nMOS transistor 22 are commonly connected to act as an error voltage on the output voltage Vout.

는 상기 트랜지스터(22)의 소오스와 드레인으로 빠져나간다. 이때 커패시터(C)에 충전된 전압은 상기 제 1 nMOS 트랜지스터(20)에 의한 영향을 받지 않고, 제 2 nMOS 트랜지스터(22)에 의한 전하(

)에 영향을 받는다.After a predetermined time td has elapsed, the second nMOS transistor 22 is turned on in synchronization with the falling edge of the Φ 2 clock signal to exist in the channel of the second nMOS transistor 22.

Exits to the source and drain of the transistor 22. At this time, the voltage charged in the capacitor C is not affected by the first nMOS transistor 20, and the charge of the second nMOS transistor 22

) Is affected.

보다 상기 제 2 nMOS 트랜지스터(22)가 턴오프될 경우 발생되는 전하값

이 휠씬 작기 때문에 출력전압(Vout)에 영향을 미치는 오차전압을 최소한의 크기로 줄인다.Therefore, a charge value generated when the first nMOS transistor 20 is turned off

The charge value generated when the second nMOS transistor 22 is turned off

Because of this small size, the error voltage affecting the output voltage (Vout) is reduced to a minimum size.

Accordingly, the present invention can minimize the size of the error voltage generated in the output voltage by minimizing the size of the second transistor according to the transistor design rule.

According to the present invention, a transistor having the same type and having a minimum transistor size and a transistor having a different size are turned on at the same time, and the transistor having the minimum size is turned off after a predetermined time than other transistors to reduce the magnitude of the error voltage generated in the output voltage. It can be minimized and effectively used in analog application circuits.

Claims (4)

An output of the same type and having a first transistor having a different transistor size and a second transistor connected in parallel so that the first and second transistors are simultaneously turned on and the second transistor is turned off a predetermined time later than the first transistor; Voltage compensated transfer gate. The output voltage compensated transfer gate of claim 1, wherein the first transistor and the second transistor include an n-type MOS field effect transistor. The output voltage compensation transfer gate of claim 1, wherein the first transistor and the second transistor include a p-type MOS field effect transistor. The output voltage compensation transfer gate as set forth in claim 1, wherein any one of the first transistor and the second transistor has a minimum size of a given design rule.

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