JPH0548504B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus control method, and particularly to a bus control method in an information processing device.

[Conventional technology]

Conventionally, this type of bus control system includes a bus system in which a plurality of modules are connected by a bus, and each module communicates via the bus. In such a bus system, as shown in Figure 3, a plurality of modules 1...n are connected to the bus, each module 1...n is assigned an address 1...n, and each module has its own address. The device is configured to perform data transfer by sending out onto the bus the address set for the communication partner and the address set for the other party to communicate with.

For example, when transferring data from module 1 to module 2, module 1 first performs an operation to acquire the right to use the bus. When module 1 acquires the usage right, it becomes the requesting module and sends its own address (hereinafter abbreviated as SA) on the bus.
The address of the party you want to communicate with “1” (hereinafter referred to as DA)
(abbreviated as "2") and the necessary data are sent.
When module 2 recognizes that the destination address DA sent from the requesting module is its own address "2," it becomes the responding module and takes in the sent own address SA, destination address DA, and data, and further performs necessary operations. perform the action,
Data transfer ends.

Next, when data is to be transferred from module 1 to all other modules 2...n, when module 1 acquires usage rights in the same way as above, all modules are transferred onto the bus with their own address SA as "1" and the destination address DA. A predetermined broadcast communication address (hereinafter abbreviated as GA) indicating the destination and necessary data are sent. All other modules use the destination address DA sent by the requesting module.
When it recognizes that GA is the broadcast communication address, it becomes the responding module and sends its own address.
Import SA, other party address DA and data,
Further necessary operations are performed and the data transfer is completed. As described above, in the conventional bus control system, only one-to-one communication between the requesting module and the responding module or communication between the requesting module and all other modules can be performed.

[Problem that the invention seeks to solve]

In the conventional bus control method described above, the requesting module that has acquired the right to use the bus either communicates with a module whose address matches the destination address to be sent, or sends a predetermined broadcast communication address to the destination. By using the address as DA, data is transferred with all modules on the bus other than the requesting module, so the requesting module that has acquired the right to use the bus can communicate with any number of modules at the same time. The drawback was that it was impossible to do so.

[Means for solving problems]

The bus control method of the present invention includes storage means for setting the self-address of the requesting module in each of a plurality of modules, and coincidence detection means for detecting a match between the self-address of the received requesting module and the contents of the storage means. has been established.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the invention. In FIG. 1, this embodiment has a plurality of modules 3, 4, 15.
and are connected to each other via a bus 30. Each module can be a requesting module or a responding module, but in this bus control method, the requesting module communicates by sending its own address as its own address and the responding module's address as the other party's address on the bus 30. Each module (for example, module 4) has a partner address matching circuit 7 that determines whether its own address matches the partner address sent from the requesting module, and a circuit 7 that determines whether the address it owns matches the partner address sent from the requesting module. It includes a partner address register 9 to be set, and a self-address matching circuit 8 to determine whether the value set in the partner address register 9 matches the own address register transmitted from the requesting module.

Furthermore, the module 4 has a data buffer 5 and an address buffer 6 connected to the bus 30.
and own address register 1 that stores the own address.
0 and the outputs of the other address matching circuit 7 and own address matching circuit 8.
, a reception recognition flip-flop 14 connected to this OR circuit 102 and whose output supplies the address buffer 6, and a reception recognition flip-flop bus clock line 21 are ORed, and the output is sent to a data buffer. 5, and a processor 11 that is connected to an internal bus 22 and performs various controls.

The internal bus 22 of each module is connected to a data buffer 5 and an address buffer 6, and further connected to a partner address register 9.

The bus 30 connected to each module has a bus 31 for upper 8 bits and a bus 32 for lower 8 bits, and both buses 31 and 32 are connected to data buffer 5.
The upper 8 bits of the bus 31 are connected to the own address matching circuit 8, and the lower 8 bits of the bus 32 are connected to the other address matching circuit 7.

In this embodiment, when data is transferred from module 3 to module 4, the requesting modules 3 and 4 are assumed to be the responding module 4. The data buffer 5 is a buffer for receiving data, and the address buffer 6 is a buffer for storing the own address SA and the other party's address DA transferred from the requesting module 3. The destination address matching circuit 7 is a matching circuit that determines whether the DA transferred from the requesting module matches the own address of the responding module, and the own address matching circuit 8 judges whether the DA transferred from the requesting module matches the own address SA transferred from the requesting module. This is a matching circuit that determines whether the contents of the partner address register of the responding module match. The destination address register 9 is a register in which the processor 11 sets the address of the destination to which data is to be received, and the own address register 10 is a register that stores the own address of the responding module. The reception recognition flip-flop 14 is a reception recognition flip-flop that is set when it recognizes that the transferred data is addressed to itself. Note that the module 15 is a module having exactly the same configuration as the response module 4.

Next, the operation of this embodiment will be explained. When data is transferred from the requesting module 3 to the responding module 4, first, when the requesting module 3 acquires the right to use the bus, it transfers its own address bus 31.
to the address of the responding module 4 on the bus 32.
Send to. In this case, the data on the bus 31 is the own address SA, and the data on the bus 32 is the other party's address DA. Sent address
DA is input to the other party address matching circuit 7 inside the response module 4, and the response module 4
The value of own address register 10 and the other party's address
When the DA matches, the output of the destination address matching circuit 7 becomes "1", and at the rising edge of the next bus clock, the reception recognition flip-flop 14 is set to "1", and at the same time the own address SA and the destination address are set to "1".
DA is stored in the address buffer 6, and data following the own address SA and the other address DA is stored in the data buffer 5 every bus clock.
In this way, the response module 4 receives the data sent from the request module 3. FIG. 2 shows the above-mentioned contents in the form of a time chart.

Next, the processor 11 sets the own address of the requesting module 3 in the partner address register 9 of the responding module 4. When the requesting module 3 acquires the right to use the bus in the same manner as described above,
Sends own address SA to bus 1 and sends destination address DA to bus 2. In this case, the other party address DA
can be any value.

Own address sent from requesting module 3
The SA is input to the own address matching circuit 8 inside the response module 4, and the response module 4
The value of the other party's address register 9 and the own address SA
If they match, the output of the own address matching circuit 8 becomes "1", and the own address SA and the other party's address DA are stored in the address buffer 6, and the data is stored in the data buffer 5, respectively, in exactly the same procedure as described above. At this time, if the own address of the requesting module 3 is set in the destination address register inside the module 15, the module 15 can also store data at the same time as the responding module 4 using exactly the same procedure as the responding module 4. .

〔Effect of the invention〕

As explained above, the present invention includes, in each module, a partner address matching circuit that determines whether the own address it owns and the partner address sent from the requesting module match, and Set the other party address register,
It has a self-address matching circuit that determines whether the value of the other party's address register matches the own address sent from the requesting module, and responds when one of the two matching circuits' conditions is met. By making it a side module,
This has the advantage that the requesting module can communicate with any number of modules simultaneously.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing a time chart in this embodiment, and Fig. 3 is a diagram showing an embodiment of the present invention.
The figure shows a conventional bus system. 3... Request side module, 4... Response side module, 5... Data buffer, 6... Address buffer, 7... Other address matching circuit, 8... Own address matching circuit, 9... Other address register, 10... Own address register, 11... Processor, 14... Reception recognition flip-flop, 15... Module, 2
1... Bus clock line, 22... Internal bus, 30... Bus, 101, 102... OR circuit.

Claims (1)

[Scope of Claims] 1 A plurality of modules are connected via a bus, and the unique address of the requesting module is taken as its own address, and the unique address of the responding module with which it wants to communicate is taken as the other party's address, and these addresses are used as the above-mentioned address. Bus control in which the requesting module transmits data onto the bus, and the module that detects a match between the received destination address and its own unique address communicates with the requesting module as the responding module. In the method, each module includes a storage means for setting the self-address of the requesting module, and a coincidence detection means for detecting a match between the received self-address of the requesting module and the contents of the storage means. A bus control method, characterized in that a module whose match is detected by the match detecting means also communicates with the requesting module as the responding module.