JPH07109598B2 - Inter-module data transfer device - Google Patents

Description

TECHNICAL FIELD The present invention relates to an information processing device, and more particularly to an inter-module data transfer device for transferring data between a plurality of modules via a bus.

2. Description of the Related Art A technique in which a plurality of modules are connected by a bus and each module communicates via the bus is widely used. An example of such a bus system is shown in FIG. In the figure, multiple modules 1, ..., n
Connected to bus 20 and modules 1, ..., n respectively
Set the address of 1, ..., n correspondingly. Then, each module performs data transfer by sending out the address set for itself and the address set for the other party with whom it is trying to communicate on the bus 20.

For example, consider the case of transferring data from module 1 to module 2. First, the module 1 performs an operation for acquiring the right to use the bus. When module 1 acquires the right to use, it becomes the requesting module, and has 1 of its own address (abbreviated as SA below), 2 of the address of the other party with whom it wants to communicate (abbreviated as DA below), and the necessary data. Is sent. When the module 2 recognizes that the DA sent from the requesting module is 2 of its own address, it becomes the responding module and takes in the SA, DA and data sent, and performs the necessary operations to transfer the data. finish.

The above is the DA sent from the request side (transfer source) module
Is a data transfer operation when the address of the response side (transfer destination) module matches, and this transfer operation is referred to as a first data transfer operation. Next, in the response side (transfer destination) module, the address of the request side (transfer source) module is set in advance in its own address register, and the SA sent by the request side (transfer source) module and the register are set. Consider the second data transfer operation, which is the operation when data is transferred when the received address matches, for example, the case where data is transferred from module 1 to module 2. First, the module 2 sets the address value 1 indicating the module 1 in the partner address register that sets the address of the partner to receive in advance, and sets the partner address match mask circuit that ignores the DA sent from the requesting module. deep. When the module 1 acquires the usage right as described above, it sends out 1 of SA, 2 as DA and necessary data. Module 2 ignores DA but SA
Recognizes that it is the same as the value 1 set in the other party's address register, it becomes the response side module and SA, DA sent
Then, the data is taken in and necessary operations are performed to complete the data transfer. The module 2 rejects the data sent from other than the module 1 because the SA is not 1.

As described above, in the conventional bus control method, it is possible to receive one-to-one communication between the request side module and the response side module or receive only certain specific partner data.

In the conventional bus control method described above, when data communication is performed only with a specific one module, the address of the requesting module is set in advance in a specific register in the responding module so that the address of the requesting module is transmitted. Since it is a method to receive only when the address is the same as the value set in the register, the requesting module becomes the requesting module for the modules other than the responding module during transfer with the responding module. It had the drawback that it could not be transferred.

It is an object of the present invention to provide an inter-module data transfer device that enables a requesting module to become a requesting module for another module while performing data transfer only with a specific module. It is an object.

According to the present invention, a plurality of modules are provided, each module has an address indicating itself, and the data transfer source module uses its own address as the transfer source address SA, An inter-module data transfer device in a bus communication system in which communication between modules is performed via the common bus by transmitting an address as a transfer destination address DA onto the common bus, and the transfer source address of each module An address valid signal transmission bus for transmitting an address valid signal indicating whether SA is valid or invalid is provided to each module, and each of the modules shares the transfer source address SA and the transfer destination address DA with each other before data transfer. The address valid signal is sent to the bus and the valid address of the transfer source address SA is shown. Means for sending to the address valid signal sending bus, register means for presetting the address of the partner module whose own module wants to receive data transfer, and the transfer source address SA received from the common bus
And a second match detecting means for detecting a match between the register address and the set address of the register means, and a second match detecting means for detecting a match between the own address and the transfer destination address DA received from the common bus.
Match detection means, invalidation means for invalidating the detection result of the second match detection means, and the common bus when the second match detection means detects a match during non-invalidation control of the invalidation means. The means for instructing to take in the above data and the address valid signal received from the address valid signal sending bus at the time of invalid control of the invalidating means are valid and the first match detecting means has detected a match. Means for instructing to take in data on the common bus only when, and an inter-module data transfer device are obtained.

EXAMPLES Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. Here, a 2-byte parallel bus will be described as an example.

Reference numerals 1 and 2 represent the upper 8 bits and the lower 8 bits, respectively. The feature of the present invention relates to this bus control system. Modules 3 and 4 are connected to the bus. In this example, data is transferred from the module 3 to the module 4. Therefore, the module 3 is a request side module and the module 4 is a response side module.

5 is a buffer for receiving data, 6 is an address buffer for storing the SA and DA transferred from the requesting module, and 7 is a judgment that the DA transferred from the requesting module and the own address of the responding module match. Counter address matching circuit, 8 is a self address matching circuit that determines that the SA transferred from the requesting module matches the contents of the partner address register of the responding module, and 9 is a partner address that sets the address of the recipient to receive Register, 10
Is an address register of the responding module, 11 is a processor for controlling the inside of the responding module, 14 is a reception recognition flip-flop that is set when recognizing that the transferred data is addressed to itself, 21 is a bus clock line, 22 Is the internal bus of the responding module. Reference numerals 101 and 102 are OR circuits, and 15 and 18 are modules having exactly the same configuration as the response side module 4. 17,103 is an AND circuit,
Especially, 17 acts as a self-address matching mask circuit. 12
Is an address matching mask circuit, set clock
The mask is set by 23.

Consider a case where data is transferred from the requesting module 3 to the responding module 4. First, when the requesting module 3 acquires the right to use the bus, it sends its address to the bus 1 and the address of the responding module 4 to the bus 2. In this case, the data on bus 1 is SA and the data on bus 2 is DA. The sent DA is input to the partner address match circuit 7 inside the response side module 4, and when the value of the own address register 10 of the reply side module 4 matches the DA, the output of the partner address match circuit 7 becomes 1 Become. At this time, if the processor 11 is set so that the output of the partner address coincidence mask circuit 12 becomes 1, the reception recognition flip-flop 14 at the next rise of the bus clock.
Is set to 1, and SA and DA are simultaneously stored in the address buffer 6. Further, the data following SA and DA is stored in the data buffer 5 for each bus clock. In this way, the response side module 4 receives the data sent from the request side module 3. FIG. 2 is a time chart showing the contents described above. The above is the first data transfer operation described in the prior art.

Next, the second data transfer operation described in the prior art will be described. For example, it is assumed that the processor 11 sets an address value indicating the requesting module 3 in the partner address register 9 of the responding module 4 and sets the output of the partner address matching mask circuit 12 to zero. When the requesting module 3 acquires the right to use the bus in the same manner as described above, SA is sent to the bus 1 and DA is sent to the bus 2. At this time, the self address valid signal 16 is set to 1. The SA sent from the request side module 3 is input to the own address match circuit 8 inside the response side module 4, and when the SA matches the value of the partner address register 9 of the response side module 4, the output of the own address match circuit 8 is output. After that, SA and DA are stored in the address buffer 6 and data are stored in the data buffer 5, respectively, in exactly the same procedure as before and after.

Next, when the address value indicating the requesting module 3 is similarly set in the partner address register 9 of the responding module 4 and the output of the partner address matching mask circuit 12 is set to 0, the requesting module 15 It is assumed that data is transferred to the response side module 4 by the conventional method. At this time, as described above, the output of the partner address coincidence circuit 7 is 1
However, since the output of the partner address coincidence mask circuit 12 is 0, the output of the AND circuit 103 remains 0 and is rejected without being taken into the response side module. The above is the same as the conventional method except that the own address valid signal 16 is set to 1.

The feature of the present invention resides in the own address valid signal 16.

As described above, the address value of the requesting module 3 is set in the partner address register 9 of the responding module 4, and the output of the partner address matching mask circuit 12 is set to 0. At this time, if the own address valid signal 16 is set to 1, the data sent from the request side module 3 is always taken in by the response side module 4. Consider a case where the requesting module 3 transfers data to a module other than the responding module 4 when the responding module 4 is set as described above. Here, consider the case where data is transferred to the responding module 18.

When the requesting module 3 acquires the right to use the bus, the requesting module 3 sets its own address to the bus 1, the address of the responding module 18 to the bus 2, and the own address valid signal 16 to 0. At this time, the response side module 18 stores the data exactly as in the conventional method. By the way, the response side module 4 makes the transferred own address match the value of the partner address register 9 and the output of the own address matching circuit 8 becomes 1, but the own address valid signal 16 becomes 0, so the own address is The output of the match mask circuit 17 remains 0 and no data is stored.

In this way, while the response-side module 4 receives only the data of the request-side module 3, the request-side module 3 can communicate with modules other than the response-side module 4 as the request-side module.

As described above, by providing the own address valid signal, the request side module becomes the request side module with respect to the other modules, and the data transfer can be performed while the data is transferred only with the specific module. Therefore, during the second data transfer operation, the requesting module can perform the first data transfer operation with other modules.

As described above, according to the present invention, the own address valid signal is provided on the bus, and the transmitting / receiving circuit of the self address valid signal in each module, the address indicating each module itself and the request side module are transmitted. The other party's address matching circuit that determines that the other party's address matches, the other party's address register that sets the received other party's address, and the fact that the value of the other party's address register matches the own address sent from the requesting module. Judgment own address match circuit, partner address match mask circuit that masks the partner address match circuit, own address match mask circuit that masks the output of the own address match circuit when the own address valid signal sent from the requesting module is not output And have. By doing so, if at least one of the conditions of the partner address match circuit is satisfied and is not masked, or the condition of the partner address match circuit is satisfied and the own address valid signal is output, the condition is satisfied. In addition, by making it the response module, the effect that the request side module can become the request side module and transfer the data to other modules while the data transfer is performed only with the specific module is there.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 3 is a time chart showing the operation of the figure, and FIG. 3 is a diagram showing an example of the bus system. Description of main part code 1,2 ...... Bus (upper and lower 8 bits each) 3 ...... Request side module 4 ...... Response side module 7 ...... Destination address register 8 ...... Own address matching circuit 9 ...... Destination address register 10 …… Own address register 12 …… Own address match mask circuit 13 …… Own address valid signal transmission circuit 14 …… Reception recognition flip-flop 17 …… Own address match mask circuit

Claims (1)

[Claims] 1. A plurality of modules are provided, each module having an address indicating itself, the data transfer source module using its own address as a transfer source address SA, and the address of a partner module to which data transfer is to be performed. An inter-module data transfer device in a bus communication system in which communication between modules is performed via the common bus by sending the address DA to the common bus, and the transfer source address SA of each module is valid. An address valid signal transmission bus for transmitting an address valid signal indicating invalidity is provided to each module, and each of the modules transmits the transfer source address SA and the transfer destination address DA to the common bus before data transfer. In addition, an address valid signal indicating that the transfer source address SA is valid is invalid. Means for sending relative effective signal transmission bus, a register means for the module itself to preset the address of the other modules to be subjected to data transfer, the transfer source address SA received from said common bus
And a second match detecting means for detecting a match between the register address and the set address of the register means, and a second match detecting means for detecting a match between the own address and the transfer destination address DA received from the common bus.
Match detection means, invalidation means for invalidating the detection result of the second match detection means, and the common bus when the second match detection means detects a match during non-invalidation control of the invalidation means. The means for instructing to take in the above data and the address valid signal received from the address valid signal sending bus at the time of invalid control of the invalidating means are valid and the first match detecting means has detected a match. And a means for instructing to take in the data on the common bus only when the inter-module data transfer apparatus.