JPS62113258A - Bus controller - Google Patents

Abstract

PURPOSE:To communicate with only a specific module by providing each module internally with a control circuit which operates an answer-side module when the coincidence output of an opposite address coincidence circuit is not masked by an opposite address mask circuit or when the address coincidence circuit of this module generates a coincidence output. CONSTITUTION:Each module is provided internally with the opposite address coincidence circuit 7 which decides the coincidence between the 2nd address of this system and the 1st opposite address, the opposite address register 9 which sets the 2nd opposite address, a module address coincidence circuit 8 which sets the coincidence between the set address of the opposite address register 9 and the 1st address of this module, an opposite address mask circuit 12 which masks the output of the opposite address coincidence circuit 7 by setting the 2nd opposite address, and the control circuit which operates an answer-side module when the opposite address coincidence circuit 7 generates a coincidence output and the output is not masked by the opposite address mask circuit 12 or when the module address coincidence circuit 8 generates a coincidence output. Consequently, a communication with only a specific module is made and respective processes are carried out securely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus control device in an information processing device.

[Conventional technology]

A widely used method is to connect the b&'l modules by a bus and to communicate with each other via this bus. An example of such a bus/stem is shown in the block diagram of FIG. In this case, multiple modules (1)---<n) are connected to the bus,
In addition, each module (1) --- (n) has (
1) Set the address of ---(n). and.

Each module performs data transfer by sending the address set for itself and the address set for the other party with which it wishes to communicate onto the bus (1, 2).

For example, consider the case where data is transferred from module (1) to module (2). First, module (1)
performs an operation to acquire the right to use the bus, and when this module (1) acquires the right to use the bus, the requesting module
address (hereinafter abbreviated as SA) on the bus.
(1), the address (2) of the person with whom you wish to communicate (hereinafter abbreviated as DA), and necessary data are sent. module(
When 2) recognizes that the DA sent by the chivalry-seeking module is its own address (2), it becomes the responding module, takes in the sent SA, DA, and data, and performs the necessary operations. , data transfer ends.

Next, from module (1) to all other modules (
2) Consider the case of data transfer to ---(n). When module (1) acquires the right to use as described above, it sends on the bus a shortened broadcast communication address (hereinafter abbreviated as GA) that indicates the destination of all modules as SA (1) and DA. Send the necessary data. When all other modules recognize that the DA sent by the supporting side 7 Joules is OA, they become responding modules, take in the sent SA, DA, and data, perform further necessary operations, and transfer the data. ends.

As described above, in the conventional bus control system, only one-to-one communication between a requesting module and a responding module or communication between a requesting module and all other modules can be performed.

[Problem that the invention seeks to solve]

In the conventional bus control method described above, a response is issued when the requesting module that has acquired the right to use the bus matches its own address with the destination address sent, or when the destination address is a predetermined broadcast communication address. Since this method communicates only with one specific module next to the side module, it is not possible to reject data from other modules on the bus, which has the disadvantage that processing may not be consistent. .

An object of the present invention is to provide a bus control device that solves these drawbacks and allows communication only with a specific module to reliably intercept processing. Means for Solving the Problems] In the bus control device of the present invention, the requesting module sets its own address as the first own address, the address of the communication partner as the first partner address, and the responding module In the bus control device in which each module sets its own address as a second own address and the address of the other party to communicate with as the second partner address, communication is carried out between these seven seals by transmitting the information on the bus. a partner address matching circuit that determines whether a second own address matches the first partner address; a partner address register that sets the second partner address; and a partner address matching circuit that determines whether the second own address matches the first partner address; a own address matching circuit that determines a match with the own address; a partner address mask circuit that masks the output of the partner address matching circuit by setting the second i+1+ address;
Each module is provided with a control circuit that operates the response module when there is a matching output from the partner address matching circuit and it is not masked by the partner address masking circuit or when there is a rare matching output from the own address matching circuit. It is characterized by

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a time chart showing the operation shown in the figure, and here, an example of a 2-byte parallel bus is shown. In the figure, l and 2 are the upper 8-bit bus and the lower 1111 8-bit bus, respectively, and 3.4ff are modules that can be connected to these buses 1 and 2. Here, the requesting module is 3 shows the case where data is transferred from the responding module 4 to the responding module 4.

In addition, 5 is a buffer for receiving data, 6 is an address buffer for storing SA and DA'f transferred from the requesting module, and 7 is a buffer for storing 1) A and the self of the responding module transferred from the requesting module. 8 is a self-address matching circuit that determines that the SA transferred from the Shunsui side module matches the contents of the partner address register of the responding module; 10 is a self-address register of the responding module 4, 11 is a processor that controls the inside of the responding module 4, 12 is a destination address matching mask circuit, and 14 is a register in which the transferred data is set. A reception recognition flip-flop that is set when it recognizes that it is addressed to itself; 15 is a module with the same configuration as the response module 4; 21 is a bus clock line; 22 is an internal bus of the response module; 31 and 32 are OR circuits. , 33 are AND circuits, and these circuits 31
33 constitute a control circuit.

Let us now consider the case where data is transferred from the requesting module 3 to the responding module 4.

First, when the requesting module 3 acquires the right to use the bus, it sends the address of the responding module 4 to its own address bus l to the bus 2. In this case, the data on bus l is SA and the data on bus 2 is l)A. The sent DA is input to the destination address matching circuit 7 inside the response module 4, and the value of the own address register IO of the response module 4 and the output of the destination address matching circuit 7 or rlJ when there is one DA are input. becomes. In this case, if the destination address matching mask circuit 12 is set to "J1", the one-way recognition flip-flop 14 is set to "l" at the next rising edge of the bus clock, and at the same time SA and D
A is stored in the address buffer 6 (Fig. 2), and then 8
The data following A and DA is stored in the data buffer 5 for every J rough of the bus (Figure 2).The data sent from the requesting module 3 in this way is stored in the responding module 4.
Receive crab.

By the way, for example, the processor 11 sets the destination address register 9 of the responding module 4 to the treated water side 7ji 1. -Le 3
Assume that the address value indicating the address matching mask circuit 12 is set to [1-1]. As described above, when the requesting module 3 acquires the right to use the bus, it sends SA to bus 1 and DA to bus 2. The SA sent from the requesting module 3 is input to the own address matching circuit 8 in the responding module 4, and when the SA matches the value of the partner address register 9 of the responding module 4, the own address is The output of the matching circuit 8 becomes "1", and SA is then performed in the same manner as described above.

1) Store A into address buffer 6 and data into data buffer 5, respectively.

Next, if the address value indicating the requesting module 3 is set in the partner address register 9 of the responding module 4, and the output of the partner address matching mask circuit 12 is set to "0", the requesting module 15 transfers data to the responding remote module 4 using the conventional method.

At this time, the output of the partner address matching circuit 7 becomes "l-1", but the output of the partner address matching mask circuit 12 becomes "0".
Therefore, the output of the AND circuit 33 remains "0".

It is rejected without being taken into the responding module 4.

In this way, the responding module 4 can only receive data from the requesting module 3 and reject data from other modules.

As explained above, each module can communicate only with a partner whose address has the value set in the partner address register in each module.

〔Effect of the invention〕

As explained above, the present invention includes a single destination address circuit that determines whether the address indicating each module itself matches the destination address transmitted from the requesting module;
The destination address register to set the address of the destination you want to receive, the value of this destination address register and the request (1+1
It has a self-address matching circuit that determines that the own address transmitted from the 1 module matches, and a partner address matching mask circuit that masks the partner address matching circuit, and masks the partner address matching circuit. By making it possible to become a responding module only when the conditions of the first self-address h118 are matched, one specific module
Since it is possible to reject take from other modules on the bus without having to do much communication between modules, each process can be reliably executed without causing problems in the processes.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a block diagram of an example of a conventional bus system. l...Bass (top 8 picks l-), 2...
・Bass (lower 8 bits, G), total...Requires -jF, side module, 41169. . Responder module, 5...Take buffer, 6
...°° Atres bar, Fa, 7-=°°° Other address matching circuit, 8゛-°-° Self-address matching circuit, 9.
・・・・・・Other address register, lO・・・・・・Self address register, 11・°′・= F0 SET, S, 1
2...°゛Counter address matching mask circuit, 14...
15...Moseal, 21...Bus clock M, 22...
・・・Internal bus, 23...Mask circuit set clock, 31.32・°゛・°°OR circuit, 3: U・
・Par° logical AND circuit. Agent Patent Attorney Uchihara Ren Figure 1

Claims (1)

[Claims] The requesting module sets its own address as the first own address and the address of the communication partner as the first other address, and each responding module sets its own address as the second own address and sets the address of the other party with which it should communicate. In a bus control device that transmits a second address on a bus to communicate between these modules, a partner address matching circuit that determines whether the second own address and the first partner address match; a partner address register for setting the second partner address; a own address matching circuit for determining whether the address set in the second partner address register matches the first own address; If there is a matching output from the partner address mask circuit masked by the setting of the partner address in step 2 and the partner address matching circuit and it is not masked by the partner address mask circuit, or if there is a matching output from the own address matching circuit, the response A bus control device characterized in that each module includes a control circuit for operating the side modules.