JPS6227848A - Bus control system - Google Patents

Abstract

PURPOSE:To enable a module set at the request side and acquired the bus using right to perform communication with optional plural modules at a time, by obtaining a module at the answer side in case the conditions of an own side address coincidence circuit or a remote side address coincidence circuit are satisfied. CONSTITUTION:The own address SA sent out of a module 3 at the request side is supplied to an own address coincidence circuit 8 set inside of a module 4 at the answer side. When the coincidence is secured between the value of a remote side address register 9 of the module 4 and the address SA, the output of the circuit 8 is set at '1'. Then both the address SA and the remote side address DA are stored in an address buffer 6 in an exactly same procedure. At the same time, data are stored in a data buffer 5. Here a module 15 can also store data in an exactly same procedure as the module 4 and simultaneously with the module 4 as long as the own address of the module 3 is set inside the module 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus control method, and particularly to a bus control method in an information processing device.

[Conventional technology]

Conventionally, this type of bus control system includes a bus system in which a plurality of modules are connected via a bus, and each module communicates via the bus.

As shown in Figure 3, in such a bus system, a plurality of modules...n are connected to the bus, and addresses 1...n are set for each module...n. Each module is configured to perform data transfer by transmitting onto the bus the address set for itself and the address set for the other party with which it wishes to communicate.

For example, when transferring data from module 1 to module 2, module 1 first performs an operation to acquire the right to use the bus. Once module 1 acquires the right to use the bus, it becomes the requesting module and transfers its own address onto the bus. (hereinafter abbreviated as SA), address of the party to communicate with (hereinafter abbreviated as DA) ``2'', and necessary data are sent.

When module 2 recognizes that the destination address DA sent by the requesting module is its own address 2'', it becomes the responding module and uses the sent own address S.
A. The other party's address DA and data are taken in, further necessary operations are performed, and the data transfer is completed.

Then from module 1 to all other modules 2...
・When transferring data to n, module 1 acquires usage rights in the same manner as above, and transfers data to address SA 1°' on the bus.
A predetermined broadcast communication address (hereinafter abbreviated as GA) indicating destination for all modules as the destination address DA and necessary data are sent. When all other modules recognize that the destination address DA sent by the requesting module is the broadcast communication address GA, they become responding modules and take in the sent own address SA, destination address DA, and data, and further perform necessary The operation is performed and the data transfer is completed.

As described above, in the conventional bus control system, only one-to-one communication between a requesting module and a responding module or communication between a requesting module and all other modules can be performed.

[Problem that the invention seeks to solve]

In the conventional bus control method described above, a requesting module that has acquired the right to use the bus communicates with a module whose address matches the destination address it sends, or sends a predetermined broadcast communication address to the destination address DA.
By using it as a bus, data is transferred with all modules on the bus other than the requesting module, so the requesting module that has acquired the right to use the bus can communicate with any number of modules at the same time. The drawback was that it could not be done.

[Means for solving problems]

The bus control method of the present invention has a plurality of modules, and in a bus control method in which a requesting module performs communication by transmitting its own address on the bus as its own address and the address of a responding module as a destination address, the bus control method has multiple modules. A partner address-circuit that determines whether the own address it owns in each module connected above matches the partner address sent from the requesting module, and a partner that sets the address of the partner to whom it wants to receive data. It has an address register and a self-address matching circuit that determines whether the value set in the partner address register matches the self-address transmitted from the requesting module.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the invention. In FIG. 1, this embodiment has a plurality of modules 3.4.15, each connected via a bus 30.

Each module can be a requesting module or a responding module, but the bus control method is such that the requesting module communicates by sending its own address as its own address and the responding module's address as the destination address on the bus 30. For example, each module (for example, module 4) includes a partner address matching circuit 7 that determines whether the own address it owns matches the partner address sent from the requesting module, and a partner address matching circuit 7 that determines whether the own address it owns matches the partner address sent from the requesting module. , and a self-address matching circuit 8 that determines whether the value set in the partner address register 9 matches the self-address register transmitted from the requesting module.

Furthermore, the module 4 has a logical sum of the outputs of the data buffer 5 and address buffer 6 connected to the bus 30, the own address register 10 that stores the own address, the other address matching circuit 7, and the own address matching circuit 8. a reception recognition flip-flop 14 connected to the OR circuit 102 and whose output supplies the address buffer 6;
A logical sum circuit 101 that takes the logical sum of the outputs of the bus crosstalk line 21 and the logical sum circuit 101 and supplies the output to the data buffer 5.
and a processor 11 that is connected to an internal bus 22 and performs various controls.

The internal bus 22 of each module is connected to a data buffer 5 and an address buffer 6, and further connected to a partner address register 9.

The bus 30 connected to each module has a bus 31 for upper 8 bits and a bus 32 for lower 8 bits, and both buses 31 and 32 are connected to a data buffer 5 and an address buffer 6.
The upper 8 bits of the bus 31 are connected to the own address matching circuit 8, and the lower 8 bits of the bus 32 are connected to the other address matching circuit 7.

In this embodiment, when data is transferred from the module 3 to the module 4, the requesting module 3.4 is the responding module 4. The data buffer 5 is a buffer for receiving data, and the address buffer 6 is a buffer that stores the own address SA and the other party's address DA transferred from the requesting module 3. The destination address matching circuit 7 is a matching circuit that determines whether the DA transferred from the requesting module matches the own address of the responding module, and the own address matching circuit 8 judges whether the DA transferred from the requesting module matches the own address SA transferred from the requesting module. This is a matching circuit that determines whether the contents of the partner address register of the responding module match. The destination address register 9 is a register in which the processor 11 sets the address of the destination to which data is to be received, and the own address register 10 is a register that stores the own address of the responding module. Reception recognition flip-flop 1
4 is a reception recognition flip-flop which is set when it is recognized that the transferred data is addressed to itself. Note that the module 15 is a module having exactly the same configuration as the response side module 4.

Next, to explain the operation of this embodiment, when data is transferred from the request side module 3 to the response side module 4,
First, when the requesting module 3 acquires the right to use the bus, it sends the address of the responding module 4 to its own address bus 31 and to the bus 32. In this case, the data on the bus 31 is the own address SA, and the data on the bus 32 is the other address DA. The sent destination address DA is input to the destination address matching circuit 7 inside the responding module 4, and when the value of the own address register 10 of the responding module 4 and the destination address DA match, the output of the destination address matching circuit 7 is The reception recognition flip-flop 14 is set to "1" at the next rising edge of the bus clock, and at the same time the own address SA and the other party's address D are set to "1".
A is stored in the address buffer 6, and further the own address S
The data following A and the destination address DA are stored in the data buffer 5 every bus clock. In this way, the response module 4 receives the data sent from the request module 3. FIG. 2 shows the above-mentioned contents in the form of a time chart.

Next, the processor 11 sets the own address of the requesting module 3 in the partner address register 9 of the responding module 4. When the requesting module 3 acquires the right to use the bus in the same manner as above, the own address SA bus 11
\, sends the destination address DA to bus 2. in this case,
The destination address DA may be any value.

The own address SA sent from the requesting module 3 is
Own address matching circuit 8 inside the responding module 4
When the value of the partner address register 9 of the responding module 4 and the own address SA match, the output of the own address matching circuit 8 is 1°.

Then, in exactly the same procedure as above, own address SA,
The destination address DA is stored in the address buffer 6, and the data is stored in the data buffer 5.

At this time, if the own address of the requesting module 3 is set in the partner address register inside the module 15, the module 15 can also store data simultaneously with the responding module 4 in exactly the same procedure as the responding module 4.

〔Effect of the invention〕

As explained above, the present invention includes, in each module, a partner address matching circuit that determines whether the own address that the module owns and the partner address sent from the requesting module match, It has a remote address register that sets the value of the target address register, and a self address match circuit that determines whether the value of the partner address register matches the own address sent from the requesting module, and the condition of either of the two match circuits is set. By allowing the requesting module to become the responding module when the following is satisfied, the requesting module can communicate with any number of modules simultaneously.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a time chart in this embodiment, and FIG. 3 is a diagram showing a conventional bus system. 3...Request side module, 4...Response side module, 5...Data buffer, 6...Address buffer, 7...Other address matching circuit, 8...Self address matching circuit, 9. ...Partner address register, 10...
Own address register, 11... Processor, 14...
・Reception recognition flip-flop, 15... module,
21...Bus clock line, 22...Internal bus, 30
...Bus, 101.102...OR circuit. Agent: Ryo Kado ＼P】l, 13'?
-'2, -ノ

Claims (1)

[Claims] In a bus control method that has multiple modules and communicates by sending the requesting module's own address on the bus as its own address and the address of the responding module as the destination address, each module connected on the bus A partner address matching circuit in the module that determines whether the own address that the module has and the partner address sent from the requesting module matches, a partner address register that sets the address of the partner to whom the request is to be received, and the partner address. A self-address matching circuit that determines whether the value set in the register matches the self-address transmitted from the requesting module, and at least one of the conditions of the self-address matching circuit and the other address matching circuit is satisfied. This bus control method is characterized in that the module becomes the responding module when the module is activated.