JPH0521377B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a data transmission method for a data way system that connects a plurality of terminal devices to one data station. (Prior technology) A data way system connects a large number of terminal devices (including computers) with data stations and transmission lines in a ring-like, bus-like, or point-to-point data way, and is distributed or hierarchical. data exchange between terminal devices. FIG. 2 shows a ring-shaped data way system, in which terminal devices 1 ₁ to 1 ₄ are respectively connected to data stations 2 _{1 to 1} 4 .
2 ₄ , and transmission lines 3 ₁ to 3 are connected between each station.
3 ₄ is connected in a ring shape. Each data station 2 ₁ to _{2 4} is assigned a station address, and data transfer from a terminal device (source) on the data sending side to a terminal device (destination) on the receiving side is sent to the sending data. The source station address and the destination station address are added and transferred from the source station to the ring-shaped transmission path, and the receiving station captures the data when the destination address attached to the received data matches its own address. The received data is transferred to the terminal device connected to the station. In such a data way system, only one terminal device can be connected to the data stations making up the network. Further, the point-to-point multiplexing device connects a pair of data stations 4 ₁ and 4 ₂ with a transmission line 5 as shown in FIG.
Both stations 4 ₁ and 4 ₂ have a plurality of terminal devices 6 ₁
~6 _o and 7 ₁ ~7 _o can be combined, respectively,
Data transmission between terminal devices has been fixed on a one-to-one basis between the source side and the destination side. _For such _a system _{, as shown in FIG .} The system can make efficient use of transmission paths and improve system functionality. Data transmission in this system involves not only attaching a source station address and a destination station address to the transmitted data, but also attaching at least a terminal address indicating to which terminal device of the station address the data is to be transmitted. A common buffer is provided for each terminal device, and after data is received, the terminal device to which the received data is to be transferred is identified from the terminal address, and then the data is transferred to the terminal device. (Problem to be Solved by the Invention) In a data way system in which a plurality of terminal devices are connected to each station, the receiving station determines which terminal device the data should be transmitted to after determining whether the station addresses match. A two-step identification process is required, in which data is transferred to the terminal device after it is identified by the terminal address. For this reason, there was a problem that data transfer efficiency was poor and high-speed transmission was difficult. The present invention enables efficient and high-speed data transmission in block units between a plurality of terminal devices within a local station connected to one data station, and between arbitrary terminal devices connected to both the local station and other stations, respectively. The purpose is to provide a data transmission method that can (Means and effects for solving the problem) A terminal address is attached to the frame transmitted from the transmitting side in addition to the destination station address, and the receiving data station has an address bus, data bus, and control bus. A terminal address bus is provided, and means for writing the terminal address into the register after detecting a match between the station addresses, and a means for outputting the memory address of the transfer destination to the address bus every time received data is transferred to the reception buffer memory, and at the same time writing the contents of the terminal address register. A communication control unit including means for outputting to a terminal address bus is provided, and when address data on the terminal address bus matches the address of a terminal device to be connected, data is written to a memory area of a receiving buffer designated by the address bus. A terminal interface unit is provided to specify a destination terminal device in parallel with data transfer. (Embodiment) FIG. 1A shows a block diagram of a data station showing an embodiment of the present invention, and FIG. 1B shows a receiving circuit configuration of a terminal interface section and a communication control section. In FIG. 1A, a plurality of terminal devices 13 ₁ to 13 _o are connected to one data station 12,
A ring-shaped data way system is constructed in which the ring-shaped transmission line 14 connects to data stations of other stations, and from the stations to terminal devices. The frame format of transmission data exchanged between the data station 12 and the transmission path 14 is as follows.

[Table] In other words, in addition to the information field I to be transmitted, the transmission data also includes the destination data station address.
DSA, destination terminal address DTA, control field C, source data station address SSA, source terminal address STA
, information indicating the contents of the frame, a frame check sequence FCS for data checking, and a flag sequence F for frame synchronization are attached. The data station 12 includes a transceiver unit 15 that mutually converts signals on the transmission path 14 and electrical signals within the station, and a communication control unit that mutually converts serial input/output signals of the transceiver unit 15 and parallel signals on the internal bus 16. unit 17 and terminal devices 13 ₁ to 1
3. A transmission control unit 18 that performs protocol processing for exchanging information with _O and executing transmission procedures, and has a buffer for transmitting and receiving data, and a data transfer rate defined by the transmission rate and the data transfer rate of the terminal device. The communication control _{unit 17}
, transmission control section 18 and interface section 19 ₁ ~
19 _o are connected by an internal bus 16 to exchange information therebetween. In such a configuration, in the data transmission source station, the transmission control unit 18 that has received the transmission request from the terminal device sends the destination station address DSA in addition to the transmission data I from the terminal device.
, destination terminal address DTA, source address SSA, STA, control field C, etc. are added, and the data in the above format is converted into serial data by the communication control section 17, and converted into a transmission signal by the transceiver section 15, and then transmitted. Put it on road 14. The destination data station that receives this data performs serial/parallel (S/P) conversion on the received frame, checks whether the DSA and its own address match, and
If they do not match, data capture is stopped, and if they match, data is captured through serial/parallel conversion until the end of the frame. Frames are captured based on the match between these DSAs and the own address in the same way as in conventional reception processing. In addition, after detecting a match between DSA and its own address, the destination data station uses the terminal address DTA to transfer data to the terminal device to be transferred simultaneously with serial/parallel conversion. Therefore, the communication control unit 17 has an S/P
In addition to the conversion circuit and parallel/serial (P/S) conversion circuit, data is transferred between the transmission/reception buffer of the interface _{section 191} to _19o and the P/S, S/P conversion circuit.
It includes a circuit that performs DMA (Direct Memory Access) transfer. The receiving circuit of the data station is constructed as shown in FIG. 1B. The internal bus 16 includes a first internal bus 16 ₁ consisting of an address bus, a data bus, and a control bus, as well as a terminal address bus 16 ₂ . Terminal address bus 1
6 ₂ connects multiple terminal devices to the internal bus.
Used to distinguish from DTA or STA. After detecting the address match, the communication control unit 17 transfers the DTA data of the received data to the S/P conversion circuit 20.
At the same time, a signal I is sent to the transmission control unit 18 requesting the right to use the internal bus 16.
After receiving the permission signal J from the transmission control section 18, the DMA control circuit 22 is driven. The DMA control circuit 22 causes the data bus buffer 23 to take in the data from the S/P conversion circuit 20 (via the delay buffer 20A during high-speed transmission), and also inputs the data from the reception buffer memory 24 of the interface units 19 ₁ to 19 _o . sets the address data of the address bus buffer 25 and the contents of the DTA register 21 for addressing the received data memory area of the terminal address bus buffer 26;
Write command to set the contents of each buffer 23, 25, 26 to control bus buffer 27
WR outputs to the address bus, data bus, and terminal bus. This control is performed every time received data is transferred, and the memory address and terminal address are updated. The interface units 19 ₁ to 19 _o are connected to the buses 16 ₁ and 16 ₂ by a data bus buffer 28 , an address bus buffer 29 , a terminal address bus buffer 30 , and a control bus 16 1 , as represented by 19 _o . It has a bus buffer 31 to take in data from the communication control section 17 side. The interface units ₁₉₁ to _19o have a terminal address match detection circuit 32, and when a match with the terminal address DTA from the buffer 30 is detected, the data is stored in the memory area of the memory 24 specified by the address data from the buffer 29. Write. For this address specification, a memory select signal for the buffer memory 24 is obtained by the output of the reception buffer selector 33 which takes in the address data of the buffer 29 and the output of the coincidence detection circuit 32. The data written in the reception buffer memory 24 is taken into the terminal devices 13 ₁ to 13 _o after the writing is completed. By receiving data in this way, even if multiple terminal devices are connected to one data station, data can be transferred to the desired terminal device, and the destination terminal device can be specified in parallel with the data transfer. It is possible to obtain a transmission speed equivalent to a transmission system in which the station and the terminal device are one-to-one. In addition, when transmitting data, the terminal address of the transmitter is recognized by the transmitter, so the terminal address and memory address of the interface section where the transmitted data is stored are DTA
It is sufficient to simply write to the address register of the DMA control circuit without using a register. Further, data transfer between terminal devices within the own station is performed between reception buffer memories via buses 16 ₁ and 16 ₂ under the processing of the transmission control section 18 . In addition, although a ring-shaped data way system is shown in the embodiment, it goes without saying that the present invention can also be applied to a bus-shaped data way system or a point-to-point multiplexing device. (Effects of the Invention) According to the present invention, a terminal address is attached to a frame to be transmitted in addition to the destination station address, a terminal address bus is added as an internal bus of the data station, and the receiving data station uses the data station address. When a match is detected, the terminal address data is captured, and the received data is written to the reception buffer of the interface section of the terminal device specified by the terminal address to transfer the received data to the terminal device. This makes selection processing for multiple terminal devices easier. Enables high-speed data transmission in parallel.

[Brief explanation of the drawing]

FIG. 1A is a configuration diagram of a data station showing an embodiment of the present invention, FIG. 1B is a configuration diagram of a receiving circuit in FIG. 1A, FIG. 2 is a configuration diagram of a conventional ring-shaped data way system, and FIG. 4 is a block diagram of a point-to-point multiplexing device, and FIG. 4 is a block diagram of a data way system according to the present invention. 1 ₁ , 1 ₄ ... terminal device, 2 ₁ , 2 ₄ ... data station, 3 ₁ , 3 ₄ ... transmission line, 8 ₁ , 8 _o , 9 ₁ , 9 _o ,
10 ₁ , 10 ₂ , 11... terminal device, 12... data station, 13 ₁ , 13 _o ... terminal device, 14... transmission path, 15... transceiver unit, 16... internal bus,
17... Communication control section, 18... Transmission control section, 19 ₁ ,
19 _o ...terminal interface section, 20...S/P
Conversion circuit, 21...DTA register, 22...DMA control circuit, 23, 28...Data bus buffer, 24
...Reception buffer memory, 25, 29... Address bus buffer, 26, 30... Terminal address bus buffer, 27, 31... Control bus buffer, 32... Terminal address match detection circuit,
33...Receive buffer selector.

Claims (1)

[Claims] 1 Connect each data station with a transmission line,
In a data way system in which multiple terminal devices are connected to each data station and data is transmitted between each terminal device, the source terminal device attaches the destination station address and terminal address data to the frame to be transmitted, and the data station is the internal bus address bus, data bus,
In addition to a bus consisting of a control bus, it has a terminal address bus, and the receiving data station starts receiving data after detecting a match between the station addresses, and also provides means for writing the terminal address of the received frame into the terminal address register, and the receiving data station. a communication control section including means for outputting the memory address of the transfer destination to the address bus each time the data is transferred to the reception buffer memory, and simultaneously outputting the contents of the terminal address register to the terminal address bus; A data transmission system comprising: a terminal interface section that writes data into a memory area of a receiving buffer designated by the address bus when the address data matches the address of a connected terminal device.