JPH0548010A - Input circuit - Google Patents

Abstract

PURPOSE:To effectively propagate an input level to gate means of a semiconductor integrated circuit by disposing a pull-up resistor or a pull-down resistor between an external input terminal and a static eliminator circuit. CONSTITUTION:A pull-up resistor 8 is disposed between an external input terminal 1 and a static eliminator circuit. If the terminal 1 is opened, an input level of an inverter 7 is fed from a positive electrode power source VDD through resistors 8, 4, 5 at a high level, and hence the inverter 7 can output a low level. On the other hand, when the low level is applied to the terminal 1, the input level of the inverter 7 is applied through the resistors 4, 5 at the low level of the terminal 1, and hence the inverter 7 can output a high level. Thus, the input level can be effectively propagated to gate means of a semiconductor integrated circuit.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to pull-up and pull-down resistors.

[0002]

2. Description of the Related Art Taking a pull-up resistor as an example, a conventional technique which has been frequently used from now on will be described with reference to FIG. VDD indicates a positive power source and VSS indicates a negative power source. 1 is an external input terminal to which a signal is input from the outside. Reference numerals 2, 3, 4, and 5 constitute an electrostatic protection circuit for preventing damage to the semiconductor integrated circuit when static electricity is applied to the external input terminal 1. Reference numeral 2 is a clamp diode for absorbing the static electricity to the positive power source VDD when the static electricity having the positive charge is applied to the external terminal 1, and 3 is the static electricity when the static electricity having the negative charge is applied to the external terminal 1. A clamp diode for absorbing the negative power supply VSS, 4 is a resistor for attenuating the energy of static electricity applied to the external terminal 1, and 5 is a resistor for preventing static electricity from flowing into elements such as transistors inside the semiconductor integrated circuit. Is. Reference numeral 6 denotes a pull-up resistor, which is a P-type MOS transistor in this example. Reference numeral 7 denotes a complementary MOS inverter, which indicates a gate means controlled by a signal input to the external input terminal 1.

Usually, the pull-up resistance value is a relatively high resistance of several tens KΩ to several hundreds KΩ. Therefore, in order to reduce the size of the element and obtain high resistance, MOS transistors are often used as pull-up resistors. However, when static electricity is directly applied to the MOS transistor, the MO
There is a risk that the gate film of the S transistor will be destroyed. For the reason described above, the pull-up resistor 6 is connected from the external input terminal 1 to the clamp diodes 2 and 3 and the resistors 4 and 5.
It is placed in a position that goes through an electrostatic protection circuit composed of
And it was made of MOS transistors.

[0004]

However, the above-mentioned conventional techniques have the following problems. In FIG. 4, the pull-up resistor 6 is an MO in which the source and the sub-straight are connected to the positive power supply VDD and the gate is connected to the negative power supply VSS.
Since it is an S-transistor, its resistance value changes with changes in the power supply voltage. 2. Description of the Related Art In recent years, portable devices such as cameras have been increasing in type in which two lithium batteries are connected in series as a power source. In this case, the power supply voltage of the device covers a wide range from 2V to 7V. As is well known, the resistance of the MOS transistor is almost inversely proportional to the square of the power supply voltage. Therefore, if the minimum value and the maximum value of the pull-up resistor 6 are compared, a difference of 10 to 20 times occurs. Pull-up resistor 6
If the resistance value of 1 is large, a malfunction tends to occur due to noise to the external input terminal 1. On the contrary, if the resistance of the pull-up resistor 6 is small, the inverter 7 cannot detect the low level input when the low level (negative power supply VSS level) is input to the external input terminal 1. External input terminal 1
The input level of the inverter 7 when the low level is input to is given by the resistance voltage division of the pull-up resistor 6 and the resistor 4 + the resistor 5. This is shown in FIG. In FIG. 5, the same components as those in FIG. 4 are given the same numbers. The P-type MOS transistor 6 is replaced with a resistance element for the sake of clarity. Since the input level of the inverter 7 is given as shown in FIG. 5, when the resistance 6 becomes too small, the resistance becomes 6 <resistance 4 + resistance 5 and
Even if a low level (level of the negative power supply voltage VSS) is input to the external input terminal 1, the inverter 7 cannot detect the low level and malfunctions.

[0005]

In order to solve the above problems, the present invention provides an input circuit of a semiconductor integrated circuit comprising an external input terminal, a pull-up resistor or a pull-down resistor, and an electrostatic protection circuit. In the above, the pull-up resistor or the pull-down resistor is arranged between the external input terminal and the electrostatic protection circuit.

[0006]

According to the present invention, since the input level is not resistance-divided with the pull-up resistor or pull-down resistor and the resistance in the electrostatic protection circuit, the input level can be reliably transmitted to the gate means in the semiconductor integrated circuit.

[0007]

1 is a circuit diagram of an embodiment of the present invention. In FIG. 1, the same components as those in FIG. 4 are given the same numbers. VDD is a positive power supply and VSS is a negative power supply.
Reference numeral 1 designates an external input terminal, and 2, 3, 4, and 5 constitute an electrostatic protection circuit, and the function thereof is as described in the section of the prior art. Reference numeral 7 is a complementary MOS inverter which is a gate means controlled by a signal input to the external input terminal 1. 8 is a pull-up resistor. Pull-up resistor 8
Are arranged between the external input terminal 1 and the electrostatic protection circuits of 2, 3, 4, and 5. Next, the operation will be described.
When the external input terminal 1 is open, the input level of the inverter 7 is from the positive power source VDD to the resistors 8, 4, and 5.
Since a high level is given through the inverter, the inverter 7 can output a low level. (Impedance of resistance 8 + resistance 4 + resistance 5 << input impedance of inverter 7)
On the other hand, when a low level is applied to the external input terminal 1, the input level of the inverter 7 is low because the low level of the external input terminal 1 is applied via the resistors 4 and 5. Can be output. Although the above description is about the pull-up resistor, it goes without saying that when the resistor 8 is connected to the intersection of the external input terminal 1 and the resistor 4 and the negative power source VSS, the input circuit has a pull-down resistor. is there.

In the present invention, since the pull-up resistor or pull-down resistor is connected to the external input terminal without passing through the static electricity protection circuit, the static electricity applied to the external input terminal is directly pulled up or pulled down. Apply to. Therefore, in order to secure the electrostatic resistance of the pull-up resistor or the pull-down resistor, a resistance element is used without using a MOS transistor whose gate oxide film or the like is easily damaged by static electricity. A layout diagram of this resistance element in the semiconductor integrated circuit will be described.

FIG. 2 shows a pull-up resistor or pull-up resistor.
FIG. 6 is a layout diagram showing a first example of a resistance element used for a down resistance. In FIG. 2, reference numeral 1 denotes an external input terminal, which is usually connected to the external terminal by bonding or the like. Reference numeral 9 is an aluminum wiring, which is then connected to an electrostatic protection circuit. 10
Is the same high-concentration impurity diffusion layer as the source or drain in the semiconductor integrated circuit, and this high-concentration impurity diffusion layer 10 serves as a pull-up resistance or a pull-down resistance. 11
Indicates a low concentration impurity diffusion layer having the same polarity as the high concentration impurity diffusion layer 10. The high-concentration impurity diffusion layer 10 is surrounded by the low-concentration impurity diffusion layer 11. A contact 12 electrically connects the high-concentration impurity diffusion layer 10 and the aluminum wiring. 1
3 is aluminum for the power supply wiring, which is a high-concentration impurity diffusion layer 10
Is used as the pull-up resistance, the positive power supply VDD is shown, and when the high-concentration impurity diffusion layer 10 is used as the pull-down resistance, the negative power supply VSS is shown. The low-concentration impurity diffusion layer 11 is for separating the high-concentration impurity diffusion layer 10 from the substrate, and is for preventing the PN junction between the high-concentration impurity diffusion layer 10 and the substrate from being formed. When static electricity is applied between the substrates, the PN junction breakdown between the substrate and the high-concentration diffusion layer 10 is prevented, and the electrostatic withstand capability is improved.

FIG. 3 shows a second example of the resistance element used for the pull-up resistance or pull-down resistance. 2 that are the same as those in FIG. 2 are given the same numbers as in FIG. The example of FIG. 3 is an example in which a low-concentration impurity diffusion layer is used as a pull-up resistor or a pull-down resistor rather than a source or a drain in a semiconductor integrated circuit. Reference numeral 11 denotes a lower concentration impurity diffusion layer than the source or drain in the semiconductor integrated circuit, which is a pull-up resistor or a pull-up resistor.
Used as a down resistor. A high-concentration impurity diffusion layer 10 is the same as the source or drain in the semiconductor integrated circuit and is a diffusion layer having the same polarity as the low-concentration impurity diffusion layer 11. Therefore, the high concentration impurity diffusion layer 10 and the low concentration impurity diffusion layer 1
1 is electrically connected. A contact 12 electrically connects the high-concentration impurity diffusion layer 10 and the aluminum wiring. Reference numeral 1 is an external input terminal, 9 is an aluminum wiring, and 13 is an aluminum wiring for a power source. If an attempt is made to electrically connect the aluminum wiring and the low-concentration impurity diffusion layer 11 directly, the resistance of the joint surface between the aluminum wiring and the low-concentration impurity diffusion layer 11 becomes extremely high, so that the aluminum wiring and the high-concentration impurity diffusion layer 10 are connected. And electrically connects to the low-concentration impurity diffusion layer 11. Also in the embodiment of FIG. 3, the high-concentration impurity diffusion layer 1
0 is covered with the low-concentration impurity diffusion layer 11 and improves the electrostatic withstand capability as in the description of FIG. 2 above. Also,
Since the low-concentration impurity diffusion layer is used as the resistance, a relatively high resistance can be obtained.

[0011]

As described above, according to the present invention, the external input level is not divided by the pull-up resistance or pull-down resistance and the resistance in the electrostatic protection circuit, so that it is possible to operate under a wide range of power supply voltage conditions. However, there is no mistaken input of the external input level. It is also possible to reduce the pull-up resistance or pull-down resistance. Normally, the resistance in the electrostatic protection circuit is about several KΩ, so that in the conventional technique, at least several tens KΩ or more is required for the pull-up resistance or the pull-down resistance. However, in the present invention, the external input level is not divided between the pull-up resistance or the pull-down resistance and the resistance in the electrostatic protection circuit, so that the low resistance value is not limited. Therefore, it is possible to obtain a highly reliable semiconductor integrated circuit in which the pull-up resistance or the pull-down resistance is set to several KΩ or less and which is extremely unlikely to be affected by noise entering the external input terminal.

Since the pull-up resistor or pull-down resistor is made of a resistance element instead of a MOS transistor, a stable and highly accurate pull-up resistor or pull-down resistor can be obtained even when the power supply voltage fluctuates. ..

Further, since the pull-up resistor or pull-down resistor is arranged in parallel between the external input terminal and the power source together with the electrostatic absorption clamp diode in the electrostatic protection circuit, the electrostatic absorption path is increased. It also has the effect of improving the electrostatic resistance.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a layout diagram showing an embodiment of a resistance element of the present invention.

FIG. 3 is a layout diagram showing another embodiment of the resistance element of the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional technique.

FIG. 5 is a circuit diagram showing an example of a problem of the conventional technique.

[Explanation of symbols]

1 External input terminal 2, 3 Clamp diode 4, 5 Resistance 6 P-type MOS transistor 7 Complementary MOS inverter 8 Pull-up resistance 9 Aluminum wiring 10 High concentration impurity diffusion layer 11 Low concentration impurity diffusion layer 12 Aluminum wiring and high concentration Contact that electrically connects the impurity diffusion layer 13 Aluminum wiring for power supply

Claims (3)

[Claims] 1. An input circuit of a semiconductor integrated circuit comprising an external input terminal, a pull-up resistor or pull-down resistor, and an electrostatic protection circuit, wherein the pull-up resistor or pull-down resistor is the external device. An input circuit characterized by being arranged between an input terminal and the electrostatic protection circuit. 2. The pull-up resistor or pull-down resistor according to claim 1, which is formed of the same high-concentration impurity diffusion layer as a source or a drain in a semiconductor integrated circuit, and the high-concentration impurity diffusion layer is formed of the high-concentration impurity diffusion layer. An input circuit characterized by being covered with a low-concentration impurity diffusion layer of the same polarity as the diffusion layer. 3. The input circuit according to claim 1, wherein the pull-up resistor or pull-down resistor is formed of a lower concentration impurity diffusion layer than a source or a drain in the semiconductor integrated circuit.