JPH0537390A - Data processing signal generating circuit - Google Patents

Abstract

PURPOSE:To reduce the deviation of the rising time or falling time of a processing signal, to hold the ON state of the above-mentioned processing signal only while transmitted data are generated, and to prevent the generation of the processing signal for a single pulse signal. CONSTITUTION:In a data processing signal generating circuit which generates a processing signal RD2 for processing transmitted data TD, a second flip flip 15 prepares and outputs the processing signal RD2 corresponding to the second pulse edge from the head of the transmitted data TD. Thus, the output of an AND circuit 16 is turned to a high level, a second counter circuit 17 starts a count by fetching a clock (a) from an outside after a clear release is operated, outputs a high level output signal (i) after the lapse of a prescribed time in order to clear the second flip flop 15, and stops the generation of the processing signal RD2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing signal generating circuit for generating a processing signal for processing transmission data of a network.

[0002]

2. Description of the Related Art Conventionally, a method for transmitting transmission data of a network, particularly a local area network,
There is a Manchester system in which one logical bit of transmission data is divided into two small bit sections and processed. In the Manchester method, when processing transmission data, a signal indicating a period in which the transmission data exists may be required as a basic processing signal. The processing signal is the first part of the transmission data. It became high level, and at the last part it became low level, indicating the period during which the transmission data existed. As a circuit for generating this processed signal, an integrator circuit or a monostable multivibrator whose rise time is slow with respect to the input signal is used. For example, as shown in FIG. 4, the transmission data (see FIG. 4 (a)) is transferred to the above circuit. To a single constant signal (see FIG. 4 (b)) and then waveform shaping by a logic circuit to generate a processed signal as shown in FIG. 4 (c).

[0003]

However, since the signal generation circuit described above generates a signal by using the time constants of the capacitor and the resistance, the generated signal waveform has variations in the time constant and temperature. There is a problem in that the range in which the rise time and the fall time vary greatly due to changes and the like. Further, in the above Manchester system, when the transmission data does not exist for a long time, or when the voltage is held in the opposite voltage, the generated signal needs to be in the off state, but is kept in the on state forever, There is a problem that it reacts to a single pulse signal such as noise other than the transmission data, and a processed signal is generated in a period other than the transmission data period.

The present invention has been made in view of the above-mentioned problems, and there is little deviation between the rising time and the falling time of a signal, the ON state of the signal is held only during the generation period of the transmission data, and the single state is maintained. An object of the present invention is to provide a data processing signal generation circuit that does not generate a signal for a pulse signal.

[0005]

The present invention has been made in view of the above problems, and in a data processing signal generating circuit for generating a processing signal for processing transmission data, at least one of the data processing signal generation circuits includes the transmission data. First signal generating means for generating an output signal in response to the application of the pulse signal, and second signal generating means for triggering the transmission data in response to the output signal from the first signal generating means to generate the processed signal. The clear state is released in response to the signal generation means and the output signal from the first signal generation means and the pulse signal, a constant clock signal is counted, and when the count value reaches a predetermined value, the first and the first The first counting means for clearing the second signal generating means and the clear state are released according to the output signal and the pulse signal from the second signal generating means, and the constant clock is counted. , Processing the signal generating circuit comprises a second counting means the count value to clear the first and second signal generating means and a predetermined value is provided.

[0006]

The clearing period of the first counting means, which is performed by the output signal from the first signal generating means and the generated single pulse signal, is a period in which no transmission data exists.
The first counting means clears the first and second signal generating means so as not to generate a processing signal, and the second counting means is constituted by the output signal from the second signal generating means and the transmission data.
Since the clearing period of the counting means is the period in which the transmission data exists, the second counting means clears the first and second signal generating means after the transmission data no longer exists, and outputs the processed signal. Terminate the generation.

Therefore, if the output of the processed signal is the output of the second signal generating means, the processed signal can be output during the input period of the transmission data.

[0008]

Embodiments of the present invention will be described with reference to the drawings of FIGS. FIG. 1 is a diagram showing a data processing signal generation circuit according to the present invention using the Manchester method. In the figure, the first flip-flop 11 has transmission data TD
Is used as a trigger input, and the signal c is output from the output terminal Q to the AND circuit 13.

In addition to the output from the first flip-flop 11 described above, the transmission data TD is input to the AND circuit 13 via the knot circuit 12, and the AND circuit 13 outputs, when both signals are at a high level, The clear cancellation signal e is output to the first counter circuit 14. The output of the AND circuit 13 is in a low level state when there is no transmission data, and is in a high level state when there is high level transmission data.

The counter circuit 14 is in a state where the count is cleared when the output of the AND circuit 13 is in the low level state, and is cleared when the output of the AND circuit 13 is in the high level state. The clock signal a is taken in to start counting, and after t ₄ hours, for example, a high-level output signal RD ₁ is output to the first and second flip-flops 11 and 15 via the NOR circuit 18, and the flip-flops 11 and 15 are output. Clear 15.

The second flip-flop 15 outputs the output signal c from the first flip-flop 11 to the AND circuit 16 from the output terminal Q by using the transmission data TD input to the input terminal S as a trigger. The output signal RD ₂ from the output terminal Q is a processing signal which indicates the input period of the transmission data TD and serves as a reference for processing the transmission data, and the second flip-flop 15 of the present embodiment has the first flip-flop 15. With respect to the output signal c of the flip-flop 11, the output of the processing signal is started corresponding to the second pulse edge from the beginning of the transmission data.

The AND circuit 16 receives not only the output from the second flip-flop 15 but also the transmission data TD. The AND circuit 16 receives the transmission data TD when both signals are at a high level.
The clear cancellation signal h is output to the second counter circuit 17. The AND circuit 16 outputs a low level signal when the transmission data TD is low level, and outputs a high level signal when the transmission data TD is high level.

The counter circuit 17 is in the state where the count is cleared when the output of the AND circuit 16 is in the low level state, and is cleared when the output of the AND circuit 16 is in the high level state. The clock signal a is taken in, counting is started, and the high-level output signal i is passed through the NOR circuit 18 after, for example, t ₄ hours, and the first and second
To the flip-flops 11 and 15 to clear the flip-flops 11 and 15.

Next, the operation of the data processing signal generation circuit will be described with reference to FIGS. 2 and 3. Figure 2
FIG. 3 is a waveform diagram of each part when a single pulse signal due to noise (see FIG. 2B) is input instead of transmission data during a period A. First, when the single pulse signal is input, the first flip-flop 11 outputs the output signal c having the waveform shown in FIG. On the other hand, since the output of the knot circuit 12 by the single pulse signal becomes the output signal d having the waveform shown in FIG. 2 (d), the output of the AND circuit 13 is
The output signal e becomes the waveform shown in FIG. 2E, and the clearing of the first counter circuit 14 is released. First counter circuit 1
In the clear release state, _{No. 4} receives the clock a from the outside, starts counting, and outputs the high-level output signal RD ₁ (see FIG. 2 (f)) after ₄ hours t ₄ .
It outputs to the first flip-flop 11 via 8. When the output signal RD ₁ is input, the flip-flop 11 is cleared and the output signal c is set to low level.

On the other hand, in the second flip-flop 15,
Even if a single pulse is input, the output terminal Q maintains the low level state, so that the processing signal RD ₂ (see FIG. 2 (g)) is not output. Further, FIG. 3 is a waveform diagram of each part when the transmission data (see FIG. 3B) is input within the period B. The leading bit of the transmission data is, for example, a synchronization bit, and the high level state of the tail bit is a special one indicating the end of the transmission data.

First, when the transmission data TD is input, the first flip-flop 11 outputs the output signal c having the waveform shown in FIG. 3C to the AND circuit 13, and the output of the AND circuit 13 is as shown in FIG. The output signal e has the waveform shown in e). As a result, the first counter circuit 14 is maintained in the clear state, and the output signal RD ₁ remains low level as shown in FIG. 3 (f).

On the other hand, in the second flip-flop 15,
When the transmission data TD is input, the processing signal RD is started from the pulse edge next to the transmission data head (for synchronization) bit.
Output ₂ (see Fig. 3 (g)). Therefore, AND circuit 1
The output of 6 becomes a signal h having a waveform as shown in FIG. 3 (h). When the signal h is at a high level, the second counter circuit 17 is cleared and the clock a from the outside is taken in. , Counting is started, and a high-level output signal i (see FIG. 2 (i)) is output to the second flip-flop 15 via the NOR circuit 18 after t ₄ hours. When the output signal i is input, the flip-flop 15 is cleared and the output signal RD ₂ can be set to the low level.

If no special bit indicating the end of the transmission data is provided at the end of the transmission data, the transmission data TD becomes low level as in FIG. 2B because of the end of the transmission data. The output signals c and d both become high level, and the high-level output signal RD ₁ is output to the second flip-flop 15 after t ₄ hours. Output signal R
When D ₁ is input, the flip-flop 15 is cleared and the output signal RD ₁ can be set to low level.

Therefore, in this embodiment, if the output of the processed signal is set to the second flip-flop 15, the transmission data in the Manchester system is not present, or the transmission data is in the high-level voltage state for a long time. If so, the processed signal can be brought to a low level after a predetermined time, so that the processed signal is not kept in a high level for a long period of time, and the processed signal can be output in conformity with the input period of the transmission data. Further, since the second flip-flop 15 starts outputting the processing signal from the second pulse edge from the beginning of the transmission data, the output of the processing signal can be prevented when a single pulse signal is input.

[0020]

As described above, according to the present invention, in the data processing signal generating circuit for generating the processing signal for processing the transmission data, the data processing signal generation circuit outputs the pulse signal containing the transmission data when the pulse signal is applied. First signal generating means for generating a signal; second signal generating means for triggering the transmission data to generate the processed signal in response to an output signal from the first signal generating means; The clear state is released according to the output signal from the signal generating means and the pulse signal, a constant clock signal is counted, and when the count value reaches a predetermined value, the first and second signal generating means are cleared. The clear state is released according to the output signal and the pulse signal from the first counting means and the second signal generating means, the fixed clock is counted, and the count value is a predetermined value. In that case, since the second counting means for clearing the first and second signal generating means is provided, if the output of the processed signal is the output of the second signal generating means, the rising time and the rising time of the processed signal are increased. It is possible to keep the ON state of the processing signal only during the transmission data generation period with little fall time deviation and prevent the generation of the processing signal with respect to the single pulse signal.

[Brief description of drawings]

FIG. 1 is a diagram showing a data processing signal generation circuit according to the present invention using a Manchester system.

FIG. 2 is a waveform diagram in each part of the data processing signal generation circuit shown in FIG. 1 when a single pulse signal is input.

FIG. 3 is a waveform diagram in each part of the data processing signal generation circuit shown in FIG. 1 when transmission data is input.

FIG. 4 is a waveform diagram in a conventional example when transmission data is input.

[Explanation of symbols]

11,15 Flip-flop 12 Not circuit 13,16 AND circuit 14,17 Counter circuit 18 NOR circuit TD Transmission data RD ₂ Processing signal

Claims (1)

Claim: What is claimed is: 1. A data processing signal generation circuit for generating a processing signal for processing transmission data, wherein an output signal is generated in response to application of at least one pulse signal containing the transmission data. First signal generating means, second signal generating means for triggering the transmission data in response to an output signal from the first signal generating means to generate the processed signal, and the first signal generating means The clear state is released in response to the output signal from the pulse signal and the pulse signal, a constant clock signal is counted, and when the count value reaches a predetermined value, the first and second signal generating means are cleared. When the clear state is released in response to the output signal and the pulse signal from the counting means and the second signal generating means, the constant clock is counted, and when the count value reaches a predetermined value, the first And second signal generating means comprise a second counting means for clearing the data processing signal generation circuit and generates the processed signal indicating the input period of the transmission data.