JPH10336162A - High speed transmission device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform phase adjustment of high speed digital data in a system clock unit. SOLUTION: Input data WD is temporarily stored in a buffer memory 1 in a frame unit. A differential circuit 5 receives a frame pulse FP and a system clock CLK and starts a counter 6 with a leading edge of the frame pulse FP. A load value setting part 7 preliminarily sets necessary delay time. Data RD is read from the memory 1 after the delay time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed digital data transmission apparatus employed in SDH (Synchronous Digital Hierarchy).

[0002]

2. Description of the Related Art A transmission device used in an SDH network, comprising: a frame pulse indicating a head position of a frame;
Some systems perform a data multiplex conversion process by distributing a system clock for signal transmission. At this time, the system clock, the frame pulse, and the data are transmitted through the same cable or back panel. On the receiving side, a method is employed in which a frame pulse or input data is punched out and reproduced by a system clock using a data flip-flop or the like.

[0003]

However, the above-mentioned prior art has the following problems to be solved.
In a high-speed transmission device in which the data transmission speed is 150 Mb / s or more, that is, the system clock exceeds 150 MHz, the phase of the transmission signal is slightly shifted due to variations in driver / receiver elements, transmission delays and variations in cables and back panels. I do. For this reason, there has been a problem that a timing shift occurs such that frame pulses and data cannot be punched out by the system clock. Therefore, it is necessary to perform phase adjustment in system clock units on the receiving side.

[0004]

The present invention employs the following structure to solve the above problems. <Structure 1> A buffer memory for temporarily holding input data and a frame pulse for frame synchronization of the input data are received, differentiated using a high-speed clock, and a differentiated frame pulse is generated at the rising edge of the frame pulse. Receiving the differentiated circuit to be generated and the differentiated frame pulse output from the differentiated circuit, starting counting from the input of the differentiated frame pulse, reading the system clock for input data transfer by counting a preset count value, and then reading out A high-speed transmission device comprising a counter for outputting a frame pulse to the buffer memory and reading input data temporarily stored in the buffer memory.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below using specific examples. FIG. 1 is a block diagram of a high-speed transmission apparatus according to the present invention. The illustrated device includes a buffer memory 1 for receiving and temporarily storing input data WD. The data temporarily stored in the buffer memory 1 is phase-adjusted by this circuit in units of a system clock, and becomes output data RD. For this purpose, a frame synchronization circuit 2, buffers 3 and 4, a differentiation circuit 5, a counter 6, and a load value setting unit 7 are provided.

The frame synchronization circuit 2 is a circuit that receives input data WD, detects a frame synchronization signal, and controls writing of the input data WD into the buffer memory 1 for each frame. The system clock CLK is input to this circuit via the buffer 4 for such a write control. Note that this system clock CLK
Are also supplied to the buffer memory 1 for writing control.

The differentiating circuit 5 is a circuit that receives the frame pulse FP via the buffer 3, differentiates it using the system clock CLK, and outputs a differentiated frame pulse FPA at the rising edge of the frame pulse FP.
Although the specific contents of these signals will be described later, this differentiated frame pulse FPA is input to the counter 6 and resets the counter 6 to start counting.

The counter 6 receives the system clock CLK via the buffer 4 and counts down from the initial value by this clock. The borrow output at the end of the count is a read frame pulse RFP, which is supplied to the buffer memory 1. The load value setting section 7 is a section for setting an initial value to be counted by the counter 6.

This device is intended to delay input data WD in units of a clock of system clock CLK and adjust the phase. The operator inputs and sets the amount of delay using a numerical value from a console (not shown) to the load value setting unit 7. Note that the setting may be made by a dip switch or the like. The amount of delay has various values for each circuit due to variations in elements of drivers / receivers in peripheral circuits and variations in delay times of cables, back panels, and the like. Therefore, it is set by using experimental data or by trial and error. This makes it possible to obtain a timing at which the receiving side can accurately pass through the frame pulse or data with the system clock.

The specific operation of the apparatus shown in FIG. 1 will be described with reference to FIG. FIG. 2A shows the input data WD. Here, data contents are displayed for each bit such as D0, D1, D2,... D7. FIG. 2 (b)
Is a frame pulse FP. When 8 bits are defined as one frame, a frame pulse is generated at time t as shown in FIG.
It indicates a high level from 1 to time t4.

FIG. 2C shows a system clock CLK. It has a repetition frequency that matches the transfer timing of the input data WD. (D) is a differential frame pulse FPA. The differentiating circuit 5 shown in FIG. 1 differentiates the frame pulse FP at the timing of the system clock CLK and outputs a differentiated frame pulse FPA. Therefore, this timing coincides with the first bit of the frame of the input data WD.

FIG. 2E shows a write frame pulse W
FP. This is output from the frame synchronization circuit 2 shown in FIG. 1 and is used for controlling the writing of the input data WD to the buffer memory 1. Thus, the input data WD is written into the buffer memory 1 for each frame.

FIG. 2F shows a read frame pulse R
FP. The read frame pulse RFP is output from the counter 6 when the time T has elapsed after the differential frame pulse FP was input to the counter 6 at time t1. T corresponds to a predetermined count value set in the counter 6 by the load value setting unit 7 and loaded into the counter 6.

The counter 6 loads a predetermined count value set in the load value setting section 7 by the differentiated frame pulse FPA output from the differentiating circuit 5. Thereafter, the counter 6 receives the system clock CLK and decrements the loaded count value. When the count value becomes “0”, a borrow is output to the buffer memory 1.
This is the read frame pulse RFP. Therefore,
In this example, for example, a load value of “5” is set,
After the counter 6 has counted "5", the read frame pulse RFP is output.

When the read frame pulse RFP is input to the buffer memory 1, reading of the input data WD stored in the buffer memory 1 is started from the head.
Thus, the output data RD shown in FIG. 2 (g) is obtained. In the above example, the subtraction counter is used as the counter. However, any counter may be used as long as the system clock is counted, the readout from the buffer memory is started after counting the set number of pulses, and so on. It may be a counter. Of course, a software counter or a hardware counter may be used.

[0016]

In the apparatus described above, a differential frame pulse synchronized with the system clock is generated at the rising edge of the frame pulse, the system clock is counted by the load value loaded into the counter, and the input data stored in the buffer memory is counted. , The phase of input data can be adjusted in clock units of the system clock. As a result, high-speed data can be accurately reproduced on the receiving side without being affected by the transmission delay of the peripheral circuit and other environments.

In addition, since an arbitrary count value can be set in the load value setting section, it is possible to precisely and easily perform phase adjustment of signals in the device in various circuits.

[Brief description of the drawings]

FIG. 1 is a block diagram of a high-speed transmission device according to the present invention.

FIG. 2 is an operation time chart of the high-speed transmission device.

[Explanation of symbols]

 Reference Signs List 1 buffer memory 2 frame synchronization circuit 3, 4 buffer 5 differentiator 6 counter 7 load value setting unit WD input data RD output data FP frame pulse CLK system clock FPA differential frame pulse WFP write frame pulse RFP read frame pulse

Claims (1)

[Claims] 1. A buffer memory for temporarily holding input data, a frame pulse for frame synchronization of input data being received, differentiated by using a high-speed clock, and a differentiated frame pulse at a rising edge portion of the frame pulse. And a differential circuit that receives the differential frame pulse output from the differential circuit, starts counting from the input of the differential frame pulse,
After counting a system clock for input data transfer by a preset count value, a counter for outputting a read frame pulse toward the buffer memory and reading input data temporarily held in the buffer memory is provided. A high-speed transmission device characterized by the above-mentioned.