JPH0522089A - Data processing signal generating circuit - Google Patents

Abstract

PURPOSE:To reduce deviation in the rise time or fall time of a processing signal to the input period of transmitting data. CONSTITUTION:At the data processing signal generating circuit to generate a processing signal RD for processing transmitting data TD, a second flip-flop 12 generates and outputs the processing signal RD corresponding to the pulse edge of the second signal from the head of the transmitting data TD. Thus, the output of an AND circuit 13 is turned to a high level, and a count circuit 14 cancels the clear, fetches a clock (a) from the outside and starts counting. After the lapse of prescribed time, an output signal (f) at the high level is outputted, the second flip-flop 12 is cleared, and the generation of the processing signal RD is stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing signal generating circuit for generating a processing signal for processing transmission data of a network.

[0002]

2. Description of the Related Art Conventionally, a method for transmitting transmission data of a network, particularly a local area network,
There is a Manchester system in which one logical bit of transmission data is divided into two small bit sections and processed. In the Manchester method, when processing transmission data, a signal indicating a period in which the transmission data exists may be required as a basic processing signal. The processing signal is the first part of the transmission data. It became high level, and at the last part it became low level, indicating the period during which the transmission data existed. An integrator circuit or a monostable multivibrator whose rise time is slow for the input signal is used as a circuit for generating this processed signal. For example, as shown in FIG. 3, transmission data (see FIG. 3 (a)) is transferred to the above circuit. To a single constant signal (see FIG. 3 (b)) and then waveform shaping by a logic circuit to generate a processed signal as shown in FIG. 3 (c).

[0003]

However, since the signal generating circuit described above generates a signal by using the time constants of the capacitor and the resistor, the generated signal waveform (see FIG. 3).
(see (c)) has a problem that the range of variation in the rise time and the fall time becomes large due to the influence of the variation of the time constant and the temperature change.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a data processing signal generation circuit in which the deviation of the rising time and the falling time of the processing signal is small.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and in a data processing signal generation circuit for generating a processing signal for processing transmission data, the transmission data is applied to the data processing signal generation circuit. First signal generating means for generating an output signal, and second signal generating means for triggering the predetermined signal of the transmission data in response to the output signal from the first signal generating means to generate the processed signal. And the second
The clearing state is released according to the processed signal from the signal generating means and the transmission data, a constant clock is counted, and when the count value reaches a predetermined value, the counting means clears the first and second signal generating means. A data processing signal generation circuit comprising:

[0006]

The first signal generating means generates the output signal indicating that the transmission data is detected, and the second signal generating means generates the processed signal from the pulse edge of the second signal of the transmission data, for example. Start generation. Since the clearing period of the counting means, which is made by the processed signal from the second signal generating means and the transmission data, is the period in which the transmission data exists, the counting means, after the transmission data disappears,
The first and second signal generating means are cleared to end the generation of the processed signal.

Therefore, if the output of the processed signal is the output of the second signal generating means, the processed signal can be output during the input period of the transmission data.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to the drawings of FIGS. FIG. 1 is a diagram showing a data processing signal generation circuit according to the present invention using the Manchester method. In the figure, the first flip-flop 11 has transmission data TD
Is used as a trigger input, and the signal c is output from the output terminal Q to the input terminal D of the second flip-flop 12.

The second flip-flop 12 outputs the output signal c from the first flip-flop 11 to the AND circuit 13 from the output terminal Q by using the transmission data TD input to the input terminal S as a trigger. The output signal RD from the output terminal Q is a processing signal which indicates the input period of the transmission data TD and serves as a reference for processing the transmission data, and the second flip-flop 12 of the present embodiment is the first flip-flop 12. With respect to the output signal c of the flip-flop 11, the output of the processing signal is started in response to the pulse edge of the second signal from the beginning of the transmission data. The output start timing of the processed signal is not limited to the pulse edge of the second signal of the transmission data, but can be set arbitrarily.

The AND circuit 13 receives the transmission data TD in addition to the output signal RD from the second flip-flop 12.
, And the AND circuit 13 outputs the clear cancellation signal e to the counter circuit 14 when both signals are at the high level. The output of the AND circuit 13 is in a low level state when there is no transmission data, and is in a high level state when there is high level transmission data.

The counter circuit 14 is in the state where the count is cleared when the output of the AND circuit 13 is in the low level state, and is cleared when the output of the AND circuit 13 is in the high level state. The clock signal a is taken in, counting is started, and a high-level output signal f is output to the first and second flip-flops 11 and 12 via the knot circuit 15 after, for example, t ₄ hours, and the flip-flops 11 and 12 are output. To clear.

Next, the operation of the data processing signal generation circuit will be described with reference to the drawing of FIG. FIG. 2 is a waveform diagram of each part when the transmission data (see FIG. 2B) is input. The leading bit of the transmission data is, for example, a synchronization bit, and the high level state of the tail bit is a special one indicating the end of the transmission data.

First, when the transmission data TD is input, the first flip-flop 11 outputs the output signal c having the waveform shown in FIG. 2 (c) to the second flip-flop 12, which then , When the transmission data TD is input, the processing signal RD is started from the pulse edge in the signal next to the first signal (for synchronization) of the transmission data (see FIG. 2 (d)).
Is output to the AND circuit 13.

When the processed signal RD is input, the AND circuit 1
The output of 3 becomes a signal e having a waveform as shown in FIG. 2 (e). When the signal e is at high level, the counter circuit 14
Is cleared, fetches the clock a from the outside, starts counting, and outputs the high level output signal f (see FIG. 2 (f)) through the knot circuit 15 after t ₄ hours.
And to the second flip-flop 12. When the output signal f is input, the second flip-flop 12 is cleared and the output signal RD can be set to the low level. Further, when the transmission data TD or the processing signal RD is not input or is in the low level state, the output signal e of the AND circuit 13 becomes the low level, and the counter circuit 14 is cleared by the output signal e. Maintained.

Further, when a single pulse signal due to noise is input instead of the transmission data, the output terminal Q of the second flip-flop 12 maintains the low level state, so that the processing signal RD is not output. It is possible to prevent the generation of the processing signal by the single pulse signal. Therefore, in this embodiment, the output of the processed signal is output to the second flip-flop 1
If the output is set to 2, the generation and stop time of the processed signal is determined by the delay time of the logic circuit such as the flip-flop and the counter, and when the transmission data of the Manchester system is no longer present, the processed signal is set to the predetermined value. Since it can be set to the low level after a certain period of time, the processed signal is not kept in the high level for a long period of time, and the time lag is small and stable, so that the processed signal can be output according to the input period of the transmission data. it can. Also, the second
Since the flip-flop 12 starts outputting the processed signal from the second pulse edge from the beginning of the transmission data, the output of the processed signal can be prevented when a single pulse signal due to noise or the like is input.

[0016]

As described above, according to the present invention, in the data processing signal generating circuit for generating the processing signal for processing the transmission data, the first signal for generating the output signal in response to the application of the transmission data is provided. A second signal generating means, and a second signal for generating the processed signal by triggering the predetermined signal of the transmission data according to the output signal from the first signal generating means.
Of the signal generating means and the processing signal and the transmission data from the second signal generating means, the clear state is released, a constant clock is counted, and when the count value reaches a predetermined value, the first and second Since the counting means for clearing the signal generating means is provided, if the output of the processed signal is the output of the second signal generating means, it is possible to reduce the deviation between the rising time and the falling time of the processed signal.

[Brief description of drawings]

FIG. 1 is a diagram showing a data processing signal generation circuit according to the present invention using a Manchester system.

FIG. 2 is a waveform diagram in each part of the data processing signal generation circuit shown in FIG. 1 when transmission data is input.

FIG. 3 is a waveform diagram in a conventional example when transmission data is input.

[Explanation of symbols]

 11, 12 Flip-flop 13 AND circuit 14 Counter circuit 15 Not circuit TD Transmission data RD Processing signal

Claims (1)

Claim: What is claimed is: 1. A data processing signal generation circuit for generating a processing signal for processing transmission data, comprising: first signal generation means for generating an output signal in response to the application of the transmission data. A second signal generating means for generating the processing signal by triggering the predetermined signal of the transmission data according to the output signal from the first signal generating means, and the processing from the second signal generating means The clear data is released according to the signal and the transmission data, counts a fixed clock, and counts means for clearing the first and second signal generating means when the count value reaches a predetermined value. A data processing signal generation circuit, which generates the processing signal indicating the input period of.