JPH05343590A - Lead frame for semiconductor device - Google Patents

Abstract

PURPOSE:To form a sheath-plating also on an end of a lead and to effectively connect a semiconductor device to a circuit board by providing at least one through sheath-plating hole for forming a sheath-plating layer at a position to become an end of an outer lead of the device. CONSTITUTION:A lead frame for a semiconductor device has a plurality of leads 3 on a periphery of a semiconductor device placing part 1 and a pilot hole 7 at a frame 4 outside the leads 3, and comprises a sheath-plating hole 2 for sheath-plating at a position to become an end of the lead of the device at a center of the lead 3. When a sheath-plating layer 8 sheath-plated after rein-sealing is formed by using the frame for the device, the layers 8 are simultaneously formed also on a front surface, a rear surface, side faces and a periphery of the hole 2. Thus, a soldered region is increased, connection of the device to the board is effectively performed, and an inspection is facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device lead frame.

[0002]

2. Description of the Related Art Conventional lead frames for semiconductor devices are
As shown in FIG. 4, a plurality of leads 3, one or a plurality of semiconductor element mounting portions 1, a frame frame 4 outside the leads 3 and a pilot hole 7 provided in the frame frame 4 are provided. The shape of 3 was flat and parallel.

Further, as shown in FIG. 5, there has been a structure having a gap 9 between the frame 4 and the lead 3.

[0004]

In recent years, electrolytic plating has been the mainstream of the exterior plating treatment for the leads of semiconductor devices, and it is necessary to electrically connect the leads of the semiconductor device and the frame to the leads after the exterior plating treatment. It is a process of cutting to a specified length. In addition, the surface mounting type is the mainstream for actually mounting a semiconductor device on a circuit board. Furthermore, due to the trend of lighter, thinner, shorter, finer pitch between leads and shorter leads, the connecting portion between the lead of the semiconductor device and the circuit board is extremely small, and only the area of about 0.2 × 0.4 mm is left. It is difficult to connect the device leads to the circuit board.

However, in the above-mentioned conventional lead frame for a semiconductor device, since the leads are flat and parallel, when the leads are cut to a specified length, the cut surface of the tips of the leads is not subjected to exterior plating treatment. , The lead was exposed. Therefore, when a semiconductor device is mounted on a circuit board and solder connection is performed, solder does not attach to the tip portions of the leads, resulting in a defect that the connection area is small and electrical conduction cannot be reliably obtained. was there.

Further, as a method of inspecting the connection state between the leads of the semiconductor device and the circuit board, it is judged by the solder rising state on the side surface of the leads, but the inspection is impossible due to the miniaturization of the lead pitch. It has come to be judged by the rising state of the solder at the tip of the. However, the conventional lead frame for a semiconductor device has a problem in that the cut surface of the lead tip portion of the semiconductor device is not externally plated, so that the solder does not rise and is erroneously inspected.

Further, as shown in FIG. 5, in the conventional lead frame for a semiconductor device, since a gap is provided between the lead and the frame, it is possible to apply exterior plating to the lead tip. However, since the tips of the leads are not supported by the frame frame, there is a problem in that the strength of the leads is low and lead bending defects occur in the present semiconductor devices with a fine lead pitch.

An object of the present invention is to provide a lead frame for a semiconductor device, in which electrical continuity is surely obtained when the semiconductor device is soldered and connected to a circuit board, a connection state is surely checked, and a lead bending defect does not occur. To provide.

[0009]

According to the present invention, there is provided a lead frame for a semiconductor device, which comprises (1) at least one penetrating exterior plating for forming an exterior plating layer at a position which becomes a tip of an external lead of the semiconductor device. Has a hole.

(2) The semiconductor device has a notch for forming an exterior plating layer at a position which becomes a tip of an external lead.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIGS. 1A and 1B are a plan view of a first embodiment of the present invention and a partially enlarged plan view of a lead portion thereof.

In the first embodiment, as shown in FIGS. 1A and 1B, a plurality of leads 3 are provided around the semiconductor element mounting portion 1.
And a pilot hole 7 is provided in the frame frame 4 outside the lead 3 in the lead frame for a semiconductor device,
An outer plating hole 2 for performing outer plating is provided at a position at the center of the lead 3 which is the tip of the lead of the semiconductor device.

FIG. 2 is a perspective view of the lead shown in FIGS. 1 (a) and 1 (b), which is obtained by applying exterior plating to the exterior plating hole and cutting the tip.

Using the lead frame for a semiconductor device shown in FIGS. 1A and 1B, outer layer plating is applied after resin sealing to form an outer layer plating layer 8.

As shown in FIG. 2, the outer plating layer 8 is also applied to the front surface, the back surface, the side surface of the lead 3 and the circumferential surface of the outer plating hole 2.

The size of the outer plating hole 2 is best set to the maximum diameter up to about 0.02 mm in thickness with the side surface of the lead 3. Also, the same effect can be obtained when the shape of the exterior plating hole 2 is square or rectangular.

FIGS. 3 (a) and 3 (b) are a plan view of a second embodiment of the present invention and a partially enlarged plan view of its lead portion.

In the second embodiment, as shown in FIGS. 3 (a) and 3 (b), the outer plating hole in the central portion of the lead 3 of the first embodiment shown in FIGS. 1 (a) and 1 (b). A notch 6 is provided instead of 2.

Also in the second embodiment, the same effect as in the first embodiment can be obtained.

[0021]

As described above, according to the present invention, in the lead frame for a semiconductor device, by providing a penetrating outer plating hole for performing outer plating in the central portion of the position of the tip of the lead of the semiconductor device, Since the outer ends of the leads are also subjected to exterior plating, the soldering area of about 20% of the soldering area between the leads of the semiconductor device and the circuit board in the conventional lead frame for a semiconductor device is expanded. . Therefore, there is an effect that the connection of the semiconductor device to the circuit board becomes reliable.

Also, in the inspection of the connection state between the leads of the semiconductor device and the circuit board, the lead tips are externally plated, so that the lead tips are also soldered.
The effect is that inspection can be performed easily.

[Brief description of drawings]

FIG. 1 is a plan view of a first embodiment of the present invention and an enlarged plan view of a lead portion thereof.

FIG. 2 is a perspective view of a lead obtained by applying exterior plating to the exterior plating hole of FIG. 1 and cutting the tip portion.

FIG. 3 is a plan view of a second embodiment of the present invention and a partially enlarged plan view of a lead portion thereof.

FIG. 4 is a plan view of an example of a conventional semiconductor device lead frame.

FIG. 5 is a plan view of another example of a conventional lead frame for a semiconductor device.

[Explanation of symbols]

 1 Semiconductor device mounting part 2 Exterior plating hole 3 Lead 4 Frame frame 5 Tie bar 6 Notch 7 Pilot hole 8 Exterior plating layer 9 Gap

Claims (2)

[Claims] 1. A lead frame for a semiconductor device, which has at least one penetrating outer plating hole for forming an outer plating layer at a position which becomes a tip of an external lead of the semiconductor device. 2. A lead frame for a semiconductor device, which has a notch for forming an exterior plating layer at a position which becomes a tip of an external lead of the semiconductor device.