JPH05343581A - Manufacture of lead frame - Google Patents
Manufacture of lead frameInfo
- Publication number
- JPH05343581A JPH05343581A JP3134411A JP13441191A JPH05343581A JP H05343581 A JPH05343581 A JP H05343581A JP 3134411 A JP3134411 A JP 3134411A JP 13441191 A JP13441191 A JP 13441191A JP H05343581 A JPH05343581 A JP H05343581A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- plate
- line
- conductive plate
- main line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4009—Loop shape
- H01L2224/40095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、リードフレーム製造装
置に係り、特に積層構造のリードフレームの製造装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame manufacturing apparatus, and more particularly to a laminated frame lead frame manufacturing apparatus.
【０００２】[0002]
【従来の技術】パワートランジスタ等のパワーデバイス
を集積化してなる半導体集積回路の分野では、高いパワ
ーを用いるため、電流供給のためのリードは、ワイヤと
の接続部におけるインダクタンスの増大を防ぐために、
ボンディングワイヤに代えてパワープレートを介してチ
ップのボンディングパッドに接続するという方法が取ら
れることが多い。また、高集積化に従い、リードの本数
を低減する目的から、複数のパッドから接地ラインに落
とすような場合、接地用のプレートを設けこれにすべて
接続するという方法が有力となってきている。2. Description of the Related Art In the field of semiconductor integrated circuits in which power devices such as power transistors are integrated, high power is used. Therefore, the leads for supplying the current have the following advantages:
A method of connecting to the bonding pad of the chip via a power plate instead of the bonding wire is often adopted. In order to reduce the number of leads in accordance with high integration, a method of providing a grounding plate and connecting all of them to the grounding line has become effective in the case of dropping from a plurality of pads to the grounding line.
【０００３】さらにまた、発熱量も大きいため、ダイパ
ッドに代えて放熱性の良好な金属板からなる大きな放熱
板を必要とする傾向にある。Further, since the amount of heat generated is large, there is a tendency that a large heat dissipation plate made of a metal plate having good heat dissipation is required instead of the die pad.
【０００４】このようなパワーデバイスでは、一例を図
９に示すように、通常、接地用のグランドプレート１２
とパワープレート１４とがリードフレーム本体１５に対
して各々所定の部位に設けられた舌片を介して溶接によ
り一体的に接続されリードフレームを構成している。In such a power device, as shown in FIG. 9, an example is shown in FIG.
The power plate 14 and the power plate 14 are integrally connected to the lead frame main body 15 by welding via tongues provided at predetermined portions to form a lead frame.
【０００５】このようなリードフレームの製造に際して
は、従来リードフレーム本体の形状加工を行う装置と、
グランドプレ−トの形状加工を行う装置とパワープレー
トの形状加工を行う装置とがそれぞれ別々に設置されて
おり、搬送工程が複雑であると共に、各部の製造時期が
別々であるため、待ち時間が長く製造に時間がかかる等
の問題があった。In manufacturing such a lead frame, a conventional device for shaping the lead frame body,
Since the equipment that processes the shape of the ground plate and the equipment that processes the shape of the power plate are installed separately, the transportation process is complicated and the manufacturing time of each part is different, so the waiting time There were problems such as long manufacturing time.
【０００６】[0006]
【発明が解決しようとする問題点】このように、従来の
パワーデバイスでは、接地用のグランドプレートやパワ
ープレート等とリードフレーム本体とが別々に形成さ
れ、搬送に時間がかかったり、各部の製造タイミングが
ずれ、そのために製造に時間がかかるという問題があっ
た。As described above, in the conventional power device, the ground plate for grounding, the power plate, etc. and the main body of the lead frame are separately formed, and it takes a long time to carry them, and the manufacturing of each part. There is a problem that the timing is deviated, and therefore it takes time to manufacture.
【０００７】本発明は、前記実情に鑑みてなされたもの
で、製造が容易でかつ短時間で多層リードフレームを製
造することのできるリードフレーム製造装置を提供する
ことを目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a lead frame manufacturing apparatus which is easy to manufacture and can manufacture a multilayer lead frame in a short time.
【０００８】[0008]
【課題を解決するための手段】そこで、本発明では、帯
状材料から形状加工を行い、めっき処理などの処理工程
を経てリードフレーム本体を形成するリードフレーム本
体形成手段とリードフレーム本体に導電性プレートを積
層加工する組み立て手段とを具備した主ラインに対し、
この主ラインと並行して導電性プレートの形状加工を行
う補助ラインから、主ライン上の組み立て手段に導電性
プレートを供給するように構成され、リードフレーム本
体に絶縁層を介して導電性プレートを積層し、積層構造
のリードフレームを製造するようにしている。In view of the above, according to the present invention, a lead frame body forming means for forming a lead frame body through a processing step such as a plating process, which is performed from a band-shaped material, and a conductive plate on the lead frame body. For the main line equipped with assembling means for laminating
It is configured to supply the conductive plate to the assembling means on the main line from the auxiliary line that shapes the conductive plate in parallel with the main line, and the conductive plate is connected to the lead frame body via the insulating layer. The layers are laminated so that a lead frame having a laminated structure is manufactured.
【０００９】望ましくは、主ラインを一連の順送り金型
装置で構成し、補助ラインが主ラインの順送り金型装置
の組み立て手段で直交するように構成し、主ラインの製
造タイミングに補助ラインの製造タイミングを対応させ
るようにする。Desirably, the main line is composed of a series of progressive die units, and the auxiliary line is constructed so that it is orthogonal to the assembly means of the progressive die unit of the main line, and the auxiliary line is manufactured at the timing of manufacturing the main line. Try to match the timing.
【００１０】[0010]
【作用】上記構成により、リードフレーム本体の形状加
工を行う装置と、グランドプレ−トの形状加工を行う装
置とパワープレートの形状加工を行う装置とが一体的に
形成されているため、搬送が容易となりまた、各部の製
造タイミングを合わせるようにすることができ、待ち時
間が皆無となり製造時間を大幅に短縮化することができ
る。With the above structure, the apparatus for shaping the lead frame body, the apparatus for shaping the ground plate, and the apparatus for shaping the power plate are integrally formed. Further, the manufacturing timing of each part can be adjusted, and no waiting time is required, and the manufacturing time can be greatly shortened.
【００１１】[0011]
【実施例】以下本発明の実施例について、図面を参照し
つつ詳細に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.
【００１２】図１乃至図５は、本発明実施例のリードフ
レームの製造装置の概要説明図、フローチャート図、概
要説明図、一部拡大説明図、この製造装置で形成される
リードフレームおよびその製造工程を示す図である。1 to 5 are schematic explanatory views, a flow chart, a schematic explanatory view, a partially enlarged explanatory view of a lead frame manufacturing apparatus according to an embodiment of the present invention, a lead frame formed by this manufacturing apparatus, and its manufacturing. It is a figure which shows a process.
【００１３】この装置は、多数のリードを有するリード
フレーム本体にグランドプレートとしての第１の導電板
２と接地プレートとしての第２の導電板４とを積層して
構成した多層リードフレームを形成するための装置であ
る。This device forms a multi-layer lead frame in which a first conductive plate 2 as a ground plate and a second conductive plate 4 as a ground plate are laminated on a lead frame body having a large number of leads. It is a device for.
【００１４】ここで形成される多層リードフレームは、
リードフレーム本体５のインナーリード先端部には凹部
Ｕが形成されており、この凹部Ｕ内に、第１または第２
の導電板２，４の対応する領域に設けられた舌片の先端
に設けられた凸部Ｔを嵌挿することにより接続を達成し
ている。The multilayer lead frame formed here is
A recess U is formed at the tip of the inner lead of the lead frame body 5, and the first or second recess is formed in the recess U.
The connection is achieved by inserting and inserting the convex portion T provided at the tip of the tongue provided in the corresponding area of the conductive plates 2 and 4.
【００１５】このリードフレーム製造装置は、図１(a)
に示すように、帯状材料の打ち抜きを行い、リードフレ
ーム本体を形成し図１(b) に示すようにテープ貼着補助
ライン（テープ供給ライン）４０を用いてテーピング処
理などを行った後、インナーリード先端の連結片の除去
等（図１(c) ）を行って、積層組立てを行う順送り金型
からなる主ライン（図１(d) 〜図１(f) ）１０と、半導
体チップ１を載置すると共にグランドプレートとしての
役割を担う第１の導電板２を形成する第１の補助ライン
２０と、電源ラインに接続されるパワープレートとして
の第２の導電板４を形成する第２の補助ライン３０とか
ら構成されており、これら主ライン１０と第１および第
２の補助ライン２０，３０とが直交するように一体的に
構成されている。なお、第１の補助ラインの上流には、
テーピングを行うためのテープ貼着補助ライン４０が設
置されている。（図２のフローチャート図参照）図３は
この装置の概要を示す図である。This lead frame manufacturing apparatus is shown in FIG.
As shown in Fig. 1, the band-shaped material is punched out to form the lead frame body, and taping treatment is performed using the tape sticking auxiliary line (tape supply line) 40 as shown in Fig. 1 (b). The semiconductor chip 1 and the main line (FIG. 1 (d) to FIG. 1 (f)) 10 composed of a progressive die for stacking and assembling are performed by removing the connecting piece at the tip of the lead (FIG. 1 (c)). A first auxiliary line 20 that forms a first conductive plate 2 that is placed and that also serves as a ground plate, and a second auxiliary plate 4 that forms a second conductive plate 4 that is connected to a power supply line. The auxiliary line 30 and the main line 10 and the first and second auxiliary lines 20 and 30 are integrally formed so as to be orthogonal to each other. In addition, upstream of the first auxiliary line,
A tape sticking auxiliary line 40 for taping is installed. (Refer to the flowchart of FIG. 2) FIG. 3 is a diagram showing an outline of this apparatus.
【００１６】図４(a) および図４(b) は、それぞれ第１
および第２の補助ラインを示す拡大図である。4 (a) and 4 (b) respectively show the first
It is an enlarged view showing a second auxiliary line.
【００１７】この装置で製造されるリードフレームは、
図５に示すように、半導体チップ１を載置すると共にグ
ランドプレートとしての役割を担う第１の導電板２と、
この上層に接着剤３を介して固着され、電源ラインに接
続されるパワープレートとしての第２の導電板４と、さ
らにこの上層に接着剤３を介して固着され、前記第１の
導電板２の半導体チップ搭載部を囲むように複数のイン
ナーリードを配設してなるリードフレーム本体５とから
構成されてなるものである。The lead frame manufactured by this apparatus is
As shown in FIG. 5, a first conductive plate 2 on which the semiconductor chip 1 is placed and which plays a role of a ground plate,
A second conductive plate 4 as a power plate, which is fixed to the upper layer via an adhesive 3 and is connected to a power supply line, and further, is fixed to the upper layer via an adhesive 3 on the first conductive plate 2 And a lead frame main body 5 in which a plurality of inner leads are arranged so as to surround the semiconductor chip mounting portion.
【００１８】次にこのリードフレーム製造装置を用いた
リードフレームの製造工程を図２に示すように、フロー
チャートを用いて説明する。Next, a lead frame manufacturing process using this lead frame manufacturing apparatus will be described with reference to a flow chart as shown in FIG.
【００１９】まず、あらかじめ所定の領域に部分めっき
のなされた帯状材料を用い、通常のスタンピング法によ
り、帯状材料を加工し、半導体チップ載置領域ａと対峙
するインナ−リ−ド６、アウターリード７、タイバー８
などを含む通常のリードフレ−ムの側縁の打ち抜きを行
う。９はサイドバーである。次いで、インナーリードの
うちの所定のものの中央からややアウターリードよりに
貫通孔Ｈを開けると共にコイニング処理を行い、インナ
−リ−ド先端部の平坦幅を確保する（第１のプレスステ
ップ１０１）。First, a band-shaped material, which has been partially plated in a predetermined region in advance, is used to process the band-shaped material by a normal stamping method, and the inner lead 6 and the outer lead 6 facing the semiconductor chip mounting region a are formed. 7, tie bar 8
The side edge of a normal lead frame including the above is punched. 9 is a sidebar. Next, a through hole H is formed from the center of a predetermined one of the inner leads to a position slightly closer to the outer leads, and coining is performed to secure a flat width of the inner lead tip (first pressing step 101).
【００２０】この後、インナ−リ−ド先端部のボンディ
ングエリアを避けるように絶縁性テープを貼着してイン
ナーリード相互間を連結固定する。（ステップ１０
２）。After that, an insulating tape is attached so as to avoid the bonding area at the tip of the inner lead, and the inner leads are connected and fixed to each other. (Step 10
2).
【００２１】そしてさらにキャビテイ領域の打ち抜きを
行いインナーリード先端を形成し、図６(a) に示すよう
にリードフレーム本体を形成する（第２のプレスステッ
プ１０３）。Then, the cavity region is punched out to form the inner lead tips, and the lead frame body is formed as shown in FIG. 6 (a) (second pressing step 103).
【００２２】一方、上記主ラインの工程と並行して図６
(b) および図６(c) に示すように、また通常のスタンピ
ング法により、放熱性の良好な銅板を加工し、グランド
プレートとしての役割を行う第１の導電板２（ステップ
２０１）と、電源ラインに接続されるパワープレートと
しての第２の導電板４（ステップ３０１）とを形成す
る。これらの第１および第２の導電板２，４に対して
は、舌片４Ｔを有するように打ち抜きを行った後、表面
を絶縁性のポリイミド膜１１で被覆すると共に、舌片４
Ｔの先端位置にポリイミド膜１１を貫通するように導電
性の突起Ｄを形成する。また第２の導電板４については
前述した成型加工ステップ３０１の後テープ貼着工程
（ステップ３０２）および、チップ載置用の空間形成の
ためのプレス工程（ステップ３０３）を経て主ラインに
供給される。図４(a) および図４(b) は第１および第２
の補助ラインを示す説明図である。On the other hand, as shown in FIG.
As shown in (b) and FIG. 6 (c), and also by a normal stamping method, a first conductive plate 2 (step 201) that functions as a ground plate by processing a copper plate with good heat dissipation, The second conductive plate 4 (step 301) as a power plate connected to the power supply line is formed. The first and second conductive plates 2 and 4 are punched out so as to have the tongue piece 4T, and then the surface is covered with the insulating polyimide film 11 and the tongue piece 4T is formed.
A conductive protrusion D is formed at the tip of T so as to penetrate the polyimide film 11. The second conductive plate 4 is supplied to the main line through the tape attaching step (step 302) after the molding step 301 and the pressing step (step 303) for forming a space for mounting a chip. It 4 (a) and 4 (b) show the first and second
It is explanatory drawing which shows the auxiliary line.
【００２３】そして、図６(d) に示すように、第１の導
電板２の中央部に半導体チップ１を接着剤を介して固着
すると共に、第１の導電板、第２の導電板、リードフレ
ーム本体５を順次積層し、前記第１および第２の導電板
の舌片の突起Ｄを、リードフレーム本体５のインナーリ
ードの中央よりややアウターリードよりに設けられた凹
部Ｕに嵌合させることによって順次一体的に固着する
（ステップ１０４，１０５，１０６）。Then, as shown in FIG. 6 (d), the semiconductor chip 1 is fixed to the central portion of the first conductive plate 2 with an adhesive, and the first conductive plate, the second conductive plate, The lead frame main body 5 is sequentially laminated, and the projection D of the tongue piece of the first and second conductive plates is fitted into the recess U provided slightly closer to the center of the inner lead of the lead frame main body 5 than the outer lead. By doing so, they are sequentially and integrally fixed (steps 104, 105, 106).
【００２４】この後、カット工程および応力除去のため
の熱処理工程（ステップ１０７）を経て、リードフレー
ムが完成する。Then, a lead frame is completed through a cutting process and a heat treatment process (step 107) for removing stress.
【００２５】このようにして極めて容易にかつ短時間で
多層構造のリードフレームを形成することができる。In this way, a lead frame having a multilayer structure can be formed extremely easily and in a short time.
【００２６】またこのようにして形成されたリードフレ
ームは、リードと導電性プレートとがインナーリード先
端に形成された貫通孔に導電性プレートの突起を嵌挿す
ることによって接続されているため、歪みや剥がれもな
く、高精度の接続を確実に行うことが可能となる。Further, in the lead frame thus formed, the lead and the conductive plate are connected by inserting the projection of the conductive plate into the through hole formed at the tip of the inner lead. It does not come off or peel off, and it is possible to make a highly accurate connection reliably.
【００２７】なお前記実施例では、パワープレートや接
地プレートは、一枚の導電性の板状体で構成したが、フ
ィルムキャリア等の絶縁性基板上に所望のパターンを形
成することによって行っても良い。このとき信号線およ
びグランド線のパターンは、スパッタリングおよび電解
めっきによって形成された銅薄膜をフォトリソ法により
パターニングして形成する方法、樹脂フィルム表面に表
面処理を行った後、薄い銅箔を直接圧着したり、接着剤
を介して固着したりして銅薄膜を形成した後パターニン
グしたりまた、薄い銅箔の表面にポリイミド樹脂等の絶
縁性樹脂を塗布しこれを硬化することによって銅薄膜を
形成した後、同様にフォトリソ法によりパターニングす
るなどの方法をとることも可能である。In the above embodiment, the power plate and the ground plate are made of one conductive plate, but they may be formed by forming a desired pattern on an insulating substrate such as a film carrier. good. At this time, the pattern of the signal line and the ground line is formed by patterning a copper thin film formed by sputtering and electroplating by photolithography, after performing a surface treatment on the resin film surface, and directly bonding a thin copper foil by pressure bonding. Alternatively, the copper thin film is formed by forming a copper thin film by adhering it via an adhesive or by patterning it, or by applying an insulating resin such as a polyimide resin to the surface of a thin copper foil and curing it to form a copper thin film. After that, it is also possible to adopt a method such as patterning by a photolithography method.
【００２８】また、前記実施例では、第２の補助ライン
３０で形成したパワープレートと第１の補助ライン２０
で形成したグランドプレートとを順次主ライン上に供給
するようにしたが、変形例として、図７に示すように第
２の補助ライン３０で形成したパワープレートと第１の
補助ライン２０で形成したグランドプレートとを積層
し、これを主ライン１０上に供給するようにしてもよ
い。Further, in the above embodiment, the power plate formed by the second auxiliary line 30 and the first auxiliary line 20.
Although the ground plate formed in 1) is sequentially supplied onto the main line, as a modification, the power plate formed by the second auxiliary line 30 and the first auxiliary line 20 are formed as shown in FIG. It is also possible to stack a ground plate and supply this to the main line 10.
【００２９】また、前記実施例では、インナーリード先
端に凹部を形成したが貫通孔でもよい。さらにリードフ
レーム本体と各プレートとの間の接続は実施例に限定さ
れることなく、図８(a) および(b) に示すように、ワイ
ヤ接続を行うようにしたものあるいは溶接接続を行うよ
うにしたものにも適用可能である。Further, in the above embodiment, the concave portion is formed at the tip of the inner lead, but it may be a through hole. Further, the connection between the lead frame body and each plate is not limited to the embodiment, and as shown in FIGS. 8 (a) and 8 (b), wire connection or welding connection may be performed. It can also be applied to the above.
【００３０】さらにまた、複数のインナーリードと、こ
れら複数のインナーリードのそれぞれに対応して外方に
突出する舌片からなるアウターリ−ドとを配設してなる
樹脂フィルムからなり、表面および裏面の導体層が前記
樹脂フィルムに形成されたスルーホールを介して接続さ
れていると共に、該舌片を集積回路チップのボンディン
グパッドに直接接続するように構成されたいわゆるＴＡ
Ｂ技術を用いたフィルムキャリアにも適用可能である。Furthermore, the front surface and the back surface are made of a resin film in which a plurality of inner leads and an outer lead made of a tongue protruding outward corresponding to each of the plurality of inner leads are arranged. Of the so-called TA, which is connected to the bonding pad of the integrated circuit chip while the conductor layer is connected through a through hole formed in the resin film.
It is also applicable to a film carrier using the B technology.
【００３１】[0031]
【発明の効果】以上説明してきたように、本発明によれ
ば、リードフレーム本体の形状加工を行う装置と、グラ
ンドプレ−トの形状加工を行う装置とパワープレートの
形状加工を行う装置とが一体的に形成されているため、
製造が容易となりまた、製造時間を大幅に短縮化するこ
とができる。As described above, according to the present invention, there are provided a device for shaping the lead frame body, a device for shaping the ground plate, and a device for shaping the power plate. Because it is integrally formed,
Manufacturing is facilitated and manufacturing time can be significantly shortened.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明実施例のリードフレームの製造装置の説
明図FIG. 1 is an explanatory view of a lead frame manufacturing apparatus according to an embodiment of the present invention.
【図２】同装置を用いたリードフレーム製造工程のフロ
ーチャート図FIG. 2 is a flowchart of a lead frame manufacturing process using the same device.
【図３】同概要説明図FIG. 3 is a schematic explanatory diagram of the same.
【図４】要部拡大説明図FIG. 4 is an enlarged explanatory view of a main part.
【図５】同製造装置で形成されるリードフレームを示す
図FIG. 5 is a view showing a lead frame formed by the manufacturing apparatus.
【図６】同製造工程図FIG. 6 is a manufacturing process diagram of the same.
【図７】本発明の装置の変形例を示す図FIG. 7 is a diagram showing a modification of the device of the present invention.
【図８】本発明の方法で形成されるリードフレームの他
の例を示す図FIG. 8 is a view showing another example of the lead frame formed by the method of the present invention.
【図９】通常の積層構造のリードフレームFIG. 9 is a lead frame having a normal laminated structure.
１ 半導体チップ ２ 第１の導電板 ３ 接着剤 ４ 第２の導電板 ５ リードフレーム本体 Ｐ 封止樹脂 ａ 半導体チップ載置領域 ６ インナ−リ−ド ７ アウターリード ８ タイバー ９ サイドバー Ｕ 凹部 Ｔ 舌片 １１ポリイミド膜 ｓ 絶縁膜 Ｄ 突起。 １０ 主ライン ２０ 第１の補助ライン ３０ 第２の補助ライン ４０ テープ貼着補助ライン 1 Semiconductor Chip 2 First Conductive Plate 3 Adhesive 4 Second Conductive Plate 5 Lead Frame Main Body P Sealing Resin a Semiconductor Chip Mounting Area 6 Inner Lead 7 Outer Lead 8 Tie Bar 9 Side Bar U Recess T Tongue Piece 11 Polyimide film s Insulating film D Protrusion. 10 Main line 20 First auxiliary line 30 Second auxiliary line 40 Tape sticking auxiliary line
Claims (3)
程を経てリードフレーム本体を形成するリードフレーム
本体形成手段と、 リードフレーム本体に導電性プレートを積層加工する組
み立て手段とを具備した主ラインと、 前記主ラインと並行して導電性プレートの形状加工を行
う補助ラインと、 前記主ライン上の組み立て手段に前記補助ラインで形成
された導電性プレートを供給する供給手段とを具備し、 前記リードフレーム本体に絶縁層を介して導電性プレー
トを積層し積層構造のリードフレームを製造することを
特徴とするリードフレーム製造装置。1. A main line comprising a lead frame body forming means for forming a lead frame body through a shaping process and a treatment process such as a plating process, and an assembling means for laminating a conductive plate on the lead frame body. And an auxiliary line for forming the shape of the conductive plate in parallel with the main line, and a supply means for supplying the conductive plate formed by the auxiliary line to the assembly means on the main line, An apparatus for manufacturing a lead frame, wherein a conductive plate is laminated on a lead frame body via an insulating layer to manufacture a lead frame having a laminated structure.
加工装置で構成されており、 前記補助ラインは前記主ラインの製造タイミングに一致
するように構成されるとともに、前記順送り金型装置の
組み立て手段で直交するように構成されていることを特
徴とする請求項(1) 記載のリードフレーム製造装置。2. The main line is composed of a processing device provided with a series of progressive metal molds, and the auxiliary line is structured so as to coincide with the manufacturing timing of the main line, and the progressive metal mold device. The lead frame manufacturing apparatus according to claim 1, wherein the assembly means is configured to be orthogonal to each other.
段と、前記導電性プレートを積層接続する接続手段と、
接続部の内部残留応力を除去するキュア手段とを具備し
て構成されていることを特徴とする請求項(1) 記載のリ
ードフレーム製造装置。3. The processing device for the main line comprises a tape sticking means and a connecting means for connecting the conductive plates in layers.
The lead frame manufacturing apparatus according to claim 1, wherein the lead frame manufacturing apparatus is configured to include a curing unit that removes an internal residual stress in the connection portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3134411A JP2668461B2 (en) | 1991-06-05 | 1991-06-05 | Lead frame manufacturing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3134411A JP2668461B2 (en) | 1991-06-05 | 1991-06-05 | Lead frame manufacturing equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05343581A true JPH05343581A (en) | 1993-12-24 |
| JP2668461B2 JP2668461B2 (en) | 1997-10-27 |
Family
ID=15127759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3134411A Expired - Fee Related JP2668461B2 (en) | 1991-06-05 | 1991-06-05 | Lead frame manufacturing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2668461B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7208794B2 (en) | 2002-09-05 | 2007-04-24 | Infineon Technologies Ag | High-density NROM-FINFET |
-
1991
- 1991-06-05 JP JP3134411A patent/JP2668461B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7208794B2 (en) | 2002-09-05 | 2007-04-24 | Infineon Technologies Ag | High-density NROM-FINFET |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2668461B2 (en) | 1997-10-27 |
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