JPS6329414B2 - - Google Patents

Abstract

PURPOSE:To enable formation, assembling and inspecting of an integrated circuit automatically by forming indexing holes (slit holes) longitudinally of a long metallic substrate. CONSTITUTION:Indexing holes 2 or slit holes 3 are formed at predetermined interval longitudinally of a metallic substrate 1 made of aluminum. Sections 4 are indexed by the indexing holes 2 or the slit holes 3 where integrated circuits are formed.

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing integrated circuits in large quantities.

As conventional methods for manufacturing large quantities of semiconductor devices, there are known a punching metal frame method as disclosed in Japanese Patent Publication No. 45-1137 and a film carrier method as disclosed in Japanese Patent Publication No. 47-3206. However, these methods are only applicable to monolithic integrated circuits with low power consumption, and because each lead piece must be self-supporting, they cannot be made thinner than a certain point and are not suitable for large-scale integrated circuits with a large number of pins. It is not suitable.

The present invention has been made in view of this point, and is intended to realize a method for mass-producing integrated circuits that greatly improves the conventional drawbacks.One embodiment of the present invention will be described below with reference to FIGS. 1 to 4. details.

First, as shown in FIG. 1, a long plate-shaped metal substrate 1 is prepared, and index holes 2 or slit holes 3 are formed at regular intervals in the longitudinal direction of the substrate 1. The metal substrate 1 is made of aluminum with a thickness of 1 mm, and has a long plate size of, for example, 70 mm x 1000 mm. Either the index hole 2 or the slit hole 3 is formed, and if the integrated circuit to be completed is large, the first one is formed.
A slit hole 3 is used as shown in Figure B, and an index hole 2 is used as shown in Figure 1A for smaller holes. This index hole 2 or slit hole 3 is punched out with a press and used for position indexing by mechanical means in a later process. Therefore, the interval between the index holes 2 or the slit holes 3 is selected according to the size of the hybrid integrated circuit to be completed.More specifically, in FIG. 1A, the index holes 2 are provided at both widthwise ends of the substrate 1, A compartment 4 indexed by an index hole 2 is provided with two integrated circuits. 1st
In Figure B, each section 4 is divided by a long slit hole 3 in the width direction of the substrate 1, and one integrated circuit is formed in each section 4. As is clear from this, by standardizing the width of the substrate 1, integrated circuits of various sizes can be formed using the same size substrate 1.

Next, as shown in FIG. 2, conductive patterns 5 are formed in a large number of sections 4 . . . 4 on the substrate 1 indexed by the index holes 2 or slit holes 3. Section 4
One or more conductive patterns 5 can be formed therein, and different types of conductive patterns 5 can be formed within the same section 4 or in different sections 4.

The aforementioned substrate 1 has an aluminum oxide film (not shown) formed on its surface by well-known anodic oxidation, and further a conductive pattern 5 is formed on one main surface of the substrate 1 as shown in FIG. First, as shown in FIG. 4A, a conductive metal foil 6, such as a copper foil, is adhered. metal foil 6
The surface is masked with a resist 7 by exposing a desired conductive pattern 5 by screen printing, and a noble metal (gold, silver, platinum) plating layer 8 is plated on the surface of the metal foil 6 as shown in FIG. 4B. After that, the resist is removed and the metal foil 6 is applied using the noble metal plating layer 8 as a mask.
Then, desired conductive patterns 5...5 are formed as shown in FIG. 4C. The thinness of the conductive pattern 5 by screen printing is limited to 0.5 mm, so when ultra-fine wiring is required, the ultra-fine conductive pattern 5 up to about 2 μm can be formed using well-known photo-etching technology.
...5 is possible. Although the ultra-fine conductive pattern 5 could not be produced using conventional punched metal frames or film carriers, it is possible with the present invention and can be used in the assembly of large-scale integrated circuits with a large number of pins and in high-frequency circuits.

If multilayer wiring is required in this process, it can be realized by further forming an insulating layer such as polyimide on the formed conductive pattern 5, printing a conductive paint on it by screen printing, and baking.

Further, when circuit elements such as resistors are incorporated in this step, a resistive paint is printed on the metal substrate 1 using a well-known screen printing technique and then baked.

Subsequently, as shown in FIG. 4, a semiconductor element 9 such as a semiconductor integrated circuit is fixed onto a desired pad 51 of the conductive pattern 5 using a conductive paste.
The conductive pattern 5 adjacent to the conductive pattern 5 is connected to the corresponding electrode of the semiconductor element 9 by bonding with a thin gold or aluminum wire.

Then index hole 2 or slit hole 3
A circuit function test including the semiconductor element 9 and other circuit elements is performed by energizing the conductive pattern 5 to be measured while mechanically moving frame by frame using the . If a resistor or the like is incorporated in such an inspection, functional trimming is performed to adjust the circuit function, and if the semiconductor element 9 does not perform the specified circuit function, the semiconductor element 9 is removed and regenerated. This will greatly improve yield. Furthermore, if necessary, the adhesive strength of the bonding thin wire can also be measured.

That is, in this process, the circuit function test can be performed in a connected state before sealing, so measurement and trimming can be performed extremely efficiently, and defective products can be recycled, resulting in a significant improvement in yield.

Furthermore, after such inspection, silicone resin is applied to the semiconductor element 9 and circuit elements requiring protection to protect the elements and bonding thin wires. Moreover, such an element can be partially molded by transfer molding.

After the above steps, the completed multiple integrated circuits connected to the metal substrate 1 are separated from the metal substrate 1 as individual integrated circuits by a press. This press has index hole 2 or slit hole 3.
It is extremely efficient because the position can be determined mechanically according to the following. In this pressing, only the peripheral end of the male die is brought into contact with the substrate 1, so the elements on the substrate 1 are not affected.

After external leads are soldered to the individual integrated circuit, it is sealed with a resin case or sealed with epoxy resin dipping to complete the circuit.

According to the present invention, since the metal substrate 1 is used, the heat dissipation effect is large, and it becomes possible to incorporate the semiconductor element 9 for high breakdown voltage and large output. As a result, there is an advantage that twin transistors, dual transistors, transistor arrays, diode arrays, and Darlington connection cascade connections for high voltage and large output can be mass-produced. Also, combinations of monolithic integrated circuits such as operational amplifiers and power transistors, diodes, transistor monolithic integrated circuits, etc.
Another advantage is that combinations of LCR elements can be mass-produced in the same package. Furthermore, as described above, by using different types of conductive patterns, it is possible to efficiently produce a wide variety of products in small quantities. Furthermore, since it is possible to test circuit functions in a connected state, functional trimming and defect recovery can be performed, resulting in a yield of nearly 100%. Finally, by using index holes or slit holes, conventionally established automation techniques can be easily incorporated and extensive automation can be achieved.

[Brief explanation of drawings]

1 to 3 are top views illustrating the present invention,
FIG. 4 is a cross-sectional view illustrating the method of forming a conductive pattern according to the present invention. Explanation of the main figure numbers: 1 is a metal substrate, 2 is an index hole, 3 is a slit hole, 4...4 is a partition, 5 is a conductive pattern, and 9 is a semiconductor element.

Claims (1)

[Scope of Claims] 1. Index holes or slit holes are provided at intervals in a long plate-shaped metal substrate, and a number of sections defined by the index holes or slit holes are each insulated from the metal substrate. After forming conductive patterns, fixing at least a semiconductor element at a desired position on each conductive pattern, and connecting with each conductive pattern using a thin bonding wire, and performing a circuit function test including the semiconductor element, the metal substrate is A method for mass manufacturing integrated circuits, characterized by separating the integrated circuits into individual integrated circuits. 2. A method for mass-producing integrated circuits according to claim 1, characterized in that a plurality of conductive patterns are arranged within the section. 3. A method for mass-producing integrated circuits according to claim 1, characterized in that different types of conductive patterns are arranged in the sections. 4. A method for mass-producing integrated circuits according to claim 1, characterized in that the conductive pattern is made of ultra-fine wiring.