GB2026234A - Circuit element package having lead patterns - Google Patents

Circuit element package having lead patterns Download PDF

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Publication number
GB2026234A
GB2026234A GB7914818A GB7914818A GB2026234A GB 2026234 A GB2026234 A GB 2026234A GB 7914818 A GB7914818 A GB 7914818A GB 7914818 A GB7914818 A GB 7914818A GB 2026234 A GB2026234 A GB 2026234A
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GB
United Kingdom
Prior art keywords
circuit element
electric conductor
element package
concavity
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7914818A
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GB2026234B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsumi Electric Co Ltd
Original Assignee
Mitsumi Electric Co Ltd
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Publication date
Application filed by Mitsumi Electric Co Ltd filed Critical Mitsumi Electric Co Ltd
Publication of GB2026234A publication Critical patent/GB2026234A/en
Application granted granted Critical
Publication of GB2026234B publication Critical patent/GB2026234B/en
Expired legal-status Critical Current

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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/09181—Notches in edge pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10166—Transistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10477—Inverted
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

The invention relates to a package in which a circuit element chip (13) is accommodated within a concavity or depression (17) in a ceramic substrate (11) and is electrically connected to conductive layers (14, 15 and 16) printed on the upper surface of the substrate (11) and on the walls of the depression. The package is intended to be mounted onto a separate printed circuit board by electrically connecting the printed conductors on the ceramic substrate to the conductors on the printed circuit board. <IMAGE>

Description

SPECIFICATION Circuit element package having lead patterns The present invention relates generally to circuit element packages having lead patterns, and more particularly to a circuit element package wherein a specific circuit element is accommodated within a concavity formed in a ceramic substrate having a plurality of discrete electric conductor layers formed thereon in such manner that the circuit element is in electrical connection with the electric conductor layers at one end thereof, the other end of the electric conductor layers on the upper surface of the ceramic chip being lead patterns to be adapted for direct attachment to electric conductor parts formed on a separate printed circuit board in electrical connection therewith.
A conventional circuit element package generally has its circuit element (a transistor chip, for example) directly attached to a printed base plate with which it is electrically connected. The circuit element is further electrically connected to a separate printed circuit board by lead wires and the entire structure is finally sealed in synthetic resin. In this arrangement, a relatively large number of parts (the transistor chips and its lead wires etc.) must be attached to a printed base plate of relatively large size. As a consequence, the fabrication work is troublesome so that both productivity and product yield are low.
Furthermore, because of the difference between the coefficients of thermal expansion of the printed base plate and the synthetic resin, cracks are apt to develop in the resin and to break the lead wires.
Moreover, once such cracks have developed, the hygroscopic property of the resin promotes the infiltration of moisture thereinto. This moisture induces unwanted leakage current from the lead wires etc. and deteriorates the high frequency performance and reliability of the package.
In another conventional type of circuit element package, a transistor chip is attached to a square ceramic base plate and is further electrically connected by way of lead wires to pin-shaped terminals fixed to the base plate and the entire structure is sealed in a case fitted to the base plate. The projected terminals of the package-type circuit ele ment thus fabricated are soldered to a printed circuit board along with other circuit elements and the entire structure including the package-type circuit element and the printed circuit board are sealed in synthetic resin.
With this construction, the transistor chips and the lead wires are completely unaffected by the resin so that there is an improvement in reliability. However, this arrangement has disadvantages in that (1) stray capacitance develops between the pin-shaped ter minals and degrades the high-frequency characteristics of the circuit and (2) each package-type circuit element must be fabricated separately thus increas ing the number of fabrication steps per piece.
It is a general object of the present invention to provide a novel and useful circuit element package having lead patterns in which the above described difficulties have been overcome.
The present invention provides a circuit element package comprising a ceramic substrate having a concavity formed in the upper surface thereof, a plurality of discrete electric conductor layers printed on said upper surface of said substrate, each electric conductor layer having one end thereof located inside the concavity and the other end thereof located outside the concavity said other ends of the electric conductor layers forming lead patterns, and a circuit element accommodated within said concavity in electrical connection with said one ends of said electric conductor layers, said circuit element package being adapted to be mounted on a separate printed- circuit board with said lead patterns of the plurality of electric conductor layers respectively fixed in an electrically conductive manner to a plurality of electric conductor parts of said separate printed circuit board.
Another feature of the present invention is to provide a circuit element package adapted to be mounted on and electrically connected to a separate printed circuit board, which circuit element package is of a structure wherein a chip-formed circuit element is accommodated within and attached to a concavity formed in a ceramic substrate so as to be electrically connected with one ends of electrically conductive layers performed on the ceramic substrate by printing. The other ends of the conductive layers form lead patterns to be connected to a separate printed circuit board. Use of the circuit element package of this construction facilitates circuit fabrication and improves product yield.Furthermore, circuits fabricated using the circuit element packages according to this invention are free from unwanted stray capacitance and consequently have good high-frequency characteristics and reliability.
Another feature of the present invention is to provide a circuit element package which can be incorporated into a printed circuit in such a manner that both the circuit element and lead wires for connecting the circuit element to the one end of electrically conductive layers are free from contact with and are not covered by the synthetic resin material used for sealing. This construction precludes the lead wire breakage and leakage current which, in circuits employing conventional circuit element package, often occurs as a result of a difference in the coefficients of thermal expansion of their ceramic substrates and the synthetic resin in which they are sealed. The circuit element package according to this invention therefore enhances the high-frequency characteristics and reliability of the circuit in which it is incorporated.
Still another feature of the present invention is to provide a circuit element package which can be manufactured in large numbers as contiguous segments of a single base plate, whereby the manufacturing process is simplified and the unit cost of manufacture is reduced.
Afurtherfeature of the present invention is to provide a circuit element package wherein the concavity in the ceramic substrate is filled with molten glass so as to seal the circuit element. With this construction, since the coefficient of thermal expansion of the glass and that of the ceramic substrate are substantially equal, breakage of the lead wires and occurrence of leakage current are prevented so as to assure reliability and excellent high-frequency characteristics.
Furtherfeatures of the present invention will be apparent from the following detailed description with respect to preferred embodiments of the present invention when read in conjunction with the accompanying drawings, in which: Figure 1A is a fragmentary plan view, showing a ceramic base plate or substrate in the first step of the fabricating process for simultaneously fabricating a large number of circuit element packages according to one embodiment of the present invention; Figure 1B is a vertical sectional view taken along the line IB - IB in Figure 1A; Figure 2A is a fragmentary plan view showing the second step in the same process according to the present invention; Figure 2B is a vertical sectional view taken along the line IIB - IIB in Figure 2A;; Figure 3A is an enlarged plan view showing one part of the fabricated ceramic substrate illustrated in Figure 2A; Figure 3B is a vertical sectional view taken along the lines IllS - IlIB in Figure 3A; Figure 4A is a fragmentary plan view showing how chip-formed circuit elements are attached to the ceramic substrate shown in Figure 3A; Figure 4B is a vertical sectional view taken along the line IVB - IVB in Figure 4A; Figure 5A is a plan view showing one embodiment of a completed circuit element package; Figure 5B is a vertical sectional view taken along the line VB -VP in Figure 5A;; Figure 6 is a vertical sectional view of the circuit element package shown in Figures 5A and 5B illustrating the state in which it is fixed to a separate printed circuit board; Figures 7 and 8 are fragmentary vertical sectional views showing the first and second steps of the fabricating process for fabricating circuit element packages according to another embodiment of the present invention; Figure 9A is an enlarged plan view showing another embodiment of a completed circuit element package according to the present invention; Figure 9B is a vertical sectional view of the circuit element package shown in Figure 9A illustrating the state in which it is mounted on a separate printed circuit board;; Figure 70A is a perspective view showing still another embodiment of a circuit element package according to the present invention; Figure 105 is a vertical sectional view of the circuit element package shown in Figure 10A illustrating the state in which it is mounted on an separate printed circuit board; and Figure 11 is a plan view showing the process for fabricating the circuit element package shown in Flgure 10A.
Referring to Figure 1A through Figure 6, the structural arrangement of one embodiment of a circuit element package according to the present invention is described in terms of the process by which it is fabricated.
First, a plurality of electric conductor layer patterns 12 are printed on the upper surface of an unbaked ceramic substrate 11. The thickness of the ceramic substrate 11 is, for example, 600 microns and the patterns 12 are printed with molybdenum paste material as indicated by shaded portions in Figure 1A. The print-formed patterns 12 have a thickness of 30 microns, for example, and are regularly spaced in n number of rows (n = 4 in Figure 1A). Each electric conductor layer pattern 12 is destined to make electrical connection with a transistor chip 13 (Figure 4A) to be described below and for this purpose is comprised of electric conductor layers 14, 15 and 16 of which one ends are respectively connected with the collector, base and emitter of the transistor chip 13.The other ends of the conductor layers 14-16 are destined to be lead patterns.
The molybdenum paste material of the electric conductor layer patterns 12 is composed of molybdenum metal powder having a melting point of 2615 i 5 C and a specific electric resistance of 5.2 ij#cm, talc (also referred to as steatite and consisting of MgO, CaO, and SiO2), and sodium glass, and is formed to be a paste-like mixture by kneading with a suitable binder. The material of the electric conductor layer patterns 12, however, is not limited to molybdenum paste, but may be a tungsten paste using tungsten metal powder having a melting point of 3,380 C and a specific electric resistance of 4.9 RQcm, instead of the molybdenum powder of the above described composition, or a molybdenumtungsten paste wherein molybdenum powder and tungsten powder are mixed.Furthermore, there may be used a paste obtained by adding a small amount of some other metal having a high melting point and low specific electric resistance such as platinum to any of the above described paste components. The above described pastes are low in cost compared with the silver paste which has conventionally been used for electric conductor layers such as layers 14, 15 and 16. The molybdenum or tungsten of the paste used adheres to the base plate 11 with large bonding force, thus improving the quality of the circuit element packages. This can also be said of all of the other materials used to form the electric conductor layer patterns of the following embodiments.
After the printing of the conductor layer patterns 12, the substrate 11 is press formed to produce a step-concavity 17, having a step 17a and a bottom 17b, at the center of each electric conductor layer pattern 12, as illustrated in Figures 2A and 2B. (For simplicity of illustration, the electric conductor layer patterns 12 are not shown in Figure 2B.) In the press-forming operation described above, the electric conductor layers 14, 15 and 16 are deformed along the step-concavity 17. Specifically, the layer 14 is deformed so that its one end 14b is positioned on the bottom 17b of the step-concavity 17 and its other end 14a is positioned on the top surface of the substrate 11.The layers 15 and 16 are deformed so that one ends 15b and 16b are respectively positioned on the step 17a of the concavity 17 and other ends 15a and 16a are positioned on the top surface of the substrate 11.
The press-forming operation also forms V-shaped grooves 18 on the unbaked ceramic substrate 11.
These grooves are, for example, 100 ym in depth and are formed in order to facilitate division of the ceramic substrate into individual circuit element package. The grooves 18 extend in the vertical and lateral directions, thus forming a lattice pattern.
Next, the unbaked substrate 11 is subjected to high-temperature baking in an appropriate atomosphere and is thereby hardened to a specific hardness. Then, a very thin nickel plating layer (not shown) is formed on the electric conductor layers 14, 15 and 16. This nickel plating layer serves to ensure firm attachment of the transistor chip 13 onto the electric conductor layers 14, 15 and 16 as well as easy wire bonding.
Then, as illustrated in Figures 4A and 4B, the transistor chips 13, which are of a thickness on the order of 200 Clam, are accommodated one within each concavity 17. Each transistor chip 13 is bonded at its collector part onto the end part 14b of the electric conductor layer 14 by an electrically conductive adhesive 19. Furthermore, a first very fine aluminum wires 20 is bonded at its one end to the base part of the chip 13 and at its opposite end to the end part 15b of the conductor layer 15. This bonding operation is performed using a bonding apparatus employing supersonic waves. Similarly, a second very fine aluminum wire is bonded at one end to the emitter part of the chip 13 and at the other end to the end part 16b ofthe conductor layer 16.Accordingly, the base and emitter parts are electrically connected to the electric conductor layers 15 and 16. Gold wires may be used instead of the aluminum wires. Alternatively, the transistor chip 13 may be fixed to the end part 14b of the electric conductive layer 14 through heat pressure welding, with a gold film interposed therebetween. The work of connecting the aluminum wires 20 to the step 17a in the concavity 17 can be carried out with good efficiency.
Both the top of the chip 13 and the aluminum wires 20 bonded thereto are positioned below the top surface of the substrate 11.
Then, the ceramic substrate 11 indicated in Figures 4A and 4B is snapped off along the grooves 18 into a large number of circuit element package 21 like the one indicated in Figures 5A and 5B.
When a circuit element package 21 is to be mounted on a separate printed circuit board 22, for example, the upper surface of the circuit element package 21 is brought face-to-face with the printed surface of the printed circuit board 22. The end parts 14a through 16a of the electric conductor layers 14 through 16 positioned on the top surface of the substrate 11 are utilized as lead patterns. These lead patterns are respectively pushed against the printed layers 22a through 22c of the printed circuit board 22. As the printed layers 22a through 22c have been precoated with molten solder 23, the electric ele ment package 21 is fixed to the printed circuit board 22 by solder connection. Electrically conductive adhesive may be used instead of the solder 23.
Finally, the circuit element package 21 is entirely covered with synthetic resin 24 to seal it from the atmosphere.
With this construction, the circuit element package 21 having lead patterns consisting of end parts 14a, 15a, and 16a of the conductive layers 13, 15, and 16 does not require any lead wires for connecting the same to the printed circuit board 22. Accordingly, the stray capacitance, which is unavoidable when lead wires are used, does not develop so that the circuit, in which the circuit element package 21 is included, exhibits good high-frequency characteristics.
Furthermore, since the chip 13 and the wires 20 are free from contact with and are not covered by the synthetic resin 24, the possibility of wire breakage and leakage current present in conventional devices is completely eliminated. Therefore, the circuit, in which the circuit element package 21 is incorporated, is assured of having good high-frequency characteristics and reliability.
Moreover, the method of fabricating the circuit element packages described above makes it possible to manufacture them at much lower cost than would be possible in the case of fabricating such circuit element packages individually from the initial fabricating step.
In a modification of this embodiment, several circuit element packages 21 are snapped off as a contiguous group and are used as they are without being snapped into individual packages.
Other types of circuit element than the transistor chip 13 can be used as the circuit element of the device of the present invention. For example, the transistor chip 13 can be replaced by an active element such as a diode or IC, by a passive element such as a resistor or capacitor, or by an electrical-tomechanical transducing element, filter element, or the like. The number of electric conductor layers (14 through 16 in the embodiment described) can be increased or decreased as required.
Figures 7 and 8 show steps in the process of fabrication of another embodiment of a circuit element package according to the present invention.
In Figures 7 and 8, those parts which are the same as coresponding parts in Figure 4B are designated by like reference numerals. Detailed description of such parts will be omitted.
Referring to Figures 7 and 8, the substrate 11 has transistor chips 13 fixed thereto, similartothe preceding case indicated in Figures 4A and 4B. A jig plate 31 formed with through-holes 31a is layed on the upper surface of the substrate 11, with holes 31a thereof in registration with the transistor chips 13.
Glass beads 32a are fitted into the holes 31 a, whereby one glass bead comes to rest on each transistor chip 13. Thereafter, the jig plate 31 is removed from the substrate 11. The glass beads 32a are made of an appropriate material such as lead borosilicate or borosilicate glass. These materials have a coefficient of thermal expansion a1 (= 72 x 10-7 1/or), which is substantially equal to the coefficient of thermal expansion a2 (= 70 x 10~7 1/or) of the substrate 11. Furthermore, the material has a melting temperature between 3600C to 430 C. This means that the electric conductor layer patterns 12 are prevented from oxidazation at the melting temperature of the material and that the material does not melt again when the package is subjected to dip soldering operation.
Next, the substrate 11 having glass beads 32a layed thereon is heated up to the above described melting point between 360 C to 4300C to melt the glass beads 32a. The substrate 11 having molten glass within the concavities 17 is thereafter subjected to air cooling in a dry atmosphere. The molten glass gradually solidifies to form a glass seal 32b.
The chip 13 and the wires 20 are securely sealed within the glass seal 32b. The top surface of the glass seal 32b is positioned a specific distance below the upper surface of the substrate 11,thus allowing the substrate 11 to be mounted onto the printed circuit board 22.
Then, the substrate 11 is snapped off along the separation grooves 18, and a large number of circuit element packages 33 as indicated in Figures 9A and 9B are thereby obtained. The circuit element package 33 thus obtained is attached to the printed circuit board 22, as illustrated in Figure 9B, in the same manner as in the case of Figure 6. In this embodiment, the provision of the glass seal 32b makes the synthetic resin 24 illustrated in Figure 6 unnecessary.
Here, as mentioned above, the glass beads 32a are made of a selected material having a melting point between 3600C to 430 C. The heating temperature for melting the glass beads 32a (in this case, around 430 C) is lower than the oxidation temperature of the electric conductor layers 14through 16 and therefore does not damage the electric conductor layers by oxidation. Furthermore, the solder heating temperature (in this case, less than 360 C) for mounting the circuit element package 33 to the printed circuit board 22 does not exceed the melting point of the glass seal 32b. Thus, no trouble arises as a result of heat application in either the bead melting step or the soldering step.
Furthermore, since the substrate 11 and the glass seal 32b have substantially equal coefficients of thermal expansion, cracks do not occur in the glass seal 32b and there is no danger of wire breakage.
Moreover, since the glass seal 32b does not develop cracks and is not hygroscopic, no wire leakage current develops.
In the fabrication process described above, the operation of positioning the glass beads 32a is simpler than the operation involved in injecting molding of the conventional synthetic resin seal and the setting time required for the glass seal 32b is only about ten minutes, approximately one sixth of the setting time for a synthetic resin seal (one hour).
Accordingly, this fabrication process can be automated with ease.
Figures 10A and 105 show still another embodiment of the circuit element package according to the present invention. In these figures, those parts corresponding to parts in Figures 5A and 5B are designated by like reference numerals, and detailed description of such parts will not be repeated.
Referring to Figure 1 or, the ceramic substrate 35 of a circuit element package 34 has a concavity 36 formed at the center part thereof and has cuts 37 formed at three lateral sides thereof so as to pass through in the direction of thickness thereof. On the surface of the ceramic substrate 35, are provided three print-formed electric conductor layers 38,39, and 40, one end (38b, 39b or 40b) of each of which extends into the concavity 36 and the other end (38a, 39a, or 40a) of each of which reaches the one of the cuts 37. The end 38b of the electric conductor layer 38 reaches the bottom of the concavity 36.The transistor chip 13 is attached to the upper surface of the end 38b of the electric conductor layer 38 in electrical connection therewith and is electrically connected through the pair of fine wires 20 to the remaining electric conductor layers 39 and 40 at the ends 39b and 40b thereof. The concavity 36 is then filled with the glass seal 32b as in the case of the circuit element package 33 described above.
The circuit element package 34 of the structure described above is mounted on the printed circuit board 22, as indicated in Figure 1 or. Solder 23 is applied so as to make contact with both the printed layer 22b on the printed circuit board 22 and the end 40a of the electric conductor layer 40 in the cut 37.
Solder is also applied is the same manner with respect to the other printed layers 22a and 22c (one layer 22a not being shown) and the associated cuts 37. The cuts 37 serve to prevent the solder 23 from flowing sideways along the lateral sides of a ceramic substrate chip 35, whereby unwanted solder flow is prevented, thus improving adhesion strength.
Next, a description is given of a method of manufacturing the substrate chip 35. Referring to Figure 11, an unbaked ceramic substrate 41 of large size is subjected to press working, thus forming the separation grooves 18, the concavities 36, and openings 42. The separation grooves 18 partition the substrate 41 into a number of substrate chips 35 including each having one concavity 36. The openings 42 are punched in substantially elliptical shape at the boundaries between adjacent substrate chips 35.
Following this, the electric conductor layers 38 through 40 are printed to extend to the internal periphery of the openings 42. After baking of the substrate, the substrate chips 35 are snapped off along the grooves 18. At this time, the openings 42 help to ensure that the substrate chips 35 will be snapped off accurately along the separation grooves 18.
Further, this invention is not limited to these embodiments but various variations and modifications may be made without departing from the scope of the invention.

Claims (7)

1. A circuit element package comprising: a ceramic substrate having a concavity formed in the upper surface thereof; a plurality of discrete electric conductor layers printed on said upper surface of said substrate, each electric conductor layer having one end thereof located inside the concavity and the other end thereof located outside the concavity said other ends of the electric conductor layers forming lead patterns; and a circuit element accommodated within said concavity in electrical connection with said one ends of said electric conductor layers; said circuit element package being adapted to be mounted on a separate printed circuit board with said lead patterns of the plurality of electric conductor layers respectively fixed in an electrically conductive manner to a plurality of electric conductor parts of said separate printed circuit board.
2. A circuit element package as claimed in claim 1, wherein said concavity has a step formed midway between the top and bottom thereof, the one end of one electric conductor layer is formed to extend to the bottom of said concavity, and the one ends of the remaining electric conductor layers are formed to extend to said step.
3. A circuit element package as claimed in claim 1, wherein said other ends of the electric conductor layers are located on the upper surface of said substrate, and said other ends of said electric conductor layers on said substrate are disposed to confront the plurality of electric conductor parts on said separate circuit board, thereby to be fixed in electrical connection therewith.
4. A circuit element package as claimed in claim 1, wherein said other ends of the electric conductor layers are located on the outer lateral surfaces of said substrate, each said outer lateral surface being disposed substantially perpendicular to the plurality of electric conductor parts on said separate circuit board, thereby to be fixed in electrical connection therewith by electric conductive material applied in the shape of a fillet weld.
5. A circuit element package as claimed in claim 1 which further comprises glass material in said concavity to seal said circuit element, said glass material having a coefficient of thermal expansion substantially the same as that of said ceramic substrate.
6. A circuit element package as claimed in claim Sin which said glass material is lead borosilicate or borosilicate glass.
7. A circuit element package having lead patterns substantially as described with reference to the accompanying drawings.
GB7914818A 1978-07-18 1979-04-27 Circuit element package having lead patterns Expired GB2026234B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53086745A JPS5835367B2 (en) 1978-07-18 1978-07-18 Circuit element board and its manufacturing method

Publications (2)

Publication Number Publication Date
GB2026234A true GB2026234A (en) 1980-01-30
GB2026234B GB2026234B (en) 1982-06-30

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GB7914818A Expired GB2026234B (en) 1978-07-18 1979-04-27 Circuit element package having lead patterns

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JP (1) JPS5835367B2 (en)
DE (1) DE2925509A1 (en)
GB (1) GB2026234B (en)

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FR2512990A1 (en) * 1981-09-11 1983-03-18 Radiotechnique Compelec METHOD FOR MANUFACTURING AN ELECTRONIC PAYMENT CARD, AND CARD PRODUCED ACCORDING TO SAID METHOD
GB2130794A (en) * 1982-11-27 1984-06-06 Prutec Ltd Electrical circuit assembly
EP0080535B1 (en) * 1981-11-27 1985-08-28 Krohne AG Measuring head for an electro-magnetic flow meter
US4578697A (en) * 1981-06-15 1986-03-25 Fujitsu Limited Semiconductor device encapsulating a multi-chip array
EP0478426A1 (en) * 1990-09-28 1992-04-01 Thomson-Csf Method of fabrication for a hybrid module
EP0598914A1 (en) * 1992-06-05 1994-06-01 MITSUI TOATSU CHEMICALS, Inc. Three-dimensional printed circuit board, electronic circuit package using this board, and method for manufacturing this board

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JPS60211960A (en) * 1984-04-06 1985-10-24 Hitachi Ltd Semiconductor device
US4839713A (en) * 1987-02-20 1989-06-13 Mitsubishi Denki Kabushiki Kaisha Package structure for semiconductor device
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JP2914861B2 (en) * 1993-12-02 1999-07-05 富士車輌株式会社 Garbage sorting equipment
US5408126A (en) * 1993-12-17 1995-04-18 At&T Corp. Manufacture of semiconductor devices and novel lead frame assembly
US5629835A (en) * 1994-07-19 1997-05-13 Olin Corporation Metal ball grid array package with improved thermal conductivity

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* Cited by examiner, † Cited by third party
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US4578697A (en) * 1981-06-15 1986-03-25 Fujitsu Limited Semiconductor device encapsulating a multi-chip array
FR2512990A1 (en) * 1981-09-11 1983-03-18 Radiotechnique Compelec METHOD FOR MANUFACTURING AN ELECTRONIC PAYMENT CARD, AND CARD PRODUCED ACCORDING TO SAID METHOD
EP0075351A1 (en) * 1981-09-11 1983-03-30 Rtc-Compelec Method of making an identity card, and identity card produced, for example, by means of this method
EP0080535B1 (en) * 1981-11-27 1985-08-28 Krohne AG Measuring head for an electro-magnetic flow meter
GB2130794A (en) * 1982-11-27 1984-06-06 Prutec Ltd Electrical circuit assembly
EP0478426A1 (en) * 1990-09-28 1992-04-01 Thomson-Csf Method of fabrication for a hybrid module
FR2667443A1 (en) * 1990-09-28 1992-04-03 Thomson Csf METHOD FOR PRODUCING A HYBRID MODULE
EP0598914A1 (en) * 1992-06-05 1994-06-01 MITSUI TOATSU CHEMICALS, Inc. Three-dimensional printed circuit board, electronic circuit package using this board, and method for manufacturing this board
EP0598914A4 (en) * 1992-06-05 1994-11-23 Mitsui Toatsu Chemicals Three-dimensional printed circuit board, electronic circuit package using this board, and method for manufacturing this board.
US5639990A (en) * 1992-06-05 1997-06-17 Mitsui Toatsu Chemicals, Inc. Solid printed substrate and electronic circuit package using the same

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GB2026234B (en) 1982-06-30
JPS5513933A (en) 1980-01-31
DE2925509A1 (en) 1980-01-31
JPS5835367B2 (en) 1983-08-02

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