JPH05342118A - Method and device for data communication obtained by combining synchronization control and pipeline control - Google Patents

Abstract

PURPOSE:To provide a method and a device for a data communication, for reducing the communication processing of a computer and also having high transmission efficiency in a computer network. CONSTITUTION:Transfer of information data between computers, and the transfer of processor control information are executed by a communication by a pipeline control system and a communication by a synchronization control system respectively. A write address/data line 30 and a read-out data line 33 are provided separately and used in common by both communication systems. As for a control signal transmission path, it is provided separately on both systems. Also, register groups 15, 16 are provided for a communication by the pipeline control system and by controlling them in response to control of a synchronizing communication control procedure, data lacking at the time when the switching of a communication by both the communication systems is generated is prevented. By taking such constitution, a communication method corresponding to the quality of information transferred between the computers can be taken, the load of a communication processing of the computer is reduced and also an efficient data communication can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication method between digital computers, and more particularly to a data communication method when the transmission distance is relatively long.

[0002]

2. Description of the Related Art Conventionally, an inter-computer data communication method using a synchronous procedure and an asynchronous procedure has been known. When performing communication by the synchronization procedure, the computers exchange, for example, a transmission request signal, a transmission acknowledge signal, etc.,
Information is sent and received after synchronization between computers. On the other hand, in the asynchronous procedure, synchronization is not established before transmission / reception of information between computers, but information is transmitted / received as necessary. For example,
FIFO (First In First) between computers
This is a pipeline procedure in which the transmitting side and the receiving side operate completely asynchronously, such as providing an (Out) memory, the transmitting side writing to the FIFO memory at any time, and the receiving side reading out at a convenient time. Conventionally, either one was used for communication between computers.

[0003]

Since the conventional computer-to-computer data communication method is based on one of the above procedures, the following problems occur. In the computer data communication method based on the synchronization procedure, since the connected computers perform the processing in synchronization with each other, it is easy to synchronize each other's processing, and it is easy to perform the processing coordinated by the software. However, when there is a relatively large distance between computers and the transmission delay is large, there is a problem that the transmission amount of information is likely to be limited because the transmission line and the computer cannot operate in parallel. on the other hand,
In the computer data communication method by the asynchronous procedure, information can be transmitted and received regardless of the processing of the connected computer, so the transmission line and the computer can operate in parallel, and the information transmission amount is larger than that of the synchronous communication procedure. Can be taken. However, since the processing between computers progresses asynchronously, there is a problem that it is difficult to grasp the state of the computer and the transmission path of the communication partner, and it is difficult to coordinate the software between the computers.

[0004]

In order to solve the above problems, the data communication method of the present invention provides a synchronous communication between computers in a computer network in which a plurality of computers are connected to each other and information is transmitted and received between the computers. Information of different nature is transmitted and received by the method and the asynchronous communication method. The communication method for transmission is selected according to the nature of the information to be transmitted and received. Information transmission and reception are performed by independent routes, and the information transmission route is shared by both procedures.

Further, the data communication apparatus of the present invention has synchronous communication control means and asynchronous communication control means corresponding to each control transmission path in the computer network. Further, it has means for temporarily storing information in the information transmission path and sequentially sending it, and means for bypassing the means at least in response to the control of the synchronous communication control means. In addition, the information transmission path and the information reception path are independently provided and shared by the respective communication means. Then, the synchronous communication control means and the asynchronous communication control means control the means for temporarily storing the information and sequentially sending the information. In particular, pipeline control means is used for transmitting and receiving information data.

[0006]

According to the data communication method of the present invention, information having different properties is transmitted / received by the synchronous communication system and the asynchronous communication system, and the communication system at the time of transmission is selected according to the property of the information to be transmitted / received. Send and receive information in a manner suitable for. In addition, the information transmission efficiency is improved by transmitting and receiving the information through independent paths, and the number of cables connecting the computers is reduced by sharing the information transmission path by both procedures.

Further, the data communication apparatus of the present invention is capable of transmitting and receiving information by a method suitable for the nature of each information by the synchronous communication control means and the asynchronous communication control means corresponding to each control transmission path. To do. The means for temporarily storing information in the information transmission path and sequentially sending it out, and at least the means for bypassing the means in response to the control of the synchronous communication control means are transmitted and received by asynchronous communication when the communication control means is switched. The missing information. The information transmission path and the reception path provided independently increase the information transmission efficiency. The synchronous communication control means and the asynchronous communication control means temporarily store the information, and the means for sequentially sending the information makes it possible to easily and quickly switch between the two communication methods.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a diagram showing the configuration of the processor element (PE) shown in FIG. The present invention is applied to a PE of a parallel computer network including a computer for symbol processing (EU in FIG. 3) as shown in FIG. 3 and a computer (RM in FIG. 3) used for man-machine interface and storage. Evaluator (EU) and resource manager (RM) are connected by RM interface (RM I / F), and EU to R
Send function data to M. Further, information data is sent from the EU through the main memory interface (MM I / F) and sent to the main memory (MM) and RM. The RM I / F and MM I / F are connected to the ALU via an internal bus (IBUS) in the EU. Also, R
The M I / F is connected to the WS via an evaluator interface (EU I / F) in the RM. EU is A
LU, masker, shifter, local memory, register file, user stack, dispatch table, instruction cache, system controller, control memory, IBUS, diagnostic statics, RM I / F and MM I / F. WSR3000, diagnostics interface, communication interface, secondary storage, M
M, a pointer manipulator, and an EU I / F.

Further, a large number of LANs are connected to each PE in the form as shown in FIG. 2B to form a larger-scale computer network. FIG. 1 is a block diagram of an inter-computer interface used in the data communication method of the present invention. Figure 1
Are RM I / F, EU I / F and M in FIG.
This corresponds to a detailed description of the configuration included in each part of the M I / F. Note that, in FIG. 3, a portion related to the synchronous communication system on the first computer 1 side of FIG. 1 is omitted.

A description will be given below with reference to FIG. The first computer 1 corresponds to the RM of FIG. 3 and receives information data such as the calculation result of the second computer 2 and displays it on the CRT display according to the processor control data also received from the second computer 2 or the magnetic field. It is a digital computer that performs operations such as storing in a storage device. The second computer 2 corresponds to the EU of FIG. 3 and is a digital computer used for a specialized purpose for performing symbolic operations and the like at high speed. A cable 3 connecting the first computer 1 and the second computer 2 is a cable connecting both the computers.

Hereinafter, reading and writing are based on the first computer 1. Hereinafter, each part of the first computer 1 will be described. The expressions of reading and writing are based on the first computer 1. The CPU interface 10 is a CPU interface that decodes control lines and addresses of the CPU. Here, each control signal used in the data communication method and apparatus of the present embodiment is generated. Address and output data latch 11
Is a register that latches an address and output data. The write pipeline controller master side 12 is the master side of the write pipeline controller. A signal WSTB used for write pipeline control is generated, and WAC is generated.
Accept K. The synchronization control data buffer 13 is a buffer that sends read data to the CPU data bus during synchronization control. The pipeline control read buffer 14 is a buffer that sends data to the CPU data bus during pipeline control. The pipeline control read register (transmission line side) 15 is a register for storing data to be sent to the CPU next during pipeline control. The slave side 16 of the read pipeline control unit is a register that stores the data sent through the transmission line during pipeline control. The slave side 17 of the read pipeline control unit receives the RSTB used for the read pipeline control and generates RACK.
The synchronization controller master side 18 generates DREQ and
Accept K. The CPU 19 of the first computer 1 performs information processing and control of the first computer 1.

The respective parts of the second computer 2 will be described below. The WD signal latch 20 is set to W during pipeline control.
This is a register for latching the data sent from D under the control of the WSTB 31. The write pipeline controller slave side 21 receives the WSTB and notifies the second computer 2 of the arrival of data. In addition, the end of the data processing of the second computer 2 is accepted and WACK is generated. The data selector 22 is a data selector that selects data to be sent to the read data (RD) line 33. The synchronous read data or the pipeline read data is selected under the control of the synchronization controller slave side 25. The read pipeline control unit master side 23 receives the data transfer request from the second computer 2 and generates the RSTB signal. Further, upon receipt of the RACK pulse, the second computer 2 is notified of the end of data transfer. The WD signal buffer 24 is a buffer that receives data from the WD and outputs the data to the synchronous write data line. The output timing is controlled by a signal output from the synchronization controller slave side 25. The synchronization controller slave side 25 receives the DREQ and requests access to the second computer 2. Further, upon receipt of the access processing completion notification from the second computer 2, the DACK is generated. The synchronous write address line 26 is a read address line used during synchronous communication inside the second computer 2. The synchronous write data line 27 is a read data line used during synchronous communication inside the second computer 2. The pipeline read data line 28a is a read data line used during synchronous communication inside the second computer 2. Pipeline read data line 2
Reference numeral 8b is a read data line used during pipeline communication inside the second computer 2. CPU 29 of the second computer 2
Performs information processing and control of the second computer 2. In addition,
The second computer 2 also has a CPU interface having the same function as the CPU interface 10 of the first computer 1, but it is omitted for simplification of description.

The respective parts of the cable 3 connecting the first computer 1 and the second computer 2 will be described below. The write address signal (WA) and write data signal (WD) transmission line 30 has an address (WA) and write data (W).
D) is a transmission line to be sent. The write data strobe signal (WSTB) transmission line 31 is a transmission line that sends the write strobe signal (WSTB) during pipeline control. The write data acceptance signal (WACK) transmission line 32 is a transmission line that sends a signal (WACK) indicating acceptance of write data during pipeline control. The read data signal (RD) transmission line 33 is a transmission line to which the read data (RD) is sent. The pipeline control read strobe signal (RSTB) transmission line 34 is used for the read strobe signal (RST) during pipeline control.
It is a transmission line for sending B). The pipeline control read data acceptance (RACK) signal transmission line 35 is a signal (RAC) indicating acceptance of read data during pipeline control.
K) is a transmission line. The synchronous control data request (DREQ) signal transmission line 36 is a (DREQ) transmission line that requests data transmission in synchronous control. The synchronous control data transmission end (DACK) signal transmission line 37 is a transmission line for returning the end of data transmission in synchronous control (DACK).

The address space related to the interface of the data communication method and the apparatus of this embodiment is as shown in FIG. An address space for synchronous control and an address space for pipeline control are provided separately.
Also, the CP required for the processing of the CPU interface 10.
An interface register space 42 is provided for accessing the registers in the U interface 10. Figure 4
In the above, the synchronous address space 40 is an address space used when performing synchronous communication. The read access to this space causes activation of each control unit such as the synchronization control unit master side 18 that operates during the synchronous communication. The pipeline address space 41 is an address space used when performing pipeline communication. Specifically, access to this address is restricted to register 15
It is equivalent to accessing the control unit and simultaneously causes activation to each control unit such as the slave side 17 of the read pipeline control unit that operates during pipeline communication.
Further, when the data is accessed and read out, pipeline writing occurs at the same time.
The data information is configured so that it can be set arbitrarily.
The interface register space 42 is provided for the purpose as described above. For example, the address of a register for resetting the entire communication device or the CPU of each computer reads the state of each control signal such as WACK. Addresses etc. are assigned. In addition to the pipeline address space, an address for accessing the register 15 is also provided here.

The operation when the first computer 1 writes processor control data to the second computer 2 using the synchronous communication system will be described below with reference to FIG. In this case, the address / data information includes the address / output data latch 11 and the write address signal (WA).
And write data signal (WD) transmission line 30 and WD
It is written in the second computer 2 via the signal buffer 24. Further, the control unit used is the synchronization control unit master side 1
8 and the synchronization controller slave side 25. Step 01
In (S01), the CPU 19 of the first computer 1 performs write access of the synchronous control method to the CPU interface 10. The CPU interface 10 activates the master side 18 of the synchronization control unit. The address and data output from the CPU interface 10 are latched by the register 11 and output to the write data line 30.

In step 02 (S02), S01
The master side 18 of the synchronization control unit activated in 1 activates the DREQ on the synchronization control data request (DREQ) signal transmission line 36 and activates the synchronization control unit slave side 25. The activated synchronization control unit slave side 25 issues an access request to the CPU 29 of the second computer 2. At the same time, the output of the synchronous write data line 27 is activated under the control of the slave side 25 of the synchronous control unit, and the address is output to the synchronous address line 26 and the data is output to the synchronous write data line 27.

In step 03 (S03), when the access from the CPU 29 of the second computer 2 ends, the synchronous control unit slave side 25 ends the synchronous control data transmission (D
The ACK) signal transmission line 37 is sent out by DACK, and the synchronization control unit master side 18 which received it notifies the CPU interface 10 and the CPU 29 of the second computer 2 of the end. This completes the write operation of the CPU 19 of the first computer 1.

The operation when the first computer 1 reads the processor control data from the second computer 2 using the synchronous communication system will be described below with reference to FIG. In this case, the address information is the output data latch 1
1. Write address signal (WA) and write data signal (WD) transmission line 30 and WD signal buffer 24
The data information is written into the second computer 2 via the data selector 22, the read data signal (RD) transmission line 33, and the synchronization control data buffer 13 and then read into the first computer 1. The control units used are the synchronization control unit master side 18 and the synchronization control unit slave side 25.

In step 11 (S11), the CPU 19 of the first computer 1 makes a write access of the synchronous control method to the CPU interface 10. CPU
The interface 10 activates the master side 18 of the synchronization controller. The address output from the CPU interface 10 is latched by the register 11 and output to the write data line 30. In step 12 (S12),
The activated synchronization control unit master side 18 activates the synchronization control unit slave side 25. In step 13 (S13), the activated synchronization control unit slave side 25 issues an access request to the CPU of the second computer 2. At the same time, the WD signal buffer 24 is activated and the synchronous write address line 26
The address is output to.

In step 14 (S14), data is set on the synchronous read data line 28a, and the end of access is returned to the synchronous controller slave side 25. The synchronization controller slave side 25 receiving this returns DACK to the master side 18 of the synchronization controller. At this time, the data selector 22
It is assumed that the synchronous read data line 28a is selected under the control of the synchronous controller slave side 25.

In step 15 (S15), the DAC
Upon receiving K, the synchronization control unit master side 18 notifies the CPU interface 10 of the end and activates the buffer 13. As a result, the data from the second computer 2 is taken into the CPU 19 of the first computer 1 via the read data signal (RD) transmission line 33. First computer 1
The CPU 19 read cycle ends. Communication using the above-mentioned synchronous control method is performed by accessing the synchronous address space of FIG.

The operation when the first computer 1 writes information data to the second computer 2 using the pipeline control method will be described below with reference to FIG. In this case, the address / data information is sent to the second computer 2 via the address and output data latch 11, the write address signal (WA) and write data signal (WD) transmission line 30 and the WD signal latch 20. Written.
The control units used are the write pipeline control unit master side 12 and the write pipeline control unit slave side 21. In step 51 (S51), the CPU 19 of the first computer 1 issues a pipeline control write request. CPU interface 10
Receives the request, activates WREQ, and activates the pipeline controller master side 12. The address and data are latched by the register 11 and output to the write data line 30.

In step 52 (S52), the activated pipeline controller master side 12 sends the WSTB on the write data strobe signal (WSTB) transmission line 31.
It activates the signal and at the same time deactivates the WAC signal to the CPU interface 10.

Here, the pipeline controller master side 12
If the WAC is activated when WREQ is activated, immediately generates an access end notification signal to the CPU 19 of the first computer 1. On the contrary, when the WAC is not activated, the CPU 19 of the first computer 1 is made to wait until the WAC is activated. At this time, the generation of the access end notification signal is postponed until the WAC is activated. WAC is a write data acceptance signal (WACK)
It is activated when the WACK on the transmission line 32 is returned. The relationship between these signals is shown in FIG.

In step 53 (S53), the pipeline control section slave side 21 receives the WSTB and notifies the second computer 2 of the arrival of data. Second calculator 2
When the processing of the CPU 29 is completed, the pipeline control unit slave side 21 returns WACK to the pipeline control unit master side 12.

In step 54 (S54), the WAC
The pipeline control unit master side 12 that has received K is WAC
Activate. The activation of the WAC notifies the CPU interface 10 of the end of the write access when using the pipeline control method. With the above, C of the second computer 2
Data writing to the PU 29 is completed.

Here, when the second computer 2 has a write request of the pipeline control method, the write access when the pipeline control method is used is activated again. When there is no request, the CPU 19 of the first computer 1 has already been notified of the end of processing, and it is not necessary to activate write access when using the pipeline control method.

The operation when the first computer 1 reads the information data of the second computer 2 using the pipeline control method will be described below with reference to FIG. When the CPU 29 of the second computer 2 receives the write request and needs to return the information to the first computer 1, it activates the master side 23 of the read pipeline control unit to send data to the first computer 1 side. return it. The returned data is the first calculator 1
It is stored in the register 15 until read by the CPU 19.

In this case, the address / data information includes the data selector 22 and the read data signal (RD).
Transmission line 33, pipeline control read buffer 1
4. Pipeline control read register (transmission path side)
The data is read into the first computer 1 via 15 and the pipeline control read register (transmission path side). The control units used are the slave side 17 and the read pipeline control unit master side 23 of the read pipeline control unit. In step 61 (S61), the read pipeline control unit master side 23 is the CPU of the second computer 2.
It is activated by 29. As a result, the read pipeline control unit master side 23 generates the RSTB signal. As a result, the read data is stored in the register 16. Furthermore, the slave side 17 of the read pipeline control unit is activated. At this time, the data selector 22 selects the pipeline read data line 28b under the control of the read pipeline controller master side 23. In step 62 (S62), the slave side 17 of the read pipeline control unit, if the register 15 is empty,
The contents of the register 16 are transferred to the register 15. Here, the confirmation that the register 15 is empty is performed by the RAC signal to the CPU 19 interface of the first computer 1. If RAC was activated, then 15 is not empty, and if inactive, 15 is empty. If data is written in the register 16 and the register 15 is not empty, the register 1 is used until the register 15 becomes empty.
The transfer of data to 5 is postponed.

In step 63 (S63), when the data is transferred to the register 15, the read pipeline controller slave side 17 returns the RACK signal to the pipeline controller master side 23.

The read access of the CPU interface 10 and the CPU of the first computer 1 when the pipeline control method is used is as follows. When performing a read access to the data stored in the register 15, if the register 15 is empty, the CPU waits until the data arrives at the register 15. This access is performed in the form of access to the interface register space 42 of FIG. The timing at this time is shown in FIG. Above,
The transfer of the read data to the CPU 19 of the first computer 1 ends.

The second embodiment of the present invention will be described below. In the case where the computer of the first embodiment has a limited address space and cannot take the synchronous control space and the pipeline control space separately, both are taken in the same space as shown in FIG.
This is a method in which a register in the PU interface is used to share the address space with each other, and the address space used for communication processing is switched between synchronous communication and pipeline communication. In this case, the interface register space 42
A switching register is provided in the device, and when the register is set to 0, for example, the circuit for synchronous communication operates, and when the register is set to 1, the circuit for pipeline communication operates. This switching is performed by a method in which the CPU of each computer sets the register prior to communication processing and switches according to the intended use.

The third embodiment of the present invention will be described below. In this embodiment, communication is performed by accessing the pipeline address space 41 instead of the interface register space 42 during pipeline communication. In the first embodiment, in the read access of the CPU interface 10 and the CPU of the first computer 1 when using the pipeline communication, by accessing the pipeline address space, at the same time as the reading of the register 15, the write pipeline communication is performed. To send address data to the first computer 1. By giving a meaning to the address, the data is continuously received by receiving the data and simultaneously issuing a request for sending the next data.

A description will be given below with reference to FIG. The second computer 2 has n registers 5 as shown in FIG.
0 to 52 to 5n. These addresses are shown in FIG. 11 (B).
It is supposed to be. However, for simplification of description, only the addresses of the registers 50 to 52 are shown here. Of the address information on the write address signal (WA) and the write data signal (WD) transmission line 30, bits 23 to 4 indicate the register set A, and bit 23
3 indicates whether read (0) or write (1), and bit
Specify the register with 2 to 0. Hereinafter, a case of accessing the register set A will be described. When the first computer 1 writes to the register 52, bits 3 to 0
Is set to 1010, write data is designated, and the write operation is performed. With the above, writing to the register 52 is completed. When the first computer 1 reads the register 50, bits 3 to 0 are set to 0100 and write access is performed first. Here, since the bit3 is 0 even though it is the write access, the write data is discarded. Here, the CPU 29 of the second computer 2 interprets the address, reads the register 52, and sends it to the first computer 1. First calculator 1
The CPU 19 can read the pipeline control read register (transmission path side) 15 to obtain the transmitted value. Each register can be read and written by the same method as above.

In the case of reading and writing such a register, first, the first computer 1 performs pipeline writing, and then reads the register 50 in the pipeline address space 41. At this time, bits 3 to 0 of the address information output by the first computer 1 are designated as 0010, and the next read register is designated as the register 51. When reading the register 51 in the next pipeline space, bits 3 to 0 of the address information are set to 0100 and the register 52 is designated. Thus, when reading is performed, continuous reading is possible by designating the address of the register to be read next.

The data communication method and apparatus of the present invention are not limited to the above-mentioned embodiment, and various other configurations can be adopted. Further, the above-described device configuration is an example.

[0037]

According to the data communication method of the present invention, information having different properties is transmitted / received by the synchronous communication system and the asynchronous communication system, and each information is selected by selecting the communication system at the time of transmission according to the property of the transmitted / received information. Information is transmitted and received by a method suitable for the nature of. In addition, the information transmission efficiency is improved by transmitting and receiving the information through independent paths, and the number of cables connecting the computers is reduced by sharing the information transmission path by both procedures.

As described above, according to the data communication method and the apparatus for combining the synchronous control and the pipeline control of the present invention, information can be transmitted and received by a method suitable for the property of each information, and the above communication is performed. A data communication method capable of preventing loss of information transmitted / received by synchronous communication when the control means is switched, improving information transmission efficiency, and capable of easily and promptly switching between the both communication systems, and A device can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an inter-computer interface used in a data communication method of the present invention.

FIG. 2 is a configuration diagram of a computer network to which the data communication method of the present invention is applied.

FIG. 3 is a configuration diagram of a computer to which the data communication method of the present invention is applied.

FIG. 4 is a diagram showing an address space of a computer to which the data communication method of the present invention is applied.

5 is a diagram showing an operation when the first computer 1 writes data to the second computer 2 by using the synchronous communication system. FIG.

FIG. 6 is a diagram showing an operation when the first computer 1 reads data from the second computer 2 by using the synchronous communication system.

FIG. 7 is a diagram showing an operation when the first computer 1 writes data to the second computer 2 by using the pipeline control method.

FIG. 8 is a timing chart of a write side pipeline control of a computer interface applied to the data communication method of the present invention.

FIG. 9 is a diagram showing an operation when the first computer 1 reads data from the second computer 2 by using the pipeline control method.

FIG. 10 is a diagram showing an address space when the synchronization control address space and the pipeline control address space are shared in the data communication method of the present invention.

FIG. 11 is a diagram showing an access method according to a third embodiment of the present invention.

[Explanation of symbols]

1 ... 1st computer 2 ... 2nd computer 3 ... Cable connecting 1st computer 1 and 2nd computer 2 10 ... CPU interface 11 ... For address and output data Latch 12 ... Write pipeline control unit master side 13 ... Synchronous control data buffer 14 ... Pipeline control read buffer 15 ... Pipeline control read register (CP
U side) 16 ... Pipeline control read register (transmission path side) 17 ... Read pipeline control unit slave side 18 ... Synchronous control unit master side 19 ... CPU 1 of the first computer 1 ... WD signal latch 21 ... write pipeline controller slave side 22 ... data selector 23 ... read pipeline controller master side 24 ... WD signal buffer 25 ... synchronization controller Slave side 26 ... Synchronous write address line 27 ... Synchronous write data line 28a ... Synchronous read data line 28b ... Pipeline read data line 29 ... CPU 2 of the second computer 2 ... Write address signal (WA) and write data signal (WD) transmission line 31 ... Write data strobe signal (WST) )
Transmission line 32 ... Transmission line for write data acceptance signal (WACK) 33 ... Transmission line for read data signal (RD) 34 ... Transmission line for pipeline control read strobe signal (RSTB) 35 ... Accept pipeline read data (RA
CK) signal transmission line 36 ... Synchronous control data request (DREQ) signal transmission line 37 ... Synchronous control data transmission end (DACK) signal transmission line 40 ... Synchronous address space 41 ... Pipeline Address space 42 ... Interface address space 50-52 ... Second computer 2 in the second embodiment
Register

Claims (6)

[Claims] 1. In a computer network in which a plurality of computers are connected to each other and information is transmitted and received between the computers, information of different characteristics is transmitted and received by the synchronous communication method and the asynchronous communication method of the computers, and A data communication method characterized by selecting a communication method for transmission, transmitting and receiving information via independent paths, and sharing the information transmission path by both procedures, depending on the nature. 2. The data communication method according to claim 1, wherein the information having different properties includes at least information data and processor control data, and a pipeline control method is used for transmitting and receiving the information data. .. 3. The data communication method according to claim 2, wherein one computer sends information to another computer when reading information of communication in the pipeline control system. Method. 4. A computer network in which a plurality of computers are connected to each other and information is transmitted and received between the computers, has synchronous communication control means and asynchronous communication control means corresponding to respective control transmission paths, and an information transmission path. Has means for temporarily storing information and sequentially sending the information, and means for bypassing the means at least in response to the control of the synchronous communication control means. The information transmission path and the reception path are provided independently and shared by each of the above means. Then, the data communication device is characterized in that the synchronous communication control means and the asynchronous communication control means control the means for temporarily storing the information and sequentially sending the information. 5. The data communication apparatus according to claim 4, wherein the information having different properties includes at least information data and processor control data, and pipeline control means is provided as communication control means for the information data. Communication device. 6. The data communication device according to claim 5, wherein when one computer temporarily stores the information and reads the information by means for sequentially transmitting the information, a means for transmitting the information to another computer is provided. A data communication device characterized by having.