JP2003223428A - Data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance the processing speed of a data transfer device having a plurality of data processing circuits. <P>SOLUTION: The first to n-th data processing circuits 40-1 to 40-n perform predetermined processes on data received. First to n-th storage circuits 41-1 to 41-n are connected to the first to n-th data processing circuits 40-1 to 40-n, respectively, to store the data supplied from the data processing circuits. First to n-th access circuits 42-1 to 42-n carry out processes for letting the first to n-th data processing circuits 40-1 to 40-n access the other storage circuits. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device, and more particularly to a data transfer device that executes a data transfer process.

[0002]

2. Description of the Related Art In the field requiring digital signal processing, there are many examples of using a high-speed digital signal processor, and the processing is becoming faster and more complicated.

In recent years, the speed of digital signal processors has increased, and the demand for multitask processing by one processor has increased. However, the speed of the external bus has not made much progress as that of the processor, and the external interface has become a bottleneck. However, in the processing in which a large amount of data is accessed, the capacity of the processor is restricted.

On the other hand, in the processing by a single processor,
The power of the processor is devoted to task management, forcing inefficient programming such as interrupts. Therefore, multi-processing in which processing is executed in parallel by a plurality of processors is effective.

FIG. 9 is a diagram showing an example of the configuration of a conventional data transfer device using multiprocessing. This example
An external I / F (Interface) 10, an external memory 11, external memories I / F 12 to 14, digital signal processor cores 15 to 17, a local bus 18, and HOLD control signal lines 19 to 21 are included.

The external I / F 10 is an external ATM.
When the data is exchanged with the device or the CPU, the format of the data is converted. The external memory 11 temporarily stores data and the like to be processed when the digital signal processor cores 15 to 17 execute processing.

The external memory I / Fs 12 to 14 are interfaces for accessing the external memory 11. The digital signal processor cores 15 to 17 perform predetermined arithmetic processing on digital data.

The local bus 18 is a local bus for connecting the external I / F 10, the external memory 11, and the external memories I / F 12 to 14 to each other and enabling data exchange between them.

The HOLD control signal lines 19 to 21 are HOLD.
It is a signal line for performing D control. Next, the operation of the above conventional example will be described.

When data to be processed is input via the external I / F 10, this data is transferred to the external memory 1 for example.
1 is temporarily stored. The digital signal processor cores 15 to 17 access the external memory 11 in a predetermined order and acquire data to be processed. Then, after performing a predetermined process according to the type of acquired data,
The data of the processing result is stored again in the external memory 11.

At this time, HOLD control signal lines 19 to 21
If any of the digital signal processor cores 15 to 17 is accessing the external memory 11,
A signal for suppressing access by another digital signal processor core is output. As a result, the local bus 18 with multiple digital signal processor cores
Access can be controlled so that it does not conflict.

With the above operation, data can be processed by a plurality of digital signal processor cores, so that compared with the case where a single processor is used,
It becomes possible to execute the processing at high speed.

FIG. 10 is a diagram showing another configuration example. FIG. 9 shows an example of the case where the digital signal processor cores 15 to 17 have an equal relationship, while FIG. 10 shows an example of the case where a single processor is the main and the others are dependent on the main processor. is there.

In this example, the external I / F 30 and the external memory 3 are used.
1, an external memory I / F 32, a digital signal processor core 33, a coprocessor controller 34, and digital signal processor cores 35 and 36.

The external I / F 30 is an external ATM.
When the data is exchanged with the device or the CPU, the format of the data is converted. The external memory 31 temporarily stores data and the like to be processed when the digital signal processor cores 33, 35 and 36 execute processing.

The external memory I / F 32 is the external memory 31.
This is the interface for accessing. The digital signal processor cores 33, 35, 36 perform predetermined arithmetic processing on digital data.

The local bus 37 is a local bus for connecting the external I / F 30, the external memory 31, and the external memory I / F 32 to each other, and enabling data transfer between them.

Next, the operation of the above conventional example will be described. When data to be processed is input via the external I / F 30, this data is temporarily stored in the external memory 31, for example.

Digital signal processor core 33
Accesses the external memory 31 via the external memory I / F 32 and acquires the data to be processed. Then, the data is processed according to the type of the acquired data, and at that time, a part of the processing is performed by the digital signal processor core 3
5 and 36 will be shared appropriately.

At this time, the coprocessor controller 34 takes charge of control of data transfer to the digital signal processor cores 35 and 36. Then, the digital signal processor core 35,
When the processing by 36 is completed, the digital signal processor core 33 synthesizes these processing results and stores the data of the processing results in, for example, the external memory 31 to prepare for the next processing.

By the above operation, the data can be processed by the plurality of digital signal processor cores 33, 35 and 36, so that the processing can be executed at a higher speed than in the case where a single processor is used. It will be possible.

[0022]

However, in the case of the method shown in FIG. 9, each digital signal processor core holds data therein, and when the processing is completed by only a single processor, independent parallel processing is performed. Since the processing can be realized, the processing can be speeded up. However, when processing the data on the local bus 18, the access to the data is limited to only one processor, and the other processors are in the standby state. Therefore, there is a problem that processing delay occurs.

Further, in the case of performing sequential processing on data, there may be a case where the result of another processor processing has to be waited, and there is a problem that the efficiency of the system is not improved.

Further, in the method shown in FIG. 10, the digital signal processor core 33 needs to wait until the processing assigned to the digital signal processor cores 35 and 36 is completed. Further, even in the case of multi-task processing, one task cannot be entirely transferred to the digital signal processor cores 35 and 36, so that the load is concentrated on the digital signal processor core 33 and the processing efficiency is not necessarily improved. There was a point.

Further, when the digital signal processor core 33 exchanges data with the digital signal processor cores 35 and 36, the bus of the digital signal processor core 33 is used, so that the bus congestion occurs and the processing speed is sufficiently high. There is also a problem that the number of dependent processors that can be connected is limited as well as not improving.

The present invention has been made in view of the above circumstances, and an object thereof is to improve the processing speed of a data transfer apparatus having a plurality of digital signal processors.

[0027]

In order to solve the above problems, the present invention provides a data transfer apparatus for executing a data transfer process, as shown in FIG. 1, which performs a predetermined process on received data. To nth (n ≧ 2) data processing circuits 40-1 to 40-n and the first to nth data processing circuits 40-1 to 40-n, respectively, and supplied from each data processing circuit The first to n-th storage circuits 41-1 to 41-n for storing the stored data and the first to n-th data processing circuits 40-1 to 40-n to access other storage circuits. And a first to n-th access circuit 42-1 to 42-n for executing the processing of 1.

Here, the first to nth data processing circuits 4
0-1 to 40-n perform a predetermined process on the received data. First to nth memory circuits 41-1 to 41-n
Are the first to n-th data processing circuits 40-1 to 40-n.
And stores the data supplied from each data processing circuit. First to nth access circuits 42
-1 to 42-n are first to n-th data processing circuits 40
-1 to 40-n execute processing for accessing other memory circuits.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram for explaining the operation principle of the embodiment of the present invention. As shown in this figure,
The data transfer device according to the present invention comprises a first data processing circuit 40.
-1 to nth data processing circuit 40-n, first memory circuit 41-1 to nth memory circuit 41-n, and first access circuit 42-1 to nth access circuit 42-n Has been done.

Here, the first data processing circuits 40-1 to 40-1
The nth data processing circuit 40-n is configured by, for example, a digital signal processor, and performs a predetermined process on the received data.

The first memory circuit 41-1 to the n-th memory circuit 41-n are connected to the first data processing circuit 40-1 to the n-th data processing circuit 40-n, respectively. Stores data supplied by the circuit.

The first access circuit 42-1 to the n-th access circuit 42-n are the first data processing circuits 40-1 to 40-1.
The nth data processing circuit 40-n executes processing for accessing another storage circuit.

Note that the first data processing circuit 40-1 to the n-th data processing circuit 40-n each have a predetermined process to be shared, and data corresponding to the shared content is transmitted from another data processing circuit. Receive and perform data processing.

Next, the operation of the above principle diagram will be described. As an example, a case where data is input from the first data processing circuit 40-1 and output from the nth data processing circuit 40-n will be described.

When the data is input, the first data processing circuit 40-1 performs a predetermined process according to the type of the input data, for example. Then, the first data processing circuit 40-1 determines whether or not further processing is necessary, and if it is determined that the processing is necessary, the first data processing circuit 40-1 is connected to the data processing circuit corresponding to the processing. The circuit is supplied via the first access circuit 42-1.

For example, when it is determined that the processing by the second data processing circuit 40-2 is necessary, the first data processing circuit 40-1 passes through the first access circuit 42-1. The data and the processing instruction indicating the processing content of the data are stored in a predetermined area of the second memory circuit 41-2.

The first data processing circuit 40-1 is
As soon as the data processing is completed, the process moves to the next data processing, and the input data is processed one after another. The second data processing circuit 40-2 reads the data and the instruction stored in the second storage circuit 41-2 in a predetermined order,
To process. When the read data requires further processing, the data is supplied to the storage circuit connected to the corresponding data processing circuit via the second access circuit 42-2.

Similarly, the second data processing circuit 40-2 also has
As soon as the data processing is completed, the process moves to the next data processing, and the received data is processed one after another. The n-th data processing circuit 40-n, like other data processing circuits,
The data and instructions stored in the nth memory circuit 41-n are read out in a predetermined order, subjected to a predetermined process, and then output to the outside.

According to the above embodiment, the first data processing circuits 40-1 to 40-n can operate independently. In addition, when data is exchanged between the data processing circuits, bus congestion does not occur unlike in the case where data is transmitted via the bus. Therefore, each data processing circuit can perform the processing in parallel and can perform the processing independent of the other data processing circuits, so that the data processing efficiency can be improved.

Next, a more detailed operation principle of the present invention will be described. FIG. 2 is a principle diagram for explaining a more detailed operation principle of the present invention. As shown in this figure, according to the present invention, the external I / Fs 60a-60c and the external memories 61a-
61c, external memory I / Fs 62a to 62c, digital signal processor cores 63a to 63c, DPRAM
(Dual Port Random Access Memory) 64a to 64c,
It is configured by FIFO (First In First Out) 65a to 65c, local buses 66a to 66c and a bus 67.

Here, the external I / Fs 60a to 60c are for converting the representation format of the data when the data is exchanged with an external device (not shown).
It is composed of a D conversion circuit, a D / A conversion circuit, and the like. The external I / F 60a is connected to the ATM device and inputs data from the ATM device. Also, the external I / F 60b is connected to the upper CPU, and the CP
Input a control command from U. In addition, external I / F 60c
Is connected to an ATM device and outputs data to the ATM device.

The external memories 61a to 61c are memories that the digital signal processor cores 63a to 63c can exclusively access, and store data to be processed and the like.

The external memory I / Fs 62a to 62c are interfaces when the digital signal processor cores 63a to 63c access the external memories 61a to 61c, respectively.

Digital signal processor core 63a
.About.63c have a function of performing predetermined processing on digital data and processing the digital data at high speed in real time.

The DPRAMs 64a to 64c have a function of temporarily storing the data supplied from other digital signal processor cores. FIFO 65a to 65c
Has a function of temporarily storing an instruction supplied from another digital signal processor core.

As will be described later, the FIFO 65a ...
Instructions stored in 65c and DPRAM6
Since the data stored in each of 4a to 64c are associated with each other, it is possible to easily determine which data corresponds to which instruction.

The bus 67 connects each of the DPRAMs 64a to 64c and each of the FIFOs 65a to 65c to each other, and enables data exchange between them. Next, referring to FIG. 3, a method of storing data by the external memories 61a to 61c and the DPRAMs 64a to 64c will be described. Although only the portion related to the digital signal processor core 63a is shown in this figure, other digital signal processor cores 63b, 6
Since 3c has the same configuration, its description is omitted.

The external memory 61a has an individual data area 61a-1 for storing individual data and a common data area 61a-2 for storing common data. Here, the individual data is, for example, data such as payload, which each digital signal processor core has individually. Further, the common data is, for example, data such as a VC (Virtual Channel) number and control information that each digital signal processor core has in common.

The DPRAM 64a has a common data area 64a-1 for storing common data and a transfer data area 64a-2 for storing transfer data. Here, the common data refers to a part of the above-mentioned common data that is frequently used.

Processing instructions are stored in the FIFO 65a. FIG. 4 is a diagram showing a detailed configuration example of the DPRAM 64a. As shown in this figure, the DPRAM 64a
The common data area 64a-1 can store m pieces of data. In these areas, the external memory 61
Of the common data stored in a to 61c, frequently used data is selected and stored.

The transfer data area 64a-2 has n
Individual data can be stored in this area, so to speak, when transferring data to the external memories 61a to 61c,
This area is used as a buffer.

FIG. 5 is a diagram showing a detailed configuration example of the FIFO 65a. As shown in this figure, m processing instructions corresponding to the common data shown in FIG. 4 are stored. Also,
N transfer instructions corresponding to the transfer data shown in FIG. 4 are stored.

It should be noted that the transfer data and the transfer instruction and the common data and the processing instruction are in one-to-one correspondence with each other, and when a predetermined data is designated, the corresponding processing instruction or transfer instruction is specified. Has become.

Next, the operation of the above principle diagram will be described. In the following, the external I / F 60a inputs data from the ATM device, the external I / F 60b is connected to a higher CPU, and the external I / F 60c is further connected.
Will be described as outputting data to the ATM device.

First, when data is input via the external I / F 60a, individual data is stored in the individual data area 61a, and common data is stored in the common data area 61a-2. It is also possible to directly transfer to the digital signal processor core without storing it in the external memory 61a.

Digital signal processor core 63a
Is connected to the external memory 61a via the external memory I / F 62a.
To obtain frequently used data from the data stored in the common data area 61a-2 and store it in the common data area 64a-1.
Writing is also performed to a common data area (not shown) of the DPRAM 64b and DPRAM 64c connected to another digital signal processor core. Also, FI
For the FO 65a, the FIFO 65b, and the FIFO 65c (not shown), a processing instruction indicating that the common data has been updated is written in the corresponding area.
As a result, the common data, which is frequently used, is held in the respective common data areas of the DPRAMs 64a, 64b, 64c.

The digital signal processor core 63a has a common data area 61a of the external memory 61a.
-2 among the common data stored in the DPRAM 6
Those not stored in 4a are transferred to other external memories 61b and 61c via the transfer data area. That is, the digital signal processor core 63
a acquires data not stored in the common data area 64a-1 of the DPRAM 64a out of the data stored in the external memory 61a, writes it in the transfer data area of the DPRAM 64b and DPRAM 64c, and stores it in the FIFO 65b and the FIFO 65c, respectively. On the other hand, a transfer instruction including a destination address, a source address, etc. is written.

Then, the digital signal processor core 63b and the digital signal processor core 63 are
c stores common data based on the transfer instructions stored in the FIFO 65b and the FIFO 65c, and stores the common data in the external memory 6
1b and the corresponding area of the external memory 61c, respectively.

As a result, common data that is not frequently used is stored in the common data areas of the external memories 61a to 61c. Here, the amount of data stored in the common data area of the DPRAMs 64a to 64c is the same as that of the external memories 61a to 61c.
Since the number is smaller than that of c, the digital signal processor cores 63a to 63c can easily retrieve target data.

Since the same processing is also executed by the digital signal processor cores 63b and 63c, these digital signal processor cores 63
For common data generated by b and 63c,
It will be shared throughout the system.

On the other hand, the data stored in the individual data area 61a-1 of the external memory 61a is processed by the digital signal processor core 63a as necessary, and then further processed by another digital signal processor core. Is required, the DPR connected to the corresponding digital signal processor core
Data is written in the transfer data area of AM, and an instruction indicating the processing content for the data is written in the FIFO 65a as a transfer instruction.

For example, when it is determined that further processing by the digital signal processor core 63b is necessary, the data is written in the transfer data area of the DPRAM 64b and the transfer instruction is written in the FIFO 65b. Then, the digital signal processor core 63
First, b reads the transfer instruction stored in the FIFO 65b to specify the content of the process, acquires the corresponding data from the transfer data area, and applies the necessary process to the acquired data.

Such processing is also executed in the digital signal processor core 63c, and the data which has been processed and which has to be sent to the outside is output to the ATM device through the external I / F 60c. Will be done.

As described above, according to the present invention,
Since the data is shared by using the common data area of the DPRAMs 64a to 64c and the common data area of the external memories 61a to 61c, the plurality of digital signal processor cores are parallel to each other while maintaining the consistency of processing through the common data. Then, it becomes possible to execute the processing.

Further, since some common data which is frequently used is stored in the common data area of the DPRAMs 64a to 64c, it is necessary for the digital signal processor cores 63a to 63c to retrieve the target data. It becomes possible to shorten the time and improve the processing speed of the entire apparatus.

Regarding the processing instruction, the FIFO 65a
Since the data is transferred to another digital signal processor core through ~ 65c, it becomes easy to manage the order in which the processing commands are received. On the other hand, regarding the data, D
Since the data is transferred to another digital signal processor core through the PRAMs 64a to 64c, it is possible to flexibly transfer data having different sizes.

Regarding the correspondence between the processing instruction and the data, the areas of the DPRAMs 64a to 64c and the FIFO
Since the areas 65a to 65c have a one-to-one correspondence, it becomes possible to easily specify the data corresponding to a predetermined processing instruction.

Data to be processed by the digital signal processor cores 63a to 63c are external memories 61a to 6 which can be exclusively and exclusively accessed.
Since the data is stored in each 1c, it is possible to prevent a delay in data processing due to bus congestion or the like.

Next, a first embodiment of the present invention will be described. FIG. 6 is a diagram showing a configuration example of the first exemplary embodiment of the present invention. As shown in this figure, in the first embodiment of the present invention, external I / Fs 80a to 80c, external memories 81a to 81c, local buses 82a to 82c, and a DSP are used.
(Digital Signal Processor) cores 83a to 83c, L
B (Local Bus) I / F 84a to 84c, FIFO85
a-85c, DPRAM 86a-86c, DPRAM
I / F 87a to 87c, FIFO I / F 88a to 88
c and a bus 89.

Here, the external I / Fs 80a to 80c convert the representation format of the data when exchanging the data with the device connected to the outside. In addition, external I / F 80a
Is connected to an ATM device and inputs data from the ATM device. The external I / F 80b is connected to an upper CPU and exchanges data with the CPU. External I
The / F80c is connected to the ATM device and outputs data to the ATM device.

The external memories 81a to 81c are connected to the local buses 82a to 82c, respectively, and store the data to be processed by the DSP cores 83a to 83c, respectively.

The LB I / Fs 84a to 84c are interfaces for the DSP cores 83a to 83c to access the external memories 81a to 81c or the external I / Fs 80a to 80c, respectively.

The DSP cores 83a to 83c perform predetermined processing on the data stored in the external memories 81a to 81c, respectively. The FIFOs 85a to 85c are DS
Processing instructions for data supplied to the P cores 83a to 83c are stored.

The data supplied to the DSP cores 83a to 83c are stored in the DPRAMs 86a to 86c. DPRAM I / F 87a to 87c are other DPRs.
This is an interface for accessing the AM.

The FIFO I / Fs 88a to 88c are interfaces for accessing other FIFOs. The bus 89 is a DPRAM I / F 87a to 87c.
And the DPRAMs 86a to 86c are connected to each other, and the FIFO I / Fs 88a to 88c and the FIFO 85 are connected.
a to 85c are respectively connected.

LB I / Fs 84a to 84c, DS
P83a to 83c, FIFO 85a to 85c, DPRA
M86a-86c, DPRAM I / F 87a-87c
And the FIFO I / Fs 88a to 88c are FPGAs.
(Field Programmable Gate Array).

Further, in relation to the principle diagram shown in FIG. 2, the external I / Fs 80a to 80c are the external I / Fs 60a to 60c.
In addition, the external memories 81a to 81c are the same as the external memories 61a to 61c.
61c, local buses 82a-82c, local buses 66a-66c, LBI / F84a-84c, external memory I / Fs 62a-62c, DSP core 83a-.
83c is a digital signal processor core 63a-
63c, FIFO 85a-85c, FIFO 65a
To 65c, DPRAMs 86a to 86c are DPRAMs.
64a to 64c and the bus 89 correspond to the bus 67, respectively.

The external memories 81a to 81c and the FIF
O85a-85c and DPRAM86a-86c
Are divided and used as in the case shown in FIGS.

Next, the operation of the above embodiment will be briefly described. Data input from the ATM device via the external I / F 80a is stored in the external memory 81a. Here, as in the case shown in FIG. 3, common data is stored in the common data area, and individual data is stored in the individual data area.

Among the common data stored in the external memory 81a in this way, the DSP core 83a stores frequently used data in the common data area of the DPRAM 86a, and the DPRAM I / F.
The data is transferred to the common data area of the DPRAMs 86b and 86c via 87a.

For the common data that is used less frequently, the DSP core 83a uses DPRAM I /
Write the transfer instruction including the source address and the destination address to the transfer data area of the DPRAMs 86b and 86c via the F87a,
Write to IFO 85b, 85c. As a result, D
The SP core 83b and the DSP core 83c are DPRAMs.
The common data written in 86b is stored in the external memory 8
Transfer to the corresponding area of 1b and 81c. As a result, common data can be shared.

The above processing is performed by the DSP core 8
Since 3b and 83c are executed in the same manner, the common data is shared by the entire system.
On the other hand, regarding the individual data, the DSP core 83a reads the external data from the external memory 81a, performs necessary processing, and when further processing is required, the DPRAM I / F 87 is used.
DPR connected to the corresponding DSP core via a
At the same time as writing to the transfer data area of the AM, the processing instruction is written to the corresponding FIFO via the FIFO I / F 88a.

For example, when it is determined that the processing by the DSP core 83b is necessary, the data is stored in the DPRAM 8
6b, and processing instructions are written to the FIFO 85b. Then, the DSP core 83b first
The processing command written in the IFO 85b is acquired, the data corresponding to the command is acquired from the DPRAM 86b, and the corresponding process is performed. Then, it is determined whether or not further processing is necessary, and if further processing is necessary, the data is transferred to another DSP core.

According to the above processing, as in the case shown in FIG. 2, since the common data area of the DPRAMs 84a to 84c and the common data area of the external memories 81a to 81c are used to share the data, the common data is shared. It becomes possible for a plurality of digital signal processor cores to execute the processing in parallel while maintaining the consistency of the processing through the media.

Since some common data that is frequently used is stored in the common data area of the DPRAMs 84a to 84c, the DSP cores 83a to 83 are used.
It is possible to shorten the time required for the c to retrieve the target data and improve the processing speed of the entire apparatus.

As for the processing instruction, FIFO I /
Since the data is transferred to another digital signal processor core through the F88a to 88c and the FIFOs 85a to 85c, it becomes easy to manage the order in which the processing instructions are received. On the other hand, for data, DPRAM I /
Since data is transferred to another digital signal processor core through the F87a to 87c and the DPRAMs 86a to 86c, it is possible to flexibly transfer data of different sizes.

Regarding the correspondence between the processing instruction and the data, the areas of the DPRAMs 86a to 86c and the FIFO
Since the areas 85a to 85c have a one-to-one correspondence, it becomes possible to easily specify the data corresponding to the predetermined processing instruction.

Since the data to be processed by the DSP cores 83a to 83c are stored in the external memories 81a to 81c that can be accessed exclusively and exclusively, delays in data processing due to bus congestion or the like. Can be prevented.

Next, a second embodiment of the present invention will be described. FIG. 7 is a diagram showing a configuration example of the second exemplary embodiment of the present invention. As shown in this figure, the second embodiment of the present invention includes DSPs 101 to 103 and a DPRAM 10.
4 to 106, FIFO 107 to 109, buffer 111
~ 113, UTOPIA (Universal Test & Operation
s PHY Interface for ATM) I / F 114, 115, memories 116 to 118, interface 120, CPU
121 and a DSP I / F 122.

Here, the DSPs 101 to 103 perform various processes on digital data. DPRAM10
Data is written in Nos. 4 to 106 when the DSPs 101 to 103 transfer data to other DSPs.

The FIFOs 107 to 109 are the DSP 101.
A processing instruction is written when the ˜103 transfers data to another DSP. The buffers 111 to 113 are D
When loading the program executed by the SP 101 to 103, the program is temporarily stored.

The UTOPIA I / Fs 114 and 115 are
It is an interface for transferring data between the ATM layer and the physical layer defined by the ATM forum. The memories 116 to 118 are external memories of the DSPs 101 to 103.

The interface 120 is composed of a PCI bridge 120a and a FIFO 120b,
It is an interface for exchanging data between the CPU 121 and the DSP 102.

The CPU 121 controls the entire apparatus. Further, the DSP I / F 122 is an interface with an ATM device (not shown), and
This is an interface for loading a program to be executed by 103.

The DSP 101, DPRAM 104,
A part of 105 and a part of the FIFOs 107 and 108 form one block. In addition, DSP10
2. Part of DPRAM 105, 106 and FIF
A part of O108 and 109 constitutes one block. Furthermore, DSP 103, DPRAM 104, 106
And part of the FIFOs 107 and 109 are 1
Make up one block.

Further, in this embodiment, the memories 116 to
118, DPRAMs 104-106 and FIFO 10
7 to 109 are used in the same manner as in the case shown in FIGS. 3 to 5.

Next, the operation of the above embodiment will be briefly described. When the device is started, DSP I / F1
The programs executed by the DSPs 101 to 103 are input via 22 and stored in the memories 116 to 118, respectively.

When the storage of the program is completed, the DSP
The I / F 122 inputs data from an external ATM device, and the memory 117 via the UTOPIA I / F 115.
Store in the common data area or individual data area of. The common data area and the individual data area are the same as in the case of FIG.

Subsequently, in the DSP 101, among the data stored in the common data area of the memory 117, the frequently used data are DPRAMs 104 and 105.
In the common data area of the DPRAM1
04 or DPRAM105 to DPRAM106
It is also written in the common data area of.

In this way, among the common data, the ones which are frequently used are DPRAMs 104 to 106.
It is stored and shared in the common data area of. Next, of the data stored in the common data area of the memory 117, the one that is used less frequently is the DSP 101.
Writes into the transfer data areas of the DPRAMs 104 and 105, and also writes transfer instructions into the corresponding areas of the FIFOs 107 and 108.

As a result, the DSPs 102 and 103 have the FIF.
The transfer command written in the O107, 108 is read, the data stored in the DPRAM 104, 105 is read according to the transfer command, and the memory 116, 1 is read.
Store in 18 designated areas.

Such processing is performed by the DSP 102 and D
Since it is also executed independently by SP103, DPRAM1 is used for common data that is frequently used.
The common data areas 04 to 106, and those not frequently used, are stored and shared in the common data areas of the memories 116 to 118.

On the other hand, when the individual data is processed by each DSP and then needs to be processed by another DSP, it is written in the transfer data area of the DPRAMs 104 to 106, and is written in the corresponding area of the FIFOs 107 to 109. By writing the transfer command, the processing designated by each DSP is executed.

In this embodiment, the DSP 102
Mainly exchanges commands with the CPU 121, decodes the commands, adjusts scheduling for other DSPs, and processes such as command violations.

The DSP 101 mainly performs processing of input data, notification, transmission request to the transmitting side, data loopback request, and received data management. Also, DSP
Reference numeral 103 mainly performs a transmission process, a return process from reception, a consistency management of received data, and the like.

Note that each DSP performs processing independently.
Further, the DSP 101 and the DSP 103 can also perform an operation of making independent judgments depending on the input data from the ATM device, discarding the data if necessary, and notifying the CPU 121 only.

Further, the instructions and data are stored in the FIFO 10
7 to 109 and DPRAMs 104 to 106, respectively, but if the DSP in charge of the corresponding processing cannot take over the processing, the instruction insertion can be stopped by the "FIFO-FULL" status.

According to the above embodiments, the result processed by each DSP is UTOP via each local bus.
It is possible to output directly to IA and PCI, and it is possible to greatly reduce the bus occupation time. Further, even while the output is being executed, each DSP can continue other processing to improve the overall processing efficiency.

Further, according to the above embodiments, it is possible to configure the device using a DSP that is normally used. If it is configured using a programmable gate array, the cost of the device will be reduced and
It is possible to reduce the mounting area.

In addition, the FIFOs 107-109 and DP
By limiting the use of the RAMs 104 to 106 only for transfer, it is possible to reduce the size of these.
Next, an operation for efficiently transferring a processing instruction according to the present invention will be described.

FIG. 8 is a signal flow chart for explaining the operation for efficiently transferring the processing instruction according to the present invention. In this example, a case where processing instructions and data are exchanged between the DSP #a and the DSP #b is shown. Here, the DSP # a is, for example, the digital signal processor core 63a, and the DSP # a
b corresponds to the digital signal processor core 63b, and DPRAM # a and FIFO # a are DP
It corresponds to the RAM 64a and the FIFO 65a, respectively.

The conversion table is stored in the external memory 61a.
And the external memory 61b. First, the DSP #a executes the processing A and the processing B, while the DSP #b executes the processing A and the processing B.

In this state, when a request for process C, process D, or process E is input from the CPU, DSP # a
Refers to the conversion table and processes C to E are all D
It is specified that the process should be processed by SP # b, and
It is specified to collectively handle these processes as process α. At this time, in DSP #b, W
AIT is executed, and a response of no request is made from the FIFO #b, and processing C, processing D, and processing E are executed.

In order for the DSP #b to execute the process α, the DSP #a first generates the data of the process α, and then the process α
As data, DPRAM # b via DPRAM # a
Transfer to. In parallel with this, a request for executing the process α is issued to the FIFO # b via the FIFO # a.

After executing the WAIT processing, the DSP #b acquires the execution request of the processing α stored in the FIFO #b, refers to the conversion table, and the processing α executes the processing C, the processing D, and the processing E. Identify what is configured.

Then, the DSP #b processes C, D,
Process α-1, process α-2, process α-3 corresponding to process E
When all of these processes are completed, FIFO #
A completion notification is transmitted to FIFO # a via b. Then, processing F and processing G are executed.

At this time, in DSP #a, after the processes F and G are executed, the WAIT process is executed,
Process H, process I, and process J are executed. And WAI
When the completion notification is received from the FIFO #a after the T processing is executed again, the DSP #a executes the completion processing. As a result, the fact that processing C, processing D, and processing E have been completed
The process K is newly executed after the response notified to the.

As described above, by constructing a command (process α request) designating a plurality of processes and exchanging this command between DSPs, it is possible to collectively request a plurality of processes at once. Therefore, the number of times of exchanging data between DSPs can be reduced and the processing speed of the entire device can be improved.

The configuration examples shown in the above embodiments are as follows.
It is needless to say that the present invention is not limited to such a configuration, which is merely an example. Further, in the above-described embodiments, the case where the number of DSP cores or DSPs is three has been described as an example, but it goes without saying that the present invention can be applied to the case where the number of DSP cores or DSPs is four or more.

Further, in the above embodiments, the processing is shared among the DSPs so that they do not overlap each other.
The same processing is shared by multiple DSPs, and each DS
It is also possible to distribute the processing according to the load on P.

(Supplementary Note 1) In a data transfer device for executing a data transfer process, first to n-th (n ≧ 2) data processing circuits for performing a predetermined process on received data, and the first to nth data processing circuits. First to nth memory circuits connected to each of the nth data processing circuits and storing data supplied from the respective data processing circuits, and the first to nth data processing circuits are other memory circuits. A first to nth access circuit that executes a process for accessing the data transfer device.

(Supplementary Note 2) The first to n-th data processing circuits pass data to be processed by other data processing circuits through the first to n-th access circuits and perform parallel processing. Note 1 characterized in that
The described data transfer device.

(Supplementary Note 3) Each of the first to n-th data processing circuits has a first to n-th memory that can be accessed exclusively and exclusively. 2. The data transfer device according to appendix 1, wherein processing is executed using a memory.

(Supplementary Note 4) Each of the first to nth storage circuits has a dual port memory and a FIFO. The dual port memory stores data to be processed, and the FIFO has: The data transfer apparatus according to appendix 1, wherein a processing instruction indicating processing content is stored.

(Supplementary note 5) The data transfer apparatus according to supplementary note 4, wherein the instruction group stored in the FIFO and the area of the dual port memory are associated with each other in a one-to-one correspondence.

(Supplementary note 6) The data transfer apparatus according to supplementary note 4, wherein the processing instruction can specify a plurality of processes by one code.

[0127]

As described above, according to the present invention, in the data transfer device for executing the data transfer process, the first to n-th (n ≧ n) which performs the predetermined process on the received data.
2) a data processing circuit, and a first to nth storage circuit connected to each of the first to nth data processing circuits and storing data supplied from each data processing circuit,
Since the first to n-th data processing circuits are provided with the first to n-th access circuits that execute processing for accessing other storage circuits, the data processing circuits are operated independently. Is easily possible, and
The access to the external bus can be performed without being restricted by each data processing circuit. Also,
The configuration can also be simplified, and synchronization confirmation processing between each data processing circuit becomes unnecessary, and the processing efficiency can be greatly improved. Furthermore, connection can be easily performed, and development efficiency can be improved in software construction by a single memory configuration. Further, even when data is input / output to / from the outside, each data processing circuit can perform the processing independently, so that the processing delay due to the occupation of the bus can be reduced and the processing efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a principle diagram for explaining an operation principle of the present invention.

FIG. 2 is a principle diagram for explaining a more detailed operation principle of the present invention.

FIG. 3 shows an external memory, DPRAM, FIF shown in FIG.
It is a figure for demonstrating the aspect of the data stored in O.

FIG. 4 is a diagram for explaining a more detailed aspect of data stored in the DPRAM shown in FIG.

5 is a diagram for explaining a more detailed aspect of data stored in the FIFO shown in FIG. 2. FIG.

FIG. 6 is a diagram showing a configuration example of a first exemplary embodiment of the present invention.

FIG. 7 is a diagram showing a configuration example of a second exemplary embodiment of the present invention.

FIG. 8 is a signal flowchart illustrating an operation for efficiently transferring a processing instruction according to the present invention.

FIG. 9 is a diagram showing a configuration example of a conventional data transfer device by multiprocessing.

FIG. 10 is a diagram showing another configuration example of a conventional data transfer device by multiprocessing.

[Explanation of symbols]

10 External I / F 11 External Memory 12-14 External Memory I / F 15-17 Digital Signal Processor Core 18 Local Bus 19-21 HOLD Control Signal Line 30 External I / F 31 External Memory 32 External Memory I / F 33 Digital Signal Processor core 34 Coprocessor controller 35, 36 Digital signal processor core 40-1 to 40-n First data processing circuit to nth data processing circuit 41-1 to 41-n First storage circuit to nth storage Circuits 42-1 to 42-n First access circuit to nth access circuit 60a to 60c External I / F 61a to 61c External memory 62a to 62c External memory I / F 63a to 63c Digital signal processor core 64a to 64c DPRAM 65a-65c FIFO 67 Bus 80a-8 0c External I / F 81a to 81c External memory 82a to 82c Local bus 83a to 83c DSP core 84a to 84c LB I / F 85a to 85c FIFO 86a to 86c DPRAM 87a to 87c DPRAM I / F 88a to 88c FIFO I / F 89 Bus 101-103 DSP 104-106 DPRAM 107-109 FIFO 111-113 Buffer 114,115 UTOPIA I / F 116-118 Memory 120 Interface 120a PCI bridge 120b FIFO 121 CPU

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Toshiyuki Yokosaka             Hokkaido Kita-ku Kita-Shichijo Nishi 4-chome 3-1, 1               Fujitsu East Japan Digital Technology Co., Ltd.             Inside the company (72) Inventor Hiroshi Yuki             Hokkaido Kita-ku Kita-Shichijo Nishi 4-chome 3-1, 1               Fujitsu East Japan Digital Technology Co., Ltd.             Inside the company (72) Inventor Fuyuki Oshima             Hokkaido Kita-ku Kita-Shichijo Nishi 4-chome 3-1, 1               Fujitsu East Japan Digital Technology Co., Ltd.             Inside the company (72) Inventor Daitaro Furuta             Hokkaido Kita-ku Kita-Shichijo Nishi 4-chome 3-1, 1               Fujitsu East Japan Digital Technology Co., Ltd.             Inside the company (72) Inventor Ken Yonekura             Hokkaido Kita-ku Kita-Shichijo Nishi 4-chome 3-1, 1               Fujitsu East Japan Digital Technology Co., Ltd.             Inside the company (72) Inventor Kenichi Saito             Hokkaido Kita-ku Kita-Shichijo Nishi 4-chome 3-1, 1               Fujitsu East Japan Digital Technology Co., Ltd.             Inside the company F term (reference) 5B045 BB12 BB35 GG11                 5B077 BA02 DD00 DD02 DD07

Claims (5)

[Claims] 1. A data transfer apparatus for executing a data transfer process, wherein first to nth processes are performed for a predetermined process on received data.
(N ≧ 2) data processing circuits, first to n-th storage circuits connected to the first to n-th data processing circuits and storing data supplied from the respective data processing circuits, A data transfer device, wherein the first to n-th data processing circuits include first to n-th access circuits that execute a process for accessing another storage circuit. 2. The first to n-th data processing circuits,
Data to be processed by other data processing circuits,
The data transfer apparatus according to claim 1, wherein the data transfer is performed via the first to nth access circuits to realize parallel processing. 3. The first to n-th data processing circuits,
The data according to claim 1, wherein each of the first to nth memories that can be exclusively and exclusively accessed has its own memory, and the processing is executed using the memory for the data shared by itself. Transfer device. 4. The first to n-th storage circuits have a dual port memory and a FIFO, the dual port memory stores data to be processed, and the FIFO has a processing content. The data transfer device according to claim 1, further comprising: 5. The data transfer apparatus according to claim 4, wherein the processing instruction can specify a plurality of processings by one code.