KR940003300B1 - Memory-queue in a system using pipe-line bus protocol - Google Patents

Abstract

The memory queue for pipeline bus protocol system as a buffer between the memory controller and the bus interface to store bus transmission request temporarily to send to the memory controller in time for efficient memory access. The memory queue comprises a memory array (10) for storing data, a memory controller (20) to control the memory array (10) which is connected to bus interface (40), and a buffer (30) which stores continuous transmission requests from the system bus, when the memory controller (20) can not process those requests, to transmit to the memory controller (20) when the memory controller (20) is ready.

Description

Memory queues on systems using the pipeline bus protocol

1 is a timing diagram of a bus protocol during a write cycle.

2 is a timing diagram of a bus protocol during a read cycle.

3 is a block diagram of a main memory device.

4 is a configuration diagram of a memory queue.

5 is a circuit diagram of a memory queue controller.

6 is a state transition diagram of a memory queue controller.

The present invention relates to the implementation of a memory queue for a system using a pipeline bus protocol.

The pipeline bus protocol divides the transmission operation into several stages and pipelines them in order to obtain high data transmission capability. This pipeline technique has the advantage of improving the transmission capacity of the bus, but the disadvantage is that the bus controller is complicated to ensure a high transmission capacity. In a system employing this pipeline technique, the memory access time for storing or fetching data into the memory is longer than the data transfer processing time of the pipeline bus. It is common to fall below the processing capacity, and thus a buffer means for temporarily storing the transfer request of the bus which is continuously transmitted to the memory controller is required.

An object of the present invention is to buffer the difference between the bus transfer processing speed and the memory access time, and when the memory controller fails to process a continuous transfer request of the bus, the memory controller temporarily stores the transfer request information of the bus and then processes it. When it is ready to do so, it provides a memory queue that forwards the transfer request information to the memory controller. Therefore, the memory queue, which is a buffer means of the present invention, is located between the memory controller and the number of bus inputs and transmits the information received by the bus interface directly or after a predetermined time to the memory controller.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 and 2 are timing diagrams of the HiPi-Bus transmission protocol.

FIG. 1 shows a write cycle and FIG. 2 shows a read cycle. Five steps of operation must be performed on the bus for one data transfer, and the other steps can be pipelined on the bus. All data transfer takes place between ReQuester (RQ) and ResPonder (RP).

Here, RQ corresponds to a central processing unit (cpu) or an input / output processing unit (I / O device), and RP corresponds to a main memory. In a system employing the pipeline technique, there may be a transfer request to the main memory every cycle, and the processing cycle in the main memory is twice as long as 1.5 times the bus cycle. (I.e., the processing speed of the main memory device is slower than the transfer speed of the bus.) The main memory device receives the bus information in the address period and translates it to determine whether it is selected. At this time, if the main memory can handle the transfer request, it sends out “ok” response signal, otherwise it sends out “busy” signal. When an error is detected or a locked address is approached, the main memory responds with an "error" and a "lock bysy" signal, respectively. When a snoop controller (not shown) attempts to cancel a transmission by a cache data homogeneity maintaining protocol, a "dirty" signal or a "snack" signal is displayed in a response period. Data transfers are only made when the response of the main memory is "ok" and there is no cancellation action by the Sonuf controller. In the case of write transfer, a response is sent to confirm error detection for the data. In the case of read transfer, the data is read from the memory and sent to the board requesting the data through mediation of the data bus.

3 illustrates a main memory device using a memory queue according to the present invention. The main memory device controls a memory array 10 for storing data and a memory array 10 to perform writing and reading operations of data. Memory controller 20 to perform, a bus interface unit 40 for exchanging information with the system bus, and a memory queue 30 connected between the memory controller 20 and the bus interface unit 40 do. It is most common to use a dynamic random access memory (DRAM) as the memory array 10 of the main memory device, and the memory controller 20 writes and reads data from the memory array 10. .

The memory controller 20 attempts to access the memory at the same time as the transfer protocol of the bus proceeds to return the data to the board requesting data as quickly as possible. All data access is terminated until the snoop controller requests to cancel the transfer, and only if the cancellation is not canceled, the data is finally written or the data is transferred. That is, the memory controller 20 operates by utilizing the characteristics of the pipeline bus as it is. The bus interface unit 40 is responsible for all information exchange with the bus and is responsible for transmitting the upper transmission request to the lower bus as opposed to receiving information from the bus and transferring the upper information.

The memory queue 30 is located between the bus interface unit 40 and the memory controller 40 to display information of the bus interface unit 40 having a relatively faster processing speed than the memory controller 40. It acts as a cushioning means in sending it.

The memory queue 30 of the present invention has no delay in sending a pipelined bus transfer request to the memory controller 20 and an interface such as no memory queue for the memory controller 20. to provide. That is, the buffer function as a queue is performed, but the queue does not require a complicated interface or a new delay time for the memory controller 20.

4 shows the structure of the memory queue 30. The memory queue 30 may include a storage unit 31 for temporarily storing address information and data information coming from a bus, and a controller 32 for managing information stored in the storage unit 31 by observing states of a memory controller and a bus. It consists of.

The storage unit 31 is implemented as a transparent latch (for example, 74F373) so that the delay time does not occur when storage is not required.

5 is a diagram illustrating the control queue 32 of the memory queue in more detail. The flip-flops 33 storing the state signals of the bus and the memory controller 20 maintain the temporal relationship with the state signals of the bus. And multiplexers 34 for sending, and a state machine 35 for controlling them overall.

The control unit 32 receives address bus information, data bus information, and status bus information from the bus interface unit 40, and stores the memory queue 30 through a signal “accept” from the memory controller 20. It can be seen whether the memory controller 20 has taken the information stored in the unit 31. In addition, the signals output from the memory queue 30 to the memory controller 20 are information received from the bus interface unit 40, which are appropriately modified according to the storage set point and the position point taken by the memory controller 20.

6 is a state transition diagram of the sequential logic circuit in the control unit 32 of the memory queue 30. In the "ready" state, the memory queue 30 operates in a transparent mode and operates in the same manner as the bus interface unit 40 and the memory controller 20 are directly connected. The operation of the memory queue 30 starts with receiving a transfer request from the bus interface unit 40. When the request of the bus interface unit 40 arrives while the memory controller 20 is able to process a transfer request, the memory controller 20 remains in the "ready" state and does not perform a separate operation. In this case, the bus interface unit 40 and the memory controller 20 may be connected as it is to transmit information without a delay time. The transition to the state of “storage 1” occurs when the memory controller 30 cannot process newly arrived request information. From this time, the memory queue 30 is connected to each step of the bus interface unit 40 and the memory controller ( Start to observe the state of 20).

Two transitions can occur in “storage 1”. The first is to go to the “ready” state. When a stored request is a write operation, a parity error is detected in the data to be written and the stored information is ignored. (WR & dpce) and when a request is sent to the memory controller. The second is a case of transition to the "storage 2" state. If the two events described above do not occur [! (WR & dpce: accept)], where! Represents NOT, & represents AND, and: represents OR, respectively.

There are two transitions in the “storage 2” state, where the transition to the “ready” state occurs when the snoop controller indicates that the bus ignores the transfer (cache) and the request is sent to the memory controller 20 ( accept). Otherwise [! (cache: accept)] transitions to the “storage 3” state, which stays in this state until the memory controller 20 takes the stored request information. Since the memory controller 20 receives the information from the bus interface in consideration of the pipeline bus protocol regardless of the existence of the queue, the control unit 32 of the memory queue 30 receives the stored information. You should provide appropriate information based on the point of view.

As shown in FIG. 1, the memory controller 20 receives the information data of the data bus after the address bus information Add, and the memory controller 20 knows that the information of the status bus related to the cache arrives in the next period. The control unit 32 of (30) must provide the information to the memory controller 20 in accordance with this time standard.

The function of the " dpce " signal of FIG. 5 and the flip-flops 33 and multiplexers 34 of the cache status bus is passed to the memory controller 20 in accordance with the time rules. It serves to provide information.

In other words, when transitioning from the “storage 1” state of FIG. 6 to the “ready” state, the state bus related to the cache has to be sent one cycle later than the case in which the cache is directly transmitted. In the case of the “data parity error”, the controller 32 of the memory queue 30 confirms that the error has not occurred since the control 32 of the memory queue 30 can make a transition to the state of “storage 1”.

In the same way, if it is accepted in "storage 2", the cache related status bus should delay 2 cycles. In the case of transition in "storage 3", the control queue 32 of the memory queue has already confirmed the status bus. Because it is transitioned through, there is no cancellation of the transmission, which provides the status bus.

As described above, the inventors of the present invention perform the function of the queue by tracking both the pipelined bus operation and the state of the memory controller, so that the memory controller is not burdened by the existence of the queue, and there is no delay time.

Claims (4)

It employs a pipeline technique including a memory array 10 for storing data, a memory controller 20 for controlling the memory array 10, and a bus interface unit 40 for interfacing with a system bus. In the main memory of the system, the memory controller 20 is connected between the bus interface unit 40, and transmits continuous transmission request information of the system bus transmitted from the bus interface unit 40 to the memory controller ( 20) temporarily stores the transmission request information and then transfers the transmission request information to the memory controller 20 without delay when the memory controller 20 is ready to process. Memory queue of a system using a pipeline bus protocol, characterized in that it comprises buffer means (30). The method of claim 1, wherein the buffer means 30 is a storage unit 31 for temporarily storing the address information and data information of the system bus transmitted from the bus interface unit 40, the memory controller 20 and And a control unit (32) for observing the state of the system bus and correspondingly managing the information stored in the storage unit (31). 3. The system memory queue according to claim 2, wherein said storage section (31) consists of a transparent latch. The system of claim 2, wherein the controller 32 includes a flip-flop 33 for storing the system bus status signals and multiplexers for transmitting the system bus status signals to the memory controller 20 in a temporal relationship. And a state machine (35) for integrally controlling the flip-flop (33) and the multiplexers (34).