JPH0533978Y2 - - Google Patents
Info
- Publication number
- JPH0533978Y2 JPH0533978Y2 JP14926684U JP14926684U JPH0533978Y2 JP H0533978 Y2 JPH0533978 Y2 JP H0533978Y2 JP 14926684 U JP14926684 U JP 14926684U JP 14926684 U JP14926684 U JP 14926684U JP H0533978 Y2 JPH0533978 Y2 JP H0533978Y2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- latch
- pulse
- latch circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000001360 synchronised effect Effects 0.000 claims description 17
- 238000012360 testing method Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 4
- 238000007493 shaping process Methods 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14926684U JPH0533978Y2 (enrdf_load_html_response) | 1984-10-01 | 1984-10-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14926684U JPH0533978Y2 (enrdf_load_html_response) | 1984-10-01 | 1984-10-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6163175U JPS6163175U (enrdf_load_html_response) | 1986-04-28 |
| JPH0533978Y2 true JPH0533978Y2 (enrdf_load_html_response) | 1993-08-27 |
Family
ID=30707452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14926684U Expired - Lifetime JPH0533978Y2 (enrdf_load_html_response) | 1984-10-01 | 1984-10-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0533978Y2 (enrdf_load_html_response) |
-
1984
- 1984-10-01 JP JP14926684U patent/JPH0533978Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6163175U (enrdf_load_html_response) | 1986-04-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4970405A (en) | Clock selection circuit for selecting one of a plurality of clock pulse signals | |
| EP0468732A2 (en) | Sequence control apparatus | |
| JP2576366B2 (ja) | 可変遅延バッファ回路 | |
| EP0404127A2 (en) | Signal generator | |
| JPH0746122B2 (ja) | 半導体集積論理回路 | |
| KR100313255B1 (ko) | 디지털주파수체배기용조합지연회로 | |
| US5337321A (en) | Scan path circuit with clock signal feedback, for skew avoidance | |
| JPH0682146B2 (ja) | スキヤンパス方式の論理集積回路 | |
| US6359483B1 (en) | Integrated circuit clock distribution system | |
| US5359636A (en) | Register control circuit for initialization of registers | |
| JP2846428B2 (ja) | 論理比較回路 | |
| JPH0946197A (ja) | 可変遅延回路 | |
| US5245311A (en) | Logical comparison circuit for an IC tester | |
| JPH0533978Y2 (enrdf_load_html_response) | ||
| US4741005A (en) | Counter circuit having flip-flops for synchronizing carry signals between stages | |
| US4270116A (en) | High speed data logical comparison device | |
| EP0350027A3 (en) | Sample-hold circuit | |
| JP2595104Y2 (ja) | 差動ゲートによるタイミング調整回路 | |
| KR0176845B1 (ko) | 마이크로컴퓨터의 입출력포트 확장 방법 및 회로 | |
| JP2595103Y2 (ja) | 差動ゲートによるタイミング調整回路 | |
| JP2605283B2 (ja) | カウンタ回路 | |
| JPH01290013A (ja) | 非同期クロツク選択同期化回路 | |
| JPH0429159B2 (enrdf_load_html_response) | ||
| JPH02110387A (ja) | 自動回路テスタ | |
| JP3236235B2 (ja) | トグルフリップフロップ |