JPH0533978Y2 - - Google Patents

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention relates to a signal synchronization device that can be used, for example, in an IC tester.

"Conventional technology" When testing an IC with a built-in clock signal source,
The clock signal from the clock signal source built into the IC under test is extracted and the clock signal is synchronized with this clock signal.
It is necessary to operate the IC tester.

When testing an IC with a built-in clock signal source,
A clock signal is extracted from the IC under test, a pattern signal is applied in synchronization with this clock signal, a response output to this pattern signal is obtained, and a logical comparison is performed to determine whether or not this response output signal matches an expected value.
It is configured to determine that it is defective when a mismatch is detected.

The clock signal and response output signal taken out from the IC under test are taken into the IC tester, but the response output signal and the clock signal should originally be synchronized, but the level of the response output signal taken out is compared with the reference value. The response output signal is determined whether it is H or L, and is extracted through a waveform shaping circuit that determines the logical waveform based on the determination result, so it uses a different route from the clock signal route. taken out. As a result, the response output signal and the clock signal may be out of phase. Furthermore, differences in the response speed of the IC under test also cause a phase shift between the clock and the response output.

For this reason, conventionally, a signal synchronization device has been used to match the phase between the response output signal and the clock.

FIG. 4 shows a conventional synchronization device. In the figure, 1 is the IC under test, 2 is the waveform shaping circuit, 3 is the synchronization device,
4 indicates an IC tester. A clock pulse is extracted from the IC under test 1 and applied to the IC tester 4. The IC tester 4 applies a pattern signal 6 to the IC under test 1 in synchronization with the clock pulse 5.

The response signal 7 output from the IC under test 1 is logically determined in the waveform shaping circuit 2, and the waveform is shaped into a signal having a predetermined logic level, and the signal is given to the synchronization device 3. The synchronization device 3 converts the signal to be synchronized (in this case, the response output signal 7 of the IC under test 1) into a polyphase signal so that it can be reliably synchronized even if the signal is a high-speed signal or the waveform is disturbed at the rising and falling timing. The method used is to convert it to a low-speed signal, synchronize it by latching it with the clock that should be synchronized in the state of this low-speed signal (with the waveform stabilized), and after synchronization, multiplex it and return it to the original high-speed signal. There is. This method is generally called an interleave method.

The synchronization device 3 employing this interleaving method is composed of latch circuit groups 8 and 9, gate groups 11 and 12, an OR gate group 13, and a control circuit 14 for controlling these.

The control circuit 14 is composed of a pulse distribution circuit 14A that alternately takes out the clock signal 5, and a gate signal generator 14B that generates a two-phase gate signal whose state changes every clock. The pulse distribution circuit 14A has two output terminals 15 and 16.
By applying the clock signal 5 to its input, it distributes one clock signal to the output terminals 15 and 16 and outputs a two-phase clock. The gate signal generator 14B has two output terminals 17 and 18, and outputs to these two output terminals 17 and 18 gate signals synchronized with the clock signal 5 and having opposite polarities.

The latch circuit groups 8 and 9 each include a number of latch circuits corresponding to the number of bits of the response output signal 7, and commonly supply the response output signal 7 output from the waveform shaping circuit 2 to their input terminals. Pulses distributed by the pulse distribution circuit 14A are applied to each latch command input terminal CK of the latch circuit groups 8 and 9.

FIG. 5 shows a waveform diagram for explaining the operation of the synchronization device 3. A in Fig. 5 is the response output signal 7, B
is the clock signal 5, and C and D are the two-phase pulses 5 distributed by the pulse distribution circuit 14A.
A and 5B are shown. By latching the response output signal 7 in the latch circuit groups 8 and 9 using pulses 5A and 5B, the latch circuit group 8 latches D ₁ , D ₃ , D ₅ . . . in the response output signal 7. Further, the latch circuit group 9 latches D ₂ , D ₄ , D ₆ , D ₈ . Figures E and F show the latch.

Gate circuit groups 11 and 12 receive gate signals 17A and 18A synchronized with clock signal 5 (Fig. 5 G, H).
Closing and opening are controlled by Yotsute gate circuit group 1
A response output signal synchronized with the clock signal 5 is taken out from 1 and 12, and the taken out signals are logically summed in the OR gate group 13 to produce a signal 7A synchronized with the clock signal 5 as shown in FIG. 5I. Obtainable.

"Problems to be Solved by the Invention" The control circuit 14 of the conventional synchronization device 3 consists of a pulse distribution circuit 14A constituted by a flip-flop circuit and a gate signal generator 14B. At a certain timing during the test, the relationship between the pulse distribution circuit 14A and the gate signal generator 14B must be initialized. For this purpose, a reset signal is applied to the terminal 21, and the pulse distribution circuit 14A and gate signal generator 14B are initialized by the reset signal.
This initialization is performed at a certain timing when the test starts or when a test item is changed, but it is difficult to decide where to set the timing, and it is necessary to do tedious work. There are disadvantages that cannot be avoided.

"Means for Solving the Problem" In this invention, the signals to be synchronized are provided in common to each input terminal of a plurality of latch circuits, and the signals to be synchronized are connected in cascade to the respective output sides of the plurality of latch circuits to achieve synchronization. a plurality of latch circuits forming a plurality of signal paths in which the number of parallel bits of one of the signals is one signal path, and having a clear terminal;
A pulse distribution circuit that distributes a pulse train for synchronization into a pulse train of the number of phases corresponding to the number of systems of multiple signal paths configured by cascading latch circuits; The pulse train is applied to each latch command input terminal of the cascade-connected latch circuits forming each signal path, and the pulse train is applied to the clear terminal of the latch circuit on the subsequent stage of the cascade-connected latch circuits forming the signal path. a signal path that provides a pulse train of a phase other than the phase of the pulse train for the latch command assigned to the latch circuit;
A signal synchronization device is constituted by each cascaded latch circuit and an OR circuit which takes out the latch output of the latch circuit at the subsequent stage.

According to the structure of this invention, the structure is such that the latch circuit on the latter stage, which constitutes the signal path, is cleared by the pulse of the phase other than the phase assigned to itself, together with the latch command, so that the latch circuit operates. is uniquely determined by the pulses distributed by the pulse distribution circuit. Therefore, there is no need to perform an initial reset. Therefore, it is possible to configure an IC tester that is easy to handle.

``Example'' Figure 1 shows an example of this invention. 14 in the diagram
A is a pulse distribution circuit that constitutes the control circuit 14;
10 and 20 indicate a first signal path and a second signal path. These first signal path and second signal path 2
0 is constituted by a cascade connection of a number of latch circuits corresponding to the number of parallel bits of the response output signal 7 to be synchronized. In the figure, the latch circuit groups 8 and 22 constitute the first signal path 10, and the latch circuit groups 9 and 2 constitute the first signal path 10.
3 shows a case in which the second signal path 20 is configured by 3.

In this example, the pulse distribution circuit 14A converts the high speed clock 5 into two-phase low speed pulses 5 shown in FIG. 2C and D.
Sort into A and 5B. One of the thus distributed low-speed pulses 5A and 5B, in this example pulse 5A, is applied to each latch command input terminal CK of the latch circuit groups 8 and 22 constituting the first signal path 10,
The low-speed pulse 5B is sent to each latch command input terminal CK of the latch circuit groups 9 and 23 that constitute the second signal path 20.
give to Along with this, the latch circuit group 2 on the rear stage side
There is a clear terminal in the latch circuit that constitutes 2 and 23.
A latch circuit equipped with CL is used, and its own latch command input terminal CK is connected to this clear terminal CL.
Low-speed pulse 5A or 5B of a phase other than that given to
give. In other words, in this example, the low-speed pulse 5B is routed through the signal path L ₂ to each clear terminal CL of the latch circuit group 22.
A low-speed pulse of 5A is applied to latch circuit group 2.
3 through the signal path _L1 .

Note that 24 and 25 in the figure indicate delay circuits.

The latch outputs of the latch circuit groups 22 and 23 are logically summed by the OR gate group 13 and are connected to the common signal line 2.
6, a response signal 7A synchronized with the clock signal 5 is sent out. Further, pulses 5A and 5B outputted from the pulse distribution circuit 14A are added together by an OR gate 27 and taken out as a clock signal 5C.

(Operation of Embodiment) FIG. 2 shows a waveform diagram for explaining the operating state of the embodiment shown in FIG. 1. Pulse distribution circuit 1
The first signal path 10 is controlled by applying two-phase low-speed pulses 5A and 5B (FIG. 2 C, D) distributed by the latch circuit groups 8 and 9 to the latch command input terminals CK of the latch circuit groups 8 and 9. As shown in FIG. 2E, signals D1, D3, D5, D7, . . . in the response output signal are latched in the latch circuit group 8.
In addition, a latch circuit group 9 constituting the second signal path 20
As shown in Figure 2F, the signals D2, D4, D6,
D8... is latched.

The low-speed pulses 5A and 5B are delayed by the necessary amount by delay circuits 24 and 25 and applied to the latch command input terminals CK and clear terminals CL of the latch circuit groups 22 and 23. Therefore, for example, when the low speed pulse 5A is applied to the latch command input terminal CK of the latch circuit group 22, the other latch circuit group 23 is cleared. Also, the latch command input terminal of the latch circuit group 23
When low speed pulse 5B is applied to CK, the other latch circuit group 22 is cleared.

Therefore, on the output side of the OR gate 13, a response output signal 7A having a phase delayed by the delay time .tau. of the delay circuits 24 and 25 from the phase of the original clock signal 5 is obtained as shown in FIG. 2G. Further, from the OR gate 27, a clock signal 5C is obtained which matches the phase of the response output signal 7A. In this way, it is possible to obtain the response output signal 7A and the clock signal 5C whose phases match.

"Effect of the invention" As mentioned above, according to this invention, the latch circuit groups 8 and 9 and the latch circuit groups 22 and 23 are controlled using the common low-speed pulses 5A and 5B. The operations of 22, 9, and 23 are uniquely determined by the low-speed pulses 5A and 5B and do not need to be initialized. Therefore, there is no need to provide a reset pulse generator, and the device can be manufactured at low cost.
Furthermore, since there is no need to consider the timing of reset pulse generation, an IC tester that is easy to handle can be provided.

"Modified Embodiment" In the above, the response output signal 7 is connected to the latch circuit groups 8 and 9.
Although we have explained the case where the system is separated into two systems and synchronized, another example is as shown in Fig. 3, where the system is separated into three systems or even more systems and synchronized at an even slower speed. You can also do it.

In addition, in the above example, IC is used as a signal for synchronization.
Although the case of the response output signal 7 and the clock signal 5 has been described, it is easy to understand that this invention can be applied to the case of synchronizing other signals as well.

[Brief explanation of the drawing]

Fig. 1 is a system diagram for explaining one embodiment of this invention, Fig. 2 is a waveform diagram for explaining the operation of Fig. 1, and Fig. 3 is a system diagram showing another embodiment of this invention. , FIG. 4 is a system diagram for explaining a conventional synchronization device, and FIG. 5 is a waveform diagram for explaining the operation of FIG. 4. 5...Clock signal, 7...Response output signal,
8, 9... Latch circuit group, 10... First signal path, 13, 27... OR gate, 14... Control circuit, 14A... Pulse distribution circuit, 15, 16...
...Output terminal, 20...Second signal path, 22, 23
...Latch circuit group.

Claims (1)

[Claims for Utility Model Registration] A. A number of latch circuits in which the signals to be synchronized are commonly applied to each input terminal, and the number of parallel bits of the signals to be synchronized corresponds to a plurality of signal paths as one signal path. B. A plurality of latch circuits equipped with clear terminals and continuously connected to the output terminals of the respective latch circuits constituting the plurality of signal paths; and C. A pulse train for synchronization is connected to the cascade of the latch circuits. (D) a pulse distribution circuit that distributes pulse trains of the number of phases corresponding to the number of systems in the plurality of signal paths configured as above; A signal path to be applied to each latch command input terminal of the latch circuit that has been set,
a signal path for providing a pulse train of a phase other than the phase of the pulse train for the latch command assigned to each latch circuit; A signal synchronization device characterized in that it is configured as follows.