JPH0533823B2 - - Google Patents

Info

Publication number
JPH0533823B2
JPH0533823B2 JP63083802A JP8380288A JPH0533823B2 JP H0533823 B2 JPH0533823 B2 JP H0533823B2 JP 63083802 A JP63083802 A JP 63083802A JP 8380288 A JP8380288 A JP 8380288A JP H0533823 B2 JPH0533823 B2 JP H0533823B2
Authority
JP
Japan
Prior art keywords
layer
electrode pad
bonding
semiconductor element
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63083802A
Other languages
English (en)
Japanese (ja)
Other versions
JPH01255234A (ja
Inventor
Takashi Shibata
Osamu Usuda
Isamu Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP63083802A priority Critical patent/JPH01255234A/ja
Publication of JPH01255234A publication Critical patent/JPH01255234A/ja
Publication of JPH0533823B2 publication Critical patent/JPH0533823B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05009Bonding area integrally formed with a via connection of the semiconductor or solid-state body
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
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    • H01L2224/05073Single internal layer
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/852Applying energy for connecting
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    • H01L2924/0001Technical content checked by a classifier
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    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP63083802A 1988-04-05 1988-04-05 半導体装置 Granted JPH01255234A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63083802A JPH01255234A (ja) 1988-04-05 1988-04-05 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63083802A JPH01255234A (ja) 1988-04-05 1988-04-05 半導体装置

Publications (2)

Publication Number Publication Date
JPH01255234A JPH01255234A (ja) 1989-10-12
JPH0533823B2 true JPH0533823B2 (enrdf_load_stackoverflow) 1993-05-20

Family

ID=13812792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63083802A Granted JPH01255234A (ja) 1988-04-05 1988-04-05 半導体装置

Country Status (1)

Country Link
JP (1) JPH01255234A (enrdf_load_stackoverflow)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6790757B1 (en) 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
DE102006044691B4 (de) * 2006-09-22 2012-06-21 Infineon Technologies Ag Verfahren zum Herstellen einer Anschlussleitstruktur eines Bauelements
JP2010258286A (ja) * 2009-04-27 2010-11-11 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP5978587B2 (ja) * 2011-10-13 2016-08-24 日立化成株式会社 半導体パッケージ及びその製造方法
JP2014021065A (ja) * 2012-07-23 2014-02-03 Denso Corp 物理量センサ

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58212169A (ja) * 1982-06-04 1983-12-09 Toshiba Corp 三層電極構造を有する半導体装置

Also Published As

Publication number Publication date
JPH01255234A (ja) 1989-10-12

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