JPH05327148A - Laminated plate for printed circuit - Google Patents

Laminated plate for printed circuit

Info

Publication number
JPH05327148A
JPH05327148A JP15575892A JP15575892A JPH05327148A JP H05327148 A JPH05327148 A JP H05327148A JP 15575892 A JP15575892 A JP 15575892A JP 15575892 A JP15575892 A JP 15575892A JP H05327148 A JPH05327148 A JP H05327148A
Authority
JP
Japan
Prior art keywords
printed circuit
thermal expansion
insulating layer
coefficient
laminated plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15575892A
Other languages
Japanese (ja)
Inventor
Masaaki Ueki
正暁 上木
Tokuo Kurokawa
徳雄 黒川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Chemical Corp
Original Assignee
Toshiba Chemical Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Chemical Corp filed Critical Toshiba Chemical Corp
Priority to JP15575892A priority Critical patent/JPH05327148A/en
Publication of JPH05327148A publication Critical patent/JPH05327148A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a laminated plate for printed circuit with the small thermal expansion coefficient and excellent through hole reliability. CONSTITUTION:Within this laminated plate for printed circuit comprising an insulating layer and a conductive layer, the insulating layer is composed of a prepreg impregnated with a thermosetting resin and dried up to be molded and set on a base material containing more then 50% of para-base aromatic polyamide fiber. At this time, the thermal expansion coefficient of this insulating layer within the range of 25-125 deg.C is to be specified as 9-11ppm/K in facial direction and 80-120ppm/K in thickness direction. Through these procedures, the title lamimated plate in the small thermal coefficient, causing no solder cracking at all and having enhanced through hole reliability can be manufactured.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、CLCC、TSOP等
の熱膨脹率の小さいパッケージ形態の半導体装置の実装
に適し、スルーホール信頼性に優れたプリント回路用積
層板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated board for a printed circuit, which is suitable for mounting a semiconductor device having a package having a small coefficient of thermal expansion such as CLCC or TSOP and which has excellent through hole reliability.

【0002】[0002]

【従来の技術】近年の技術革新は目覚ましく、電子機器
のダウンサイジングは止まるところを知らない。それ
は、実装技術の高密度化、半導体の高集積化及び半導体
パッケージの小形化技術によるものであり、CLCC
(ceramic leadless chip carrier)、TSOP(thin
small outline package)等の半導体チップサイズに比
してパッケージサイズの小さい半導体装置が多用され始
めている。ところが従来、産業用機器のプリント回路用
基板として用いられてきた銅張積層板の代表的なもの、
すなわち、ガラスクロス等の基材に、熱硬化性樹脂を含
浸・乾燥したプリプレグと銅箔を加熱加圧一体に成形し
てなる銅張積層板は、必ずしもCLCC、TSOP等の
半導体装置の実装に適したものとは言えない。
2. Description of the Related Art Recent technological innovations have been remarkable, and downsizing of electronic devices has never stopped. This is due to high-density packaging technology, high integration of semiconductors, and miniaturization technology of semiconductor packages.
(Ceramic leadless chip carrier), TSOP (thin
Small outline package) and other semiconductor devices with a smaller package size than the semiconductor chip size are becoming popular. However, a typical copper clad laminate that has been conventionally used as a printed circuit board for industrial equipment,
That is, a copper clad laminate formed by integrally molding a prepreg and a copper foil, which are impregnated with a thermosetting resin and dried on a base material such as glass cloth, under heat and pressure, is not necessarily required for mounting semiconductor devices such as CLCC and TSOP. Not a good fit.

【0003】CLCCはパッケージ材質がセラミックス
であり、一般に用いられるガラス基材エポキシ積層板と
は熱膨脹率が大きく異なる上に、熱応力を吸収するリー
ドを持たない。TSOPはパッケージ材質がエポキシ樹
脂封止材であっても、シリコンチップに対しての樹脂封
止材の量が少なく、全体の熱膨脹率は従来のパッケージ
に比べて非常に小さくリードも大変短い。そのため両者
ともガラス基材エポキシ積層板上に実装した場合、熱膨
脹率不整合による半田クラック不良が多発する欠点があ
る。そこで面方向の熱膨脹率の小さい積層板として、ア
ラミド基材エポキシ積層板が使用されることがある。し
かし、アラミド布積層板は機械加工が非常に難しい上に
高価で実用に適さない。またアラミドペーパー積層板は
面方向の熱膨脹率が 6〜8ppm/Kと非常に低く抑えられ
ている反面、厚み方向の熱膨脹率が 130〜300ppm/Kと
非常に大きく、基板のスルーホール信頼性に問題があっ
た。
The package material of CLCC is ceramics, and the coefficient of thermal expansion is greatly different from that of a glass-based epoxy laminate generally used, and it has no lead for absorbing thermal stress. Even if the package material of the TSOP is an epoxy resin encapsulant, the amount of the resin encapsulant for the silicon chip is small, and the overall coefficient of thermal expansion is much smaller than that of the conventional package, and the leads are also very short. Therefore, when both are mounted on a glass-based epoxy laminate, there is a drawback that solder crack defects frequently occur due to mismatch of thermal expansion coefficients. Therefore, an aramid-based epoxy laminate may be used as the laminate having a small coefficient of thermal expansion in the plane direction. However, the aramid cloth laminate is very difficult to machine, expensive and not suitable for practical use. In addition, the thermal expansion coefficient of the aramid paper laminated plate is kept very low at 6 to 8 ppm / K, while the thermal expansion coefficient of the thickness direction is very large at 130 to 300 ppm / K, which makes it possible to improve the through hole reliability of the substrate. There was a problem.

【0004】[0004]

【発明が解決しようとする課題】本発明は、上記の事情
に鑑みてなされたもので、熱膨脹率が小さく、半田クラ
ックの発生のない、スルーホール信頼性に優れたCLC
C、TSOP等の半導体装置の実装に最適な、プリント
回路用積層板を提供しようとするものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a small coefficient of thermal expansion, does not cause solder cracks, and has excellent through-hole reliability.
It is intended to provide a laminated board for a printed circuit, which is most suitable for mounting a semiconductor device such as C or TSOP.

【0005】[0005]

【課題を解決するための手段】本発明者らは、上記の目
的を達成しようと鋭意研究を重ねた結果、パラ系芳香族
ポリアミド繊維を50%以上含有する基材を使用すること
によって、上記の目的を達成できることを見いだし、本
発明を完成したものである。
Means for Solving the Problems As a result of intensive studies aimed at achieving the above object, the present inventors have found that the use of a base material containing 50% or more of para aromatic polyamide fiber results in The present invention has been completed by finding out that the above object can be achieved.

【0006】即ち、本発明は、絶縁層と導電層からなる
プリント回路用積層板であって、絶縁層が、パラ系芳香
族ポリアミド繊維を50%以上含有する基材に熱硬化性樹
脂を含浸・乾燥したプリプレグを、成形して硬化させた
層であり、絶縁層の25〜125 ℃の温度範囲における熱膨
脹率が、面方向で 9〜11 ppm/K、厚さ方向で80〜120p
pm/Kであることを特徴とするプリント回路用積層板で
ある。
That is, the present invention is a laminated board for a printed circuit comprising an insulating layer and a conductive layer, wherein the insulating layer impregnates a base material containing 50% or more of para aromatic polyamide fiber with a thermosetting resin.・ A layer obtained by molding and curing a dried prepreg. The thermal expansion coefficient of the insulating layer in the temperature range of 25 to 125 ℃ is 9 to 11 ppm / K in the plane direction and 80 to 120 p in the thickness direction.
It is a laminated board for a printed circuit characterized by having pm / K.

【0007】以下、本発明を詳細に説明する。The present invention will be described in detail below.

【0008】本発明に用いる基材としては、パラ系芳香
族ポリアミド繊維を50%以上含有するクロス、紙、不織
布等が挙げられ、これらは単独または混合して使用する
ことができる。パラ系芳香族ポリアミド繊維以外の繊維
は、ガラスクロス、セルロース、合成樹脂からなる繊
維、金属繊維などからなる織布、不織布、ペーパー等を
組合わみせて使用することができる。基材のうちのパラ
系芳香族ポリアミド繊維の割合が50%未満では、25〜12
5 ℃の温度範囲における熱膨脹率が面方向で 9〜11 ppm
/k 、厚み方向で80〜120ppm/k の特性を保持すること
ができず好ましくない。
The substrate used in the present invention includes cloth, paper, non-woven fabric and the like containing 50% or more of para-aromatic polyamide fiber, and these can be used alone or in combination. Fibers other than the para-aromatic polyamide fiber can be used in combination with glass cloth, cellulose, fibers made of synthetic resin, woven cloth made of metal fibers, nonwoven cloth, paper and the like. If the ratio of para-aromatic polyamide fiber in the base material is less than 50%, 25 to 12
Coefficient of thermal expansion in the plane direction of 9 to 11 ppm in the temperature range of 5 ° C
/ K and 80 to 120 ppm / k in the thickness direction cannot be maintained, which is not preferable.

【0009】本発明に用いる熱硬化性樹脂としては、溶
媒を加えて基材に含浸しやすいように粘度調整を行った
ものを使用する。具体的な樹脂としてはエポキシ樹脂、
ポリイミド樹脂およびこれらの変性樹脂等が好ましく使
用されるが、特にこれらに限定されるものではない。熱
硬化性樹脂には溶媒を加えてワニスとするが、ワニスに
は本発明の目的に反しない範囲において、高熱伝導性あ
るいは低誘電率の充填剤を配合することができる。熱伝
導性の良い充填剤としては、水酸化アルミニウム、シリ
カ等が挙げられ、また低誘電率の充填剤として弗素樹脂
粉末、中空ガラスビーズ等が挙げられる。また、必要に
応じてタルク、炭酸カルシウム等を適宜配合することが
できる。こうして得たワニスを、上述の基材に含浸・乾
燥してプリプレグをつくり、このプリプレグを絶縁層と
して使用しプリント回路用積層板を製造することができ
る。
The thermosetting resin used in the present invention is a thermosetting resin whose viscosity is adjusted so that the base material can be easily impregnated with a solvent. As a concrete resin, epoxy resin,
Polyimide resins and modified resins thereof are preferably used, but not limited thereto. A solvent is added to the thermosetting resin to form a varnish, and the varnish can be blended with a filler having a high thermal conductivity or a low dielectric constant as long as the purpose of the present invention is not impaired. Examples of the filler having good thermal conductivity include aluminum hydroxide and silica, and examples of the filler having a low dielectric constant include fluororesin powder and hollow glass beads. If necessary, talc, calcium carbonate and the like can be appropriately added. The varnish thus obtained is impregnated into the above-mentioned base material and dried to form a prepreg, and the prepreg can be used as an insulating layer to produce a laminated board for a printed circuit.

【0010】本発明のプリント回路用積層板を構成する
導電層は、金属箔、金属鍍金層、導電ペースト層等で回
路形成可能なものであれば特に限定するものではない。
特に銅箔等の金属箔を使用する場合は、上述したプリプ
レグ複数枚を重ねて、その少なくとも片面に金属箔を配
置し、ステンレス板間に挟み加熱プレスによって一体に
積層成形し、選択エッチングにより導電層を形成できる
ので、大量生産に適しており製造上の利点が有る。金属
鍍金層を用いる場合は接着剤付積層板をつくり、接着剤
の表面に必要部分のみ鍍金して導電層を形成させる。導
電ペースト層で回路形成する場合には、積層板の表面に
スクリーン印刷等によって導電層を形成することができ
る。
The conductive layer constituting the laminate for a printed circuit of the present invention is not particularly limited as long as it can form a circuit with a metal foil, a metal plating layer, a conductive paste layer and the like.
Especially when a metal foil such as a copper foil is used, a plurality of the above-mentioned prepregs are stacked, the metal foil is arranged on at least one surface of the prepreg, sandwiched between stainless steel plates and laminated integrally by a heat press, and conductive by selective etching. Since the layers can be formed, they are suitable for mass production and have manufacturing advantages. When a metal plating layer is used, a laminated plate with an adhesive is prepared, and only a necessary portion is plated on the surface of the adhesive to form a conductive layer. When the circuit is formed by the conductive paste layer, the conductive layer can be formed on the surface of the laminated plate by screen printing or the like.

【0011】こうして製造したプリント回路用積層板
は、CLCC、TSOP等の面方向の熱膨脹率の小さい
半導体装置を実装する回路板として好適に使用できる。
The printed circuit laminate thus manufactured can be suitably used as a circuit board for mounting a semiconductor device such as CLCC or TSOP having a small coefficient of thermal expansion in the plane direction.

【0012】[0012]

【作用】パラ系芳香族ポリアミド繊維は、紡糸方向に負
の熱膨脹率を示すが繊維の径方向の熱膨脹率は正であ
る。このため抄紙時に繊維配向が面方向に偏ると面方向
の熱膨脹率はマイナスで、厚み方向の熱膨脹率が大きい
基材となる。このタイプの基材に樹脂を含浸し成形した
積層板は、面方向の熱膨脹率は小さいが厚み方向の熱膨
脹率が大きいものとなる。これは基材の挙動に加えて、
面方向の熱膨脹が抑えられた積層板のマトリックス樹脂
の膨脹応力が厚み方向に集中した結果のものである。パ
ラ系芳香族ポリアミド繊維基材の厚み方向の熱膨脹率を
小さく抑えるには、各種の方法があるが、特に制限する
ものではなくいずれの方法でも使用でき、また組合せの
方法でもよい。基材の面方向と厚み方向の熱膨脹率のバ
ランスを調整することで、積層板の膨脹率のバランスを
調整することができたものである。本発明のプリント回
路用積層板は、25〜125 ℃の温度範囲における熱膨脹率
が面方向で 9〜11 ppm/k 、厚み方向で80〜120ppm/K
と調整したことによって、CLCC、TSOP等の半導
体装置と面方向の熱膨脹率を整合させ、かつスルーホー
ル信頼性を向上させることができた。
The para-aromatic polyamide fiber has a negative coefficient of thermal expansion in the spinning direction, but the coefficient of thermal expansion in the radial direction of the fiber is positive. Therefore, when the fiber orientation is biased in the plane direction during papermaking, the coefficient of thermal expansion in the plane direction is negative, and the substrate has a large coefficient of thermal expansion in the thickness direction. A laminated plate obtained by impregnating a base material of this type with a resin has a small coefficient of thermal expansion in the plane direction, but a large coefficient of thermal expansion in the thickness direction. This is in addition to the behavior of the substrate,
This is a result of the expansion stress of the matrix resin of the laminated plate in which the thermal expansion in the surface direction is suppressed, concentrated in the thickness direction. There are various methods for suppressing the thermal expansion coefficient of the para-aromatic polyamide fiber base material in the thickness direction, but there is no particular limitation, and any method can be used, or a combination method may be used. By adjusting the balance between the thermal expansion coefficient of the substrate in the plane direction and the thermal expansion coefficient of the thickness direction, the balance of the expansion coefficient of the laminated plate could be adjusted. The printed circuit laminate of the present invention has a coefficient of thermal expansion in the plane direction of 9 to 11 ppm / k and a thickness direction of 80 to 120 ppm / K in the temperature range of 25 to 125 ° C.
By adjusting the above, it was possible to match the coefficient of thermal expansion in the plane direction with a semiconductor device such as CLCC or TSOP and to improve the reliability of the through hole.

【0013】[0013]

【実施例】本発明を実施例によって具体的に説明する
が、本発明はこれらの実施例によって限定されるもので
はない。
EXAMPLES The present invention will be specifically described with reference to examples, but the present invention is not limited to these examples.

【0014】実施例 繊維ランダム配向の 0.07mm 厚のパラ系芳香族ポリアミ
ドペーパー基材、サーマウント(デュポン社製、商品
名)に、耐熱エポキシ樹脂ワニスを含浸・乾燥してプリ
プレグをつくり、このプリプレグ11枚を重ね、その両面
に厚さ18μm の電解銅箔を配置してステンレス板間に挟
み、加熱プレスによって一体に積層成形し、厚さ 0.8mm
のプリント回路用積層板を製造した。
Example A prepreg was prepared by impregnating and drying a heat-resistant epoxy resin varnish on a Cermount (trade name, manufactured by DuPont), a para-aromatic polyamide paper substrate having a random fiber orientation of 0.07 mm, and using this prepreg. 11 sheets are stacked, electrolytic copper foil with a thickness of 18 μm is placed on both sides, sandwiched between stainless steel plates, and laminated by heat press to form a laminated body with a thickness of 0.8 mm.
Of the printed circuit board was manufactured.

【0015】比較例1 繊維平面配向の 0.1mm厚のパラ系芳香族ポリアミドペー
パー基材、テクノーラ(帝人社製、商品名)に、耐熱エ
ポキシ樹脂ワニスを含浸・乾燥してプリプレグをつく
り、このプリプレグ 8枚を重ね、その両面に厚さ18μm
の電解銅箔を配置してステンレス板間に挟み、加熱プレ
スによって一体に積層成形し、厚さ 0.8mmのプリント回
路用積層板を製造した。
Comparative Example 1 A prepreg was prepared by impregnating and drying a heat-resistant epoxy resin varnish, Technora (manufactured by Teijin Ltd., trade name), a para-aromatic polyamide paper substrate having a fiber plane orientation of 0.1 mm. 8 sheets are piled up and 18 μm thick on both sides
The electrolytic copper foil of 1 was placed, sandwiched between stainless steel plates, and integrally laminated by hot pressing to produce a 0.8 mm-thick printed circuit laminate.

【0016】比較例2 厚さ 0.8mm汎用ガラス基材エポキシプリント回路用積層
板(FR−4グレード)を用意した。
Comparative Example 2 A laminated board (FR-4 grade) for a general-purpose glass substrate epoxy printed circuit having a thickness of 0.8 mm was prepared.

【0017】実施例および比較例1〜2で製造したプリ
ント回路用積層板について、熱膨脹率、TSOPの接続
安定性、スルーホール信頼性を試験したのでその結果を
表1に示した。本発明はいずれの特性においても優れて
おり、本発明の効果が確認された。
The printed circuit laminates manufactured in Examples and Comparative Examples 1 and 2 were tested for thermal expansion coefficient, TSOP connection stability, and through hole reliability. The results are shown in Table 1. The present invention is excellent in all properties, and the effect of the present invention was confirmed.

【0018】[0018]

【表1】 *1 :熱膨脹率測定温度範囲 CTEα1 25〜125 ℃
。 *2 :試験条件 気中ヒートサイクル −40℃・1h〜15
0 ℃・1h 。
[Table 1] * 1: Thermal expansion coefficient measurement temperature range CTEα 1 25 to 125 ℃
.. * 2: Test condition Air heat cycle -40 ℃ ・ 1h〜15
0 ℃ ・ 1h.

【0019】[0019]

【発明の効果】以上の説明および表1から明らかなよう
に、本発明のプリント回路用積層板は、熱膨脹率が小さ
く、半田クラックの発生のない、スルーホール信頼性に
優れたもので、CLCC、TSOP等の半導体装置の実
装に最適なものである。
As is apparent from the above description and Table 1, the printed circuit laminate of the present invention has a small coefficient of thermal expansion, is free from solder cracks, and has excellent through-hole reliability. , TSOP, etc. are most suitable for mounting semiconductor devices.

フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 // B32B 15/08 J Front page continuation (51) Int.Cl. 5 Identification code Office reference number FI technical display location // B32B 15/08 J

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 絶縁層と導電層からなるプリント回路用
積層板であって、絶縁層が、パラ系芳香族ポリアミド繊
維を50%以上含有する基材に熱硬化性樹脂を含浸・乾燥
したプリプレグを、成形して硬化させた層であり、絶縁
層の25〜125℃の温度範囲における熱膨脹率が、面方向
で 9〜11 ppm/K、厚さ方向で80〜120ppm/Kであるこ
とを特徴とするプリント回路用積層板。
1. A laminated board for a printed circuit, comprising an insulating layer and a conductive layer, wherein the insulating layer is a prepreg obtained by impregnating a base material containing 50% or more of para aromatic polyamide fiber with a thermosetting resin and drying. Is a layer which is molded and cured, and the thermal expansion coefficient of the insulating layer in the temperature range of 25 to 125 ° C. is 9 to 11 ppm / K in the plane direction and 80 to 120 ppm / K in the thickness direction. Characteristic printed circuit board.
JP15575892A 1992-05-23 1992-05-23 Laminated plate for printed circuit Pending JPH05327148A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15575892A JPH05327148A (en) 1992-05-23 1992-05-23 Laminated plate for printed circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15575892A JPH05327148A (en) 1992-05-23 1992-05-23 Laminated plate for printed circuit

Publications (1)

Publication Number Publication Date
JPH05327148A true JPH05327148A (en) 1993-12-10

Family

ID=15612770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15575892A Pending JPH05327148A (en) 1992-05-23 1992-05-23 Laminated plate for printed circuit

Country Status (1)

Country Link
JP (1) JPH05327148A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0768334A3 (en) * 1995-10-16 1997-06-04 Sumitomo Chemical Company Limited Prepreg, process for producing the same and printed circuit substrate using the same
EP1345241A1 (en) * 2000-11-27 2003-09-17 Daikin Industries, Ltd. Electrical insulating plate, prepreg laminate and method for producing them
US6642282B2 (en) 2001-03-30 2003-11-04 Sumitomo Chemical Company, Limited Porous para-oriented aromatic polyamide film, prepreg thereof, and base substrate for printed circuit board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0768334A3 (en) * 1995-10-16 1997-06-04 Sumitomo Chemical Company Limited Prepreg, process for producing the same and printed circuit substrate using the same
US5851646A (en) * 1995-10-16 1998-12-22 Sumitomo Chemical Company, Limited Prepreg, process for producing the same and printed circuit substrate/board using the same
EP1345241A1 (en) * 2000-11-27 2003-09-17 Daikin Industries, Ltd. Electrical insulating plate, prepreg laminate and method for producing them
EP1345241A4 (en) * 2000-11-27 2004-09-08 Daikin Ind Ltd Electrical insulating plate, prepreg laminate and method for producing them
US6642282B2 (en) 2001-03-30 2003-11-04 Sumitomo Chemical Company, Limited Porous para-oriented aromatic polyamide film, prepreg thereof, and base substrate for printed circuit board

Similar Documents

Publication Publication Date Title
US6849934B2 (en) Dielectric film for printed wiring board, multilayer printed board, and semiconductor device
JPH11315479A (en) Textile material and its production
US6492008B1 (en) Multilayer printed wiring board and electronic equipment
JP2010238907A (en) Laminated board, multilayer printed wiring board, and semiconductor device
JP3669782B2 (en) IC package bonding sheet and IC package
JPH05327148A (en) Laminated plate for printed circuit
JP2008294387A (en) Build-up wiring board for semiconductor device
JP2006315391A (en) Laminated plate and printed circuit board using the same
JP3596899B2 (en) Low expansion metal foil and laminate for printed circuit
JPH06188330A (en) Low-expansion metal foil and laminated board for printed circuit
JPH08111571A (en) Laminated board for printed circuit
JP3067517B2 (en) Metal foil clad laminate and method for producing the same
JP2770485B2 (en) Circuit board
JPH05318640A (en) Laminated sheet
JPH06188531A (en) Low expansion metal foil and laminate for printed circuit
JPH05291711A (en) Board for high-frequency circuit use
JPH0521957A (en) Multilayered copper-clad board
JP3211608B2 (en) Manufacturing method of copper-clad laminate
JP3227874B2 (en) Manufacturing method of laminated board
JPH11150366A (en) Production of sequential multilayer wiring board
JP2001030279A (en) Manufacture of laminated sheet
JPH03127894A (en) Laminated board for printed circuit
JPH07142829A (en) Printed circuit laminated board and prepreg
JPH05229062A (en) Metal foil clad laminated plate and printed circuit board
JPS60236279A (en) Plate for circuit