JPH05323374A - Thin-film transistor matrix device and its production - Google Patents

Abstract

PURPOSE:To provide the novel thin-film transistor(TFT) matrix device which can decrease the damages of an insulating film for storage capacities in an etching stage at the time of forming the TFTs and the process for production of the device. CONSTITUTION:This TFT matrix device has a gate electrode layer 11 connected to gate bus lines, a gate insulating layer 12 laminated on the gate electrode layer, a semiconductor layer 13 including an active layer disposed in contact with the gate insulating layer and a pair of contact layers thereon, a protective film 14 covering the active layer of the semiconductor layer, a source electrode layer 16 connecting one of the contact layers to signal bus lines and a drain electrode layer 17 connecting the other of the contact layers to picture element electrodes 18. The device has an insulating layer 22 constituting the layer common with the gate insulating layer on the storage capacity electrodes in the intersected regions of the storage capacity electrodes 21 and the picture element electrodes and a protective layer 24 which is disposed thereon and constitute the layer common with a part of the other layer forming the TFTs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor matrix device used in an active matrix driving type liquid crystal display panel and a method of manufacturing the same, and more particularly to a pixel electrode for enabling display of a multi-line display image with good contrast. And a thin film transistor matrix device having a storage capacitor electrode provided in parallel therewith and a manufacturing method thereof.

In this specification, the thin film transistor electrode on the side connected to the pixel electrode is called the drain electrode, and the current electrode on the opposite side is called the source electrode.

[0003]

2. Description of the Related Art In a liquid crystal display panel using an active matrix drive system, thin film transistors (TFTs) are arranged in a matrix for each pixel for displaying a dot, and when a thin film transistor is turned on, a pixel electrode and a counter electrode sandwiching liquid crystal are sandwiched between them. A voltage is applied to each pixel, and each pixel is provided with a memory function by a storage capacitor to hold an electric charge for one field scanning period, thereby enabling multi-line image display with good contrast.

FIG. 17 shows a planar structure of a liquid crystal display panel by the active matrix driving method. In the liquid crystal display panel of FIG. 17, a large number of gate bus lines GB1, GB2, ...
, And source bus lines SB1, SB2, ..., And storage capacitor electrode lines C1, which are parallel to the gate bus lines.
C2 ... Is formed.

Thin film transistors T11, T12, ... T2 are provided at the intersections of the gate bus lines and the source bus lines.
, T22, ... Are connected. The drain of the thin film transistor has pixel electrodes P11, P12, ... P.
21, P22, ... Each pixel electrode faces the counter electrode with the liquid crystal layer in between.

The gate electrodes of the thin film transistors are connected to the gate bus lines GB1, GB2, ..., And the gate electrodes of the thin film transistors of one row of pixels which are simultaneously driven by a gate line drive circuit (not shown) are selected.

The source electrode of the thin film transistor is connected to the source bus lines SB1, SB2, ...
A source line drive circuit (not shown) gives a signal voltage which is image information. A desired pixel is displayed in dots by scanning the screen line by line.

FIG. 18 shows a cross section taken along the line AA 'of FIG. 17 of a conventional thin film transistor matrix device. The left side of FIG. 18 is the thin film transistor area and the right side is the storage capacity area. The thin film transistor region and the storage capacitor region are formed on the common glass substrate 40.

In FIG. 18, a gate bus line having a double-layer structure made of Al (aluminum) and Ti (titanium) (GB1, G in FIG. 17) is formed on a transparent insulating glass substrate 40.
A gate electrode 41 connected to B2, ...

A gate insulating film 42 having a two-layer structure of SiO ₂ (silicon oxide) and SiN (silicon nitride) is formed so as to cover the patterned gate electrode 41, and plasma CVD is performed on the gate insulating film 42 at a position facing the gate electrode 41. The operating semiconductor layer 43 is formed of a-Si (amorphous silicon) formed by
A channel protection film 44 made of SiN is formed on the above.

Further, a source electrode 46 and a drain electrode 47, which are in contact with the a-Si layer 43, are formed via an n ⁺ -type a-Si layer 45 for forming ohmic contact, and further ITO (indium tin) is in contact with the drain electrode 47. A transparent pixel electrode 48 of oxide) is formed.

The entire thin film transistor region is covered with a passivation film 49 such as a SiN film or an alumina film.
The source electrode 46 is a source bus line (S in FIG. 17).
B1, SB2, ...) are connected.

The storage capacitor portion is also formed of the same material as that of the above-mentioned thin film transistor. That is, the storage capacitor electrode C1 is also formed of the same material in the same process as the formation of the gate electrode 41 in the thin film transistor manufacturing process. In addition, in the same step as the formation of the gate insulating film 42 of the thin film transistor, the same material is used to form the insulating film 4 for the storage capacitor on the storage electrode C1.
2 is formed.

Further, an ITO pixel electrode 48 is formed so as to cover the upper part of the storage electrode C1. The storage capacitor formed by the pixel electrode 48 and the storage capacitor electrode C1 is configured to be electrically parallel to a counter electrode (not shown) that faces the pixel electrode 48.

A method of manufacturing such a thin film transistor matrix device will be briefly described below. Two layers of Al and Ti are continuously formed on the glass substrate 40 by sputtering, and the gate electrode 41, the gate bus line connected to the gate electrode, and the storage capacitor electrode C1 are patterned using photolithography.

Then, Si is formed on the entire surface of the glass substrate 40.
Two layers of O ₂ and SiN are formed by plasma CVD or the like to form the gate insulating film 42. On the gate insulating film 42, the operating semiconductor layer 4 made of a-Si, SiN
Deposit layers.

Applying a photoresist film on the SiN layer,
Exposure is performed from the lower side of the glass substrate 40, and a pattern self-aligned with the gate electrode 41 is printed. Subsequently, exposure including the gate bus line and the storage capacitor electrode portion is performed from the upper surface to leave only the portion to be the channel region unexposed. For example, this unexposed area is several μm from the gate bus line.
They are formed apart from each other.

Using the photoresist mask thus formed, the SiN layer is etched with a hydrofluoric acid type etchant to form a channel protective film 44.
Next, an n ⁺ -type a-Si layer and a metal electrode layer are formed, and an electrode layer, an n ⁺ -type a-Si layer, and a- are formed using a photoresist mask.
Etch the Si active semiconductor layer. For example, the three layers are etched by dry etching in which the etching gas is changed according to the object to be etched to form the operating semiconductor layer 43, the n ⁺ -type a-Si layer 45, the source electrode 46, and the drain electrode 47 having a predetermined pattern.

After that, an ITO film is formed and patterned to form a transparent pixel electrode 48, and the thin film transistor portion is covered with a passivation film 49.

[0020]

As described above, in the conventional technique, the storage capacitor electrode C1 is formed at the same time as the gate electrode 41 of the thin film transistor, and the gate insulating film 42 and the storage capacitor insulating film 42 are formed at the same time. Then, the ITO pixel electrode 48 was formed thereon.

In the wet etching process using a hydrofluoric acid-based etchant for patterning the protective film 44, the storage capacitor insulating film 42 is covered with the operating semiconductor layer, but if there is a pinhole in the operating semiconductor layer, hydrofluoric acid is used. The system etchant is the storage capacitor insulating film 4 on the storage capacitor electrode C1.
Attacks 2 and causes damage. As a result, insulation failure of the storage capacitor insulating film 42 occurs.

Further, the source electrode 46 and the drain electrode 4
7. In dry etching when patterning the semiconductor layers 45 and 43, the storage capacitor insulating film 42 is damaged by accelerated particles and the like, which also causes insulation failure.

The poor insulation of the storage capacitor insulating film 42 causes a current leak or short circuit between the storage capacitor electrode C1 and the pixel electrode 48 to cause a display defect. SUMMARY OF THE INVENTION It is an object of the present invention to provide a novel thin film transistor matrix device capable of reducing damage to the storage capacitor insulating film during an etching process during formation of a thin film transistor, and a method for manufacturing the same.

[0024]

In the thin film transistor matrix device of the present invention, a layer for protecting the storage capacitor insulating film from the effect of etching on the storage capacitor insulating film after forming the storage capacitor insulating film. Was established.

In the method of manufacturing the thin film transistor matrix device of the present invention, the layer for protecting the storage capacitor insulating film is formed at the same time as the step of forming the thin film transistor.

That is, the thin film transistor matrix device of the present invention is a thin film transistor matrix device in which a signal bus line, a gate bus line intersecting with the signal bus line, a thin film transistor, a storage capacitor electrode and a pixel electrode are formed on a transparent insulating substrate. The thin film transistor includes a gate electrode layer connected to the gate bus line, a gate insulating layer stacked on the gate electrode layer, an active layer arranged in contact with the gate insulating layer, and a pair of contacts on the active layer. A semiconductor layer including a layer, a protective film covering the active layer of the semiconductor layer, a source electrode layer connecting one of the contact layers to the signal bus line, and the other of the contact layers connecting to the pixel electrode. A drain electrode layer, and in a region where the storage capacitor electrode and the pixel electrode intersect, An insulating layer forming the common layer and the gate insulating layer on the product capacitor electrode, disposed thereon, and a protective layer forming the common layer and some other layers forming the thin film transistor.

Further, in the method of manufacturing a thin film transistor matrix device according to the present invention, a thin film transistor matrix in which a signal bus line, a gate bus line intersecting the signal bus line, a thin film transistor, a storage capacitor electrode and a pixel electrode are formed on a transparent insulating substrate. A method of manufacturing a device, wherein the thin film transistor, a gate electrode layer connected to the gate bus line, and the storage capacitor electrode are simultaneously formed on the transparent insulating substrate with the same material,
A step of forming a gate insulating layer covering the gate electrode and the storage capacitor electrode; a semiconductor layer including an active layer arranged in contact with the gate insulating layer in a portion of the thin film transistor, and a pair of contact layers thereon. A channel protection film that covers the active layer of the semiconductor layer, and an electrode layer that connects the pair of contact layers to the signal bus line and the pixel electrode are laminated, and at the same time, the storage capacitor electrode and the pixel electrode Forming a part of a layer forming the thin film transistor and a protective layer forming a common layer of a common material on the gate insulating layer in the intersection region.

[0028]

By forming a part of the stack above the gate insulating film forming the thin film transistor as a protective layer at the same time on the storage capacitor insulating film at the intersection between the storage capacitor electrode and the pixel electrode, The protective layer on the storage capacitor insulating film reduces damage to the storage capacitor insulating film due to the etching process when forming the thin film transistor.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A thin film transistor matrix device according to an embodiment of the present invention and a method for manufacturing the same will be described below in detail with reference to FIGS.

1 and 2 partially show a cross-sectional structure of a thin film transistor matrix device according to two embodiments of the present invention, and FIG. 3 partially shows a planar structure of a thin film transistor matrix device. 1 and 2 are both shown in FIG. 3B.
-Shows a cross section along line B. In the cross-sectional views of FIGS. 1 and 2, the cross section on the left side is the cross section of the thin film transistor region, and the right side is the cross section of the storage capacitor region.

The structure of the thin film transistor matrix device of the embodiment shown in FIG. 1 is basically the same as the conventional structure described in FIG.
That is, first, A is placed on the transparent insulating glass substrate 10.
A gate electrode 11 having a two-layer structure made of 1 and Ti is formed.

Further, a gate insulating film 12 having a two-layer structure of SiO ₂ and SiN is deposited thereon, and a is formed on the gate insulating film 12.
An operating semiconductor layer 13 made of —Si is formed, and a channel protective film 14 made of SiN is formed on the a-Si layer 13.

After patterning the protective film 14, an n ⁺ type a-Si film 15 and a two-layer structure of Al and Ti are in ohmic contact with the a-Si layer 13 via the n ⁺ type a-Si film 15. A source electrode 16 and a drain electrode 17 are formed.

Here, a photoresist mask is formed on the electrode layer to form the source electrode 16, the drain electrode 17, and a-S.
The i layers 13 and 15 are patterned by dry etching. After patterning, the photoresist mask is removed.

Further, an ITO transparent pixel electrode 18 is formed in contact with the drain electrode 17, and the entire thin film transistor region is covered with a passivation film 19 such as SiN.
The source electrode 16 is a source bus line (SB in FIG. 3).
1) is connected.

For the storage capacitor region on the right side of FIG. 1, the same material (Al) as the gate electrode 11 is formed on the transparent glass substrate 10.
And a two-layer structure of Ti) form the storage capacitor electrode 21 (corresponding to C1 in the plan view of FIG. 3). In addition, the same layer as the gate insulating film 12 of the thin film transistor (SiO ₂ and Si
An insulating film 22 for storage capacitance is formed on the storage electrode 21 in a two-layer structure of N).

An a-Si layer 23 and a SiN protective film 24, which are made of the same material as the a-Si layer 13 and the SiN protective film 14 of the thin film transistor, are formed and patterned on the storage capacitor insulating film 22. Further, a pixel electrode 18 is formed thereon so as to cover it. Pixel electrode 18 and storage capacitor electrode 2
The storage capacitor formed by 1 is electrically connected in parallel to a common electrode (not shown) facing the pixel electrode 18.

For example, the thickness of the gate insulating film 12 and the storage capacitor insulating film 22 on the gate electrode and the storage capacitor insulating film is about 3500Å, and the a-Si layer 13 thereon,
No. 23 has a thickness of about 250 Å, and has a SiN protective film 14 or 2
No. 4 has a thickness of about 1000Å. The a-Si layer 23 is i-type and substantially functions as an insulating layer.

Therefore, the distance between the storage capacitor electrode 21 and the ITO pixel electrode 18 is about 350 according to the conventional technique.
According to the present embodiment, the value of 0Å increases to about 4750Å.

For this reason, the capacity decreases, but the degree of decrease is less than 40%, which is not a serious adverse effect.
On the contrary, in the case of the present embodiment, as will be described in more detail later, the storage capacitor insulating film 22 is always protected from etching, and the insulation failure due to etching can be almost completely prevented.

Since the plan view of FIG. 3 is basically the same as that of FIG. 17, the basic structure will be described with reference to FIG.
Will be used instead, and redundant description will be omitted. However, in the structure of FIG. 3, the a-Si layer 23 and the SiN protective film 24 are shown in the hatched portion on the storage capacitor electrode 21 (C1).
Are formed, and this portion is different from the conventional one shown in FIG.

The a-Si layer 23 and the SiN protective film 24 formed on the storage capacitor electrode 21 (C1) protect the storage capacitor insulating film 22 from erosion by an etchant in the etching process of the channel protective film 14 of the thin film transistor. Layer. Also, the storage capacitor insulating film 22 is protected during the dry etching of the electrodes 16 and 17.

FIG. 2 shows a sectional structure of a thin film transistor matrix device according to another embodiment of the present invention. The thin film transistor area is the same as in FIG. 1 and its description is omitted.
In the storage capacitance region, a storage capacitance electrode 21 (corresponding to C1 in the plan view of FIG. 3) is formed on the transparent glass substrate 10 with the same material as the gate electrode 11 (two-layer structure of Al and Ti). There is.

Further, the gate insulating film 1 of the thin film transistor
The storage capacitor insulating film 22 is formed on the storage electrode 21 in the same layer as that of No. ₂ (two-layer structure of SiO ₂ and SiN). Up to this point, the process is similar to that of FIG.

Further, n is formed on the storage capacitor insulating film 22 in the same layer as the contact semiconductor layer 15 of the thin film transistor.
^{A +} -type a-Si layer 25 is formed and is formed in the same layer as the source / drain electrode layers 16 and 17 having a two-layer structure of Al and Ti.
A metal film layer 26 having a two-layer structure made of 1 and Ti is formed, and the pixel electrode 18 is formed thereon.

In this embodiment, the n ⁺ -type a-Si layer 25 and the Ti metal film layer 26 formed in the hatched portion on the storage capacitor electrode 21 in the plan view of FIG. 3 are the electrodes 16, 17 of the thin film transistor. And the like serve as a layer for protecting the storage capacitor insulating film 22 from accelerated ions in the dry etching process.

In the etching of the channel protective film 14, if there is a pinhole in the a-Si layer, the storage capacitor insulating film 2
2 may be eroded, but the a-Si layer 25 is conductive, and the storage capacitance can be maintained at a value similar to that in the conventional case.

Next, a method of manufacturing the thin film transistor matrix device of the embodiment shown in FIGS. 1 and 2 will be described with reference to FIGS.
Will be described. In FIGS. 4 to 16, the left side is the thin film transistor area and the right side is the storage capacity area.

First, a method of manufacturing the thin film transistor matrix device of the embodiment shown in FIG. 1 will be described. The transparent glass substrate 10 is placed in a vacuum container of a magnetron sputtering device (not shown). The magnetron sputtering apparatus has a substrate parallel movement type and a facing target type magnetron sputtering electrode, and is capable of heating the substrate temperature up to 250 ° C.

The glass substrate 10 is heated to 250 ° C., the inside of the vacuum container is set to an Ar (argon) gas atmosphere at a pressure of about 0.005 torr, and Al as a vapor deposition source is sputtered by the facing target sputtering method, as shown in FIG. Then, an Al layer 111 is formed on the surface of the substrate 10 to a film thickness of about 500 Å. Note that if an alumina film is formed on the surface of the glass substrate 10 in advance, the familiarity with the Al layer is improved.

Next, the gate electrode, the gate bus lines GB1 and GB2, and the storage capacitor electrode 21 (C
Resist films 101 and 102 are formed in the pattern of 1). Next, the Al layer 111 is etched with a phosphoric acid-based etchant using the resist films 101 and 102 as masks to obtain an Al pattern. After removing the resist films 101 and 102, as shown in FIG. 5, the Al layer 111 which is the first layer of the gate electrode 11 and the storage capacitor electrode 21 is covered, and a Ti layer 112 is sputtered thereon to a thickness of about 800 Å.
To form a film.

Further, resist films 103 and 104 having patterns of the gate electrode 11 and the storage capacitor electrode 21 are formed thereon. For example, a photoresist layer is applied and exposed so as to completely cover the Al bus line.

After that, reactive ion etching is performed by using the resist films 103 and 104 as masks and BCl ₃ + Cl ₂ mixed gas as an etching gas to remove the Ti layer 112 other than the mask pattern and remove the A layer as shown in FIG.
A gate electrode 11 and a storage capacitor electrode 21 having a two-layer structure of 1 and Ti are formed.

Next, as shown in FIG. 7, P (plasma)
-SiO ₂ film 12 as a gate insulating film by the CVD method
1. The SiN film 122 is laminated, and further, the a-Si film 131 as the operating semiconductor film and the SiN film 141 as the protective film are continuously deposited. After that, the SiO ₂ film 121 and the SiN film 12
The two-layer structure with 2 is represented as the gate insulating film 12 and the storage capacitor insulating film 22.

Further, a resist film 105 having a pattern for defining a channel region on the SiN film 141 of FIG. 7 and a resist film 106 having a pattern for defining a protective layer of a storage capacitor insulating film on the storage capacitor electrode 21 are simultaneously formed. Form.

These resist films 105 and 106 are exposed to the back surface from the glass substrate 10 side once to expose a pattern self-aligned with the gate electrode 11 and the storage capacitor electrode 21, and then from the front surface side to the gate bus line and its surroundings. It is created by exposing a region having a width of several μm. In this way, the resist films 105 and 106 are formed in a self-aligned manner so as to overlap the gate electrode 11 and the storage capacitor electrode 21.

After that, the SiN film 141 other than the mask is removed by etching using a hydrofluoric acid type etchant with the resist films 105 and 106 as a mask, and the channel protection film 14 and the storage capacitor electrode of the thin film transistor are removed as shown in FIG. And the protective film 24 is left.

Further, after removing the resist films 105 and 106, the surfaces of the SiN protective films 14 and 24 are cleaned by light etching using a hydrofluoric acid type etchant to remove the oxide films.

In this etching process, the storage capacitor insulating film 22 on the storage capacitor electrode 21 is covered with the a-Si layer 131.
Not only is it covered with the SiN film 24 and the resist film 106, but even if some of these layers have pinholes, they are not easily eroded by the etchant.

Then, as shown in FIG. 9, an n ⁺ -type a-S is formed by the P-CVD method of SiH ₄ doped with PH _3.
The i film 115 is formed, and then the source of the thin film transistor
A Ti film 161 and an Al film 162 to be drain electrodes are formed by a sputtering method.

Also in the etching process in the subsequent steps, the storage capacitor insulating film 22 is formed on the a-Si film 11 formed thereon.
Since it is also protected by 5 and the protective film 24, it is protected from damage by accelerated ions and etchants.

Subsequently, the source electrode 16 and the drain electrode 1
No. 7 electrode forming pattern resist film 107 is Al film 1
It is formed on the surface 62 and is used as a mask
The I film 162 is removed by etching with a phosphoric acid-based etchant.

Further, the Ti film 161, the n ⁺ -type a-Si film 115 and the a-Si film 131 under the Al film are BCl ₃ + C.
When the reactive ion etching is performed using the l ₂ mixed gas as an etching gas to remove the mixed gas, a structure as shown in FIG. 10 is obtained.

In this process, since no resist is formed on the Al film 162 on the storage capacitor electrode 21, the SiN protective film 24 is exposed in the storage capacitor portion as shown in FIG. 10, and Al and Ti are formed in the thin film transistor portion. Thus, the source electrode 16 and the drain electrode 17 having a two-layer structure are formed, and the gate insulating film 12 remains on the entire surface of the (storage capacitor insulating film 22). Both the source electrode 16 and the drain electrode 17 have a two-layer structure of a Ti film 161 and an Al film 162.

Then, as shown in FIG. 1, the drain electrode 1
The pixel electrode 18 made of ITO is formed in contact with the electrode 7, and the gate insulating film in the gate terminal portion is removed by chemical dry etching. After that, S is formed by P-CVD as a protective film 19 so as to cover the thin film transistor region.
The thin film transistor matrix device of FIG. 1 is completed by masking the iN film.

Next, a method of manufacturing the thin film transistor matrix device of FIG. 2 will be described. The first half step of the manufacturing method for manufacturing the structure of FIG. 2 is the same as the step of FIG. 4 described in the manufacturing method of the structure of FIG. 1 to the step of forming the SiN film 141 before forming the resist film of FIG. is there. Therefore,
The structure method will be described with reference to FIGS. 11 to 16 in the latter half of the manufacturing process after the manufacturing process of FIG.

As shown in FIG. 11, the gate insulating film 12 is formed on the entire surface of the substrate 10 covering the gate electrode 11 by the P-CVD method.
And the SiO ₂ film 121, S as the storage capacitor insulating film 22.
After continuously depositing two layers of the iN film 122, an a-Si film 131 as an operating semiconductor film, and a SiN film 141 as a protective film, a resist film having a pattern for defining a channel region on the SiN film 141. Form 105.

The resist film 105 is formed by the self-alignment exposure from the back surface and the contour exposure from the surface in the same manner as the above-described manufacturing method, and has a gap of several microns from the gate bus line and is self-aligned so as to overlap the gate electrode 11. It is patterned by alignment. Note that the difference from the configuration of FIG. 1 (FIG. 7) is that the resist film is not formed on the SiN film 141 of the storage capacitor portion (right side of FIG. 11).

After that, the SiN film 141 other than the mask is etched and removed using the hydrofluoric acid type etchant with the resist film 105 as a mask to form the channel protection film 14 of the thin film transistor as shown in FIG.

In this etching, the storage capacitor insulating film 22 on the storage capacitor electrode 21 is covered only by the a-Si film 131, and if there are pinholes in the a-Si film 131, they are eroded by the etchant. There is a risk. However, this risk is similar to the conventional technique.

However, in the subsequent steps, since another film, for example, the a-Si film 23, is always formed on the storage capacitor insulating film 22, the storage capacitor insulating film is protected from damage due to accelerated ions or etchant in the etching process. Membrane 22
Can be protected.

Next, after removing the resist film 105, the surface of the SiN protective film 14 is removed by performing a slight etching with a hydrofluoric acid-based etchant to expose a clean surface. Then, as shown in FIG. 13, an n ⁺ -type a-Si film 115 is formed by the P-CVD method of SiH ₄ doped with PH ₃ .

From this n ⁺ type a-Si film 115 to a-Si
When the impurities diffuse into the film 131, a conductor is arranged on the storage capacitor insulating film 22. Ti, which should be the source and drain electrodes of the thin film transistor,
The film 161 is formed by a sputtering method.

Then, as shown in FIG. 14, the intersection (hatched region in FIG. 3) of the resist film 108 of the electrode forming pattern of the source electrode 16 and the drain electrode 17 and the pixel electrode above the storage capacitor electrode 21 is formed. Resist film 1 to cover
09 is formed on the Ti film 161, and the Ti film 161 and the n ⁺ -type a-Si film 115 other than the mask are formed using this as a mask.
The a-Si layer 131 is removed by reactive ion etching using a BCl ₃ + Cl ₂ mixed gas as an etching gas.

After that, the resist films 108 and 109 are removed, and as shown in FIG. 15, an Al film 162 is formed by a sputtering method, and then a resist film 110 having a pattern of source / drain electrodes is formed. No resist film is formed on the storage capacitor portion.

Also in the subsequent steps, the storage capacitor insulating film 2
2 on the a-Si film 23, the n ⁺ -type a-Si film 115,
Since the Ti film 161 is covered, the storage capacitor insulating film 22 can be protected from damage by the etchant in the etching process.

Next, as shown in FIG. 16, the resist film 1
The Al film 162 is etched with a phosphoric acid-based etchant using 10 as a mask to form the source electrode 16 and the drain electrode 17, and the Al film 162 in the storage capacitor portion is also removed.

In this step, the insulating film on the storage capacitor electrode 21 is
On top of 22, a-Si layer 23, n ⁺Type a-Si film 2
5, the metal film 26 is formed by the remaining Ti film 161
The gate insulating film 12 and the storage capacitor insulating film 22 remain on the entire surface.
It will be.

Then, as shown in FIG. 2, the drain electrode 1
The pixel electrode 18 made of ITO is formed in contact with the electrode 7, and the gate insulating film in the gate terminal portion is removed by chemical dry etching. Then, the thin film transistor matrix device of FIG. 2 is completed by mask deposition using the SiN film as the protective film 19 by P-CVD so as to cover the thin film transistor region.

In the manufacturing method described above, a plurality of types of insulating films can be continuously formed by using an apparatus as shown in FIG. For example, an Al ₂ O ₃ film and a SiN film can be continuously formed as the gate insulating film 12 and the storage capacitor insulating film 22.

In FIG. 19, trimethylaluminum (TMA) is provided on the outer periphery of the cylindrical container 51 at 90 ° intervals.
Nozzle 52, ammonia nozzle 53, dimethylsilane (DMS) nozzle 54, and H ₂ O nozzle 55 are arranged in the axial direction, and four heaters 55 are arranged between them.

A polygonal columnar susceptor 57 is rotatably arranged around a rotary shaft 58 in the center, and a plurality of glass substrates 59 are placed on the susceptor 57. Evacuate the inside of the container 51 once,
The glass substrate 59 is rotated by the heater 55 while rotating the susceptor 57.
Is heated to a predetermined temperature. Supplying TMA from TMA nozzle 52, supplies of H ₂ O from H ₂ O nozzle 55, when a plasma is generated, can be deposited an Al ₂ O ₃ film. A SiO ₂ film can be deposited by using the DMS nozzle 54 and the H ₂ O nozzle 55, and a SiN film can be deposited by using the DMS nozzle 54 and the ammonia nozzle 53.

Various films can be deposited by changing the source gas. The planar configuration of the thin film transistor matrix device is not limited to that shown in FIG. For example, a plane structure as shown in FIG. 20 can be used. The pixel electrode 18 is formed so as to overlap the gate bus line GB2 for the adjacent column to form a storage capacitor. Since the storage capacitor electrode can be omitted, the aperture ratio can be improved.

If the thin film transistor matrix device described above is combined with the other substrate on which the common electrode is formed while sandwiching the liquid crystal layer, an active matrix type liquid crystal display device is obtained.

The thin film transistor matrix device and the method of manufacturing the same according to the present invention are not limited to the above-described embodiments, and those skilled in the art can easily make other applications, changes, combinations and the like from the disclosed contents. I will let you.

[0086]

EFFECTS OF THE INVENTION By forming a part of each layer forming a thin film transistor as a protective layer at the same time on the storage capacitor insulating film at the intersection between the storage capacitor electrode and the pixel electrode, the storage capacitor insulating film is formed. The protective layer on the film reduces damage to the storage capacitor insulating film due to the etching process when forming the thin film transistor.

Therefore, it is possible to reduce a current leak or a short circuit between the storage capacitor electrode and the pixel electrode due to the insulation failure of the insulating film and reduce the display failure due to the insulation failure, and to obtain a highly reliable liquid crystal display device. You can

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a thin film transistor matrix device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a thin film transistor matrix device according to another embodiment of the present invention.

FIG. 3 is a plan view of a thin film transistor matrix device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process in a method of manufacturing a thin film transistor matrix device according to an example of the present invention.

FIG. 5 is a cross-sectional view for explaining the manufacturing process subsequent to FIG.

6 is a cross-sectional view for explaining the manufacturing process subsequent to FIG.

FIG. 7 is a cross-sectional view for explaining the manufacturing process subsequent to FIG.

FIG. 8 is a cross-sectional view for explaining the manufacturing process continued from FIG.

9 is a cross-sectional view for explaining the manufacturing process subsequent to FIG.

FIG. 10 is a cross-sectional view for explaining the manufacturing process continued from FIG.

FIG. 11 is a cross-sectional view illustrating a manufacturing step in a method of manufacturing a thin film transistor matrix device according to another embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining the manufacturing process continued from FIG.

FIG. 13 is a cross-sectional view for explaining the manufacturing process continued from FIG.

FIG. 14 is a cross-sectional view for explaining the manufacturing process continued from FIG.

FIG. 15 is a cross-sectional view for explaining the manufacturing process continued from FIG.

16 is a cross-sectional view for explaining the manufacturing process subsequent to FIG.

FIG. 17 is a plan view of a conventional thin film transistor matrix device.

FIG. 18 is a cross-sectional view of a conventional thin film transistor matrix device.

FIG. 19 is a schematic sectional view showing an example of a CVD apparatus.

FIG. 20 is a plan view of a thin film transistor matrix device according to another embodiment of the present invention.

[Explanation of symbols]

10 ... Transparent glass substrate 11 ... Gate electrode 12 ... Gate insulating film 13 ... a-Si layer 14 ... SiN protective film 15 ... N ⁺ type a-Si film 16 ... Source electrode 17 ... Drain electrode 18 ... ITO pixel electrode 19 ... Protective film 21 ... Storage capacitor electrode 22 ... Insulating film for storage capacitor 23 ... a-Si layer 24 ... SiN protective film 25 ... n ⁺ type a-Si film 26 ... Metal film

Claims (6)

[Claims] 1. A signal bus line and a gate bus line (G) intersecting the signal bus line on a transparent insulating substrate (10).
B1 and GB2 ...) and thin film transistors (T1 and T2)
...), a storage capacitor electrode (21), and a pixel electrode (18), wherein the thin film transistor includes a gate electrode layer (11) connected to the gate bus line, and the gate electrode. A semiconductor layer (13, 15) including a gate insulating layer (12) laminated on the layer, an active layer (13) arranged in contact with the gate insulating layer, and a pair of contact layers (15) thereon. A protective film (14) covering the active layer (13) of the semiconductor layer,
A source electrode layer (16) connecting one of the contact layers (15) to the signal bus line, and a drain electrode layer (17) connecting the other of the contact layers (15) to the pixel electrodes, In the intersection region of the storage capacitor electrode (21) and the pixel electrode (18), an insulating layer (22) which is a layer common to the gate insulating layer (12) is formed on the storage capacitor electrode, and A protective layer (23, 24; 23, 2) that is disposed and forms a common layer with a part of other layers forming the thin film transistor.
5, 26) and a thin film transistor matrix device. 2. The protective layer (23, 24) is an active layer (13) of the semiconductor layer and the channel protective film (14).
The thin film transistor matrix device according to claim 1, comprising a stack of a semiconductor layer (23) and a protective film (24) which are in common with the above. 3. The protective layer (23, 25, 26) is the semiconductor layer (13, 15) and the drain electrode layer (1).
7. The thin film transistor matrix device according to claim 1, comprising a stack of 7) or a semiconductor layer (23, 25) and a metal layer (26) forming a common layer with the source electrode layer (16). 4. A signal bus line and a gate bus line (G) crossing the signal bus line on a transparent insulating substrate (10).
B1 and GB2 ...) and thin film transistors (T1 and T2)
...), a storage capacitor electrode (21) and a pixel electrode (18) are formed, the method comprising: a gate electrode layer (11) connected to the gate bus line of the thin film transistor; The storage capacitor electrode (2
(1) and the same material are simultaneously formed on the transparent insulating substrate (10), and a gate insulating layer (12, 22) is formed so as to cover the gate electrode (11) and the storage capacitor electrode (21). And a semiconductor layer (13, 15) including an active layer (13) disposed in contact with the gate insulating layer at a portion of the thin film transistor and a pair of contact layers (15) thereon, and the semiconductor layer (15). A channel protective film (1 covering the active layer (13)
4) and an electrode layer (16, 16) connecting the pair of contact layers to the signal bus line and the pixel electrode (18).
17) and at the same time when the storage capacitor electrode (2
1) and a protective layer (23, which forms a common layer with a material common to a part of a layer forming the thin film transistor on the gate insulating layer (12) at an intersection region of the pixel electrode (18).
24; 23, 25, 26), and a method of manufacturing a thin film transistor matrix device. 5. A semiconductor layer (2) is also formed above the storage capacitor electrode (21) in a common layer simultaneously with the step of laminating the active layer (13) of the semiconductor layer and the channel protection film (14).
3) and the protective film (24) are laminated to form the protective layer (23, 2).
4. The method of manufacturing a thin film transistor matrix device according to claim 4, wherein the method 4) is formed. 6. A semiconductor layer (23, 25) and a metal film are also formed above the storage capacitor electrode in a common layer at the same time as the step of stacking the semiconductor layer (13, 15) and the electrode layer (16, 17). (26) are laminated to form the protective layer (23, 25, 2
6. The method of manufacturing a thin film transistor matrix device according to claim 4, wherein the method 6) is formed.