JP2010197927A - Method of manufacturing electrooptical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an electrooptical device, reducing contact resistance between a metal wire having a surface layer made of Ti and a conductive member even when a silicon nitride film formed by plasma CVD process is used as an insulating film formed on the surface of the metal wire. <P>SOLUTION: The method of manufacturing an electrooptical device includes a step of forming, on the surface of the metal wires 17, 18 having at least a surface layer made of Ti, a first insulating film 37a or 38a and then a second insulating film 37b or 38b made of silicon nitride by means of plasma CVD, and forming contact holes 51, 52 in the second insulating film 37b or 38b and the first insulating film 37a or 38a to expose the surface made of Ti of the metal wire 17, 18. The first insulating film 37a or 38a is formed of a material which does not form ball-like silicon nitride when forming the second insulating film 37b or 38b made of silicon nitride. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a liquid crystal display device, organic electroluminescence (EL).
e) The present invention relates to a method for manufacturing an electro-optical device such as a display device, a plasma display device, an electrophoretic display device, and a field emission display. Specifically, in the present invention, the surface layer is titanium (Ti
Plasma chemical vapor deposition (CVD) on the surface of metal wiring consisting of
n) When the insulating film made of silicon nitride is formed by the method, the ball-shaped silicon nitride is not formed when the surface of the metal wiring made of Ti is exposed so that the ball-shaped silicon nitride is not formed. The present invention relates to a method for manufacturing the electro-optical device.

An active matrix type electro-optical device such as a liquid crystal display device, an organic EL display device, or a plasma display device has a thin film transistor (TFT) as a switching element.
stor). In an active matrix electro-optical device, metal wiring is patterned on at least a substrate by photolithography. As the metal wiring, for example, signal lines and scanning lines arranged in a matrix and partitioning the display region into each pixel, routing wirings and common wirings of these signal lines and scanning lines, TFT gate electrodes, source electrodes, Examples include drain electrodes, driver IC connection terminals, inspection terminals, and external connection terminals. In addition, an inorganic insulating film such as a gate insulating film or a passivation film is formed on the surfaces of these metal wirings and various electrodes and terminals for the purpose of insulating and protecting these metal wirings and various electrodes.

As a material of the inorganic insulating film covering the surface of the metal wiring, for example, silicon nitride (SiNx)
Although silicon oxide (SiOx) is employed, silicon nitride is mainly used from the viewpoint of insulation. As a method of forming such an insulating film made of silicon nitride, plasma CV
The D method is widely used. In the plasma CVD method, gaseous silicon compounds such as disilane (Si ₂ H ₆ ) and silane (SiH ₄ ) that are circulated in a vacuum vessel under reduced pressure conditions and ammonia (N
This is a method of depositing silicon nitride on the surface of an object by applying plasma generation energy to a mixed atmosphere gas with a gaseous nitrogen-containing compound such as H ₃ ) to promote reaction and decomposition of the mixed atmosphere gas.

In this manner, contact holes are appropriately formed in the silicon nitride film formed by the plasma CVD method. This contact hole partially exposes the surface of the underlying metal wiring, and through this contact hole, a metal film, ITO (
This is for establishing an electrical connection between a conductive member such as Indium Tin Oxide) or IZO (Indium Zinc Oxide) and a metal wiring. The contact hole formed in the silicon nitride film can be formed by a wet etching method or a dry etching method. However, when the plasma CVD method is employed as a method for forming the silicon nitride film, the same plasma equipment can be used. In general, a plasma etching method which is a kind of dry etching method is employed. The dry etching method can perform finer processing than the wet etching method, and has an advantage that a cleaning process as a post-process is unnecessary.

On the other hand, as a material of the metal wiring covered with the silicon nitride film, for example, aluminum (Al
), Al alloy, chromium (Cr), molybdenum (Mo), Ti and the like are used, and Al or Al alloy is mainly used as the base material from the viewpoint of conductivity and manufacturing cost. Furthermore, on the surface of these metal wirings, Ti or Mo is formed on the surface of the Al or Al alloy layer in order to prevent the oxidation of the Al or Al alloy layer, to suppress the formation of minute protrusions called hillocks or to suppress the formation of pinholes. It is done to coat with. Since Al or Al alloy has low adhesion to the silicon nitride layer, when an Al or Al alloy layer is formed on the surface of the silicon nitride layer, between the Al or Al alloy layer and the silicon nitride layer. Ti layer or Mo layer is arranged, Ti / Al or Al alloy / T
i, or a three-layer structure of Mo / Al or Al alloy / Mo is often used (see Patent Documents 1 and 2 below).

JP 2006-309028 A JP 2008-242086 A

As described above, as the metal wiring, the surface layer of Al or Al alloy is often covered with Mo or Ti, but both have advantages and disadvantages. That is, the Mo system is easy to wet-etch, and the surface film formed by the etching atmosphere becomes a hydroxide film and can be easily removed by washing with water, etc., but it is difficult to miniaturize because dry etching is difficult. . On the other hand, Ti-based materials are easy to oxidize, but are easy to dry etch and suitable for miniaturization.

However, when a silicon nitride film is formed on the surface of a metal wiring whose surface layer is a Ti layer by a plasma CVD method, a contact hole is formed in the silicon nitride film, and the metal wiring and the conductive material are formed through the contact hole. It was found that the contact resistance between the two increases when electrical continuity is established between them. Such a phenomenon does not occur when a silicon nitride film is formed by the plasma CVD method on the surface of the metal wiring whose surface is a Mo layer,
This occurs specifically when the surface layer of the metal wiring is a Ti layer.

The inventors have conducted various studies on the cause of this phenomenon, and as a result, the silicon nitride film contains ball-like silicon nitride that has grown abnormally. The silicon nitride film is etched to form contact holes. However, the present inventors have found that this ball-shaped silicon nitride is due to remaining on the surface of the Ti layer. This phenomenon will be described with reference to FIG.

FIG. 9 is an enlarged cross-sectional view when a silicon nitride SiNx film is formed on the surface of a metal wiring ML having a two-layer structure in which a Ti layer is laminated on an Al layer by a plasma CVD method.

As shown in FIG. 9, a Ti layer is formed on the surface of the Al layer, and a SiNx film is formed on the surface of the Ti layer. The SiNx film has silicon nitride 100 developed in a ball shape. Is recognized. In this state, when contact holes are formed in the SiNx film by a plasma etching method which is a kind of dry etching method, the ball-shaped silicon nitride 100 may remain on the surface of the Ti layer as an etching residue. Then, since the insulating ball-shaped silicon nitride 100 is sandwiched between the Ti material and the conductive material such as ITO or IZO formed in the contact hole, the metal wiring and the metallic material It is presumed that the electrical resistance between the conductive member such as ITO or IZO becomes large.

The present invention has been made in view of the problems of the prior art as described above.
Even if a silicon nitride film is formed as an insulating film on the surface of a metal wiring whose surface layer is made of Ti, the formation of granular silicon nitride is suppressed, and the contact resistance between the metal wiring and the conductive member is small. It is to provide a method for manufacturing an apparatus.

In order to achieve the above object, at least the surface layer of the electro-optical device manufacturing method of the present invention is Ti.
A second insulating film made of silicon nitride is formed on the surface of the metal wiring made of silicon nitride by plasma CVD, and then a plasma etching is performed on the second insulating film and the first insulating film. A method of manufacturing an electro-optical device comprising a step of forming a contact hole by a method and exposing a surface of a metal wiring made of Ti, wherein the first insulating film is a second insulating film made of silicon nitride It is characterized in that it is made of a material that does not form ball-shaped silicon nitride at the time of forming.

In the method for manufacturing the electro-optical device according to the present invention, the first insulating film is formed on the surface of the metal wiring having at least a surface layer made of Ti by the plasma CVD method, and then the second insulating film made of silicon nitride is formed. However, the first insulating film is formed of a material that does not form ball-shaped silicon nitride when forming the second insulating film. Therefore, when contact holes are formed in the first insulating film and the second insulating film by plasma etching, since the ball-shaped silicon nitride is not formed, the surface of the homogeneous Ti layer can be exposed. . Therefore, according to the method of manufacturing the electro-optical device of the present invention, the metal material, ITO or IZO is transmitted through the contact hole.
Even if the conductive material such as the conductive material is electrically connected to the metal wiring, the contact resistance between the metal wiring and the conductive material is not increased. Note that the first insulating film may be thinner than the second insulating film because the Ti layer on the surface layer of the metal wiring is not exposed when the second insulating film is formed.

In the electro-optical device manufacturing method of the present invention, the first insulating film is nitrided by deposition under a deposition condition having a deposition rate slower than that of the second insulation film made of silicon nitride. It is preferable to form from silicon.

Assuming that the first insulating film is made of silicon nitride deposited under film forming conditions whose deposition rate is slower than the film forming condition of the second insulating film made of silicon nitride, the first insulating film contains balls. It is difficult to form silicon nitride. Therefore, when the second insulating film made of silicon nitride is formed, the first
Even if the deposition rate is made faster than the film formation conditions of this insulating film, since the Ti layer is not exposed, the formation of ball-shaped silicon nitride is suppressed. Therefore, according to the method of manufacturing the electro-optical device of the invention,
An electro-optical device that can effectively exhibit the above-described effects can be obtained.

In the method of manufacturing the electro-optical device according to the aspect of the invention, it is preferable that the first insulating film is formed with a power smaller than the power for generating plasma when the second insulating film made of silicon nitride is formed. .

The power for plasma generation in the plasma CVD method can be easily increased or decreased. If the power for plasma generation is reduced, the plasma reaction conditions become mild and the film formation rate becomes slow. Therefore, according to the electro-optical device manufacturing method of the present invention, even if the first insulating film is made of a silicon nitride film formed by plasma CVD, the formation of ball-shaped silicon nitride can be easily suppressed. An electro-optical device that can easily achieve the above-described effects can be manufactured.

In the method of manufacturing the electro-optical device according to the aspect of the invention, the first insulating film may be a flow rate or partial pressure of a gaseous silicon raw material in a raw material gas when forming the second insulating film made of silicon nitride. It is preferable that the flow rate or partial pressure be small.

If the flow rate or partial pressure of the gaseous silicon raw material in the raw material gas in the plasma CVD method is made smaller than the normal film forming conditions, the plasma reaction conditions become mild and the film forming speed becomes slow. Therefore, according to the method of manufacturing the electro-optical device of the present invention, even if the first insulating film is made of a silicon nitride film formed by plasma CVD, the formation of ball-shaped silicon nitride can be suppressed. An electro-optical device that can achieve the above-described effects can be manufactured. In addition, as a gaseous silicon material, monosilane, disilane, etc. can be selected suitably, and can be used. Moreover, inexpensive nitrogen and ammonia gas can be used as the nitrogen raw material for forming silicon nitride.

In the method for manufacturing the electro-optical device according to the aspect of the invention, the first insulating film can be formed of silicon oxide.

Even if a silicon nitride film is formed on the surface of the silicon oxide film by plasma CVD, it is difficult to form ball-shaped silicon nitride. Therefore, according to the method for manufacturing an electro-optical device of the present invention, it is possible to manufacture an electro-optical device that can easily achieve the above effects.

Note that the Ti layer on the surface layer of the metal wiring has low selectivity with respect to plasma etching, and may be scraped if overetched. However, when a silicon oxide layer is laminated on the surface of the metal wiring, this silicon oxide layer acts as a stopper layer during plasma etching of the silicon nitride layer of the second insulating film, so that the second insulating film is over-etched. However, the Ti layer is not scraped off. This silicon oxide layer can be etched by two-stage etching by changing the etching gas as compared with the plasma etching of the silicon nitride layer, or by wet etching with dilute hydrofluoric acid or buffered hydrofluoric acid solution.

In the electro-optical device manufacturing method of the present invention, the metal wiring having at least a surface layer made of Ti has the same insulation as a gate insulating film covering a surface of a gate electrode of a thin film transistor as a switching element of the electro-optical device. It can be formed on the surface of the film.

A source wiring, a source electrode, a drain electrode, and the like are formed on the surface of the gate insulating film. An insulating film (passivation film) is formed on these surfaces, and the passivation film on the terminal portion of the source wiring and the drain electrode is formed. Contact holes are formed. In the method for manufacturing an electro-optical device according to the present invention, the source wiring and the drain electrode correspond to a metal wiring having at least a surface layer made of Ti, and the passivation film corresponds to the first insulating film and the second insulating film.
Therefore, according to the method for manufacturing an electro-optical device of the present invention, a metal wiring having at least a surface layer made of Ti can be formed simultaneously with a source electrode, a drain electrode, and a signal line of a TFT as a switching element. An electro-optical device that can achieve the above-described effects can be obtained.

It is a top view which shows a schematic structure of a liquid crystal display panel through a color filter substrate in common with 1st Embodiment and 2nd Embodiment. It is sectional drawing of the II-II line of FIG. FIG. 3 is a plan view of one sub-pixel represented by seeing through a color filter substrate of the liquid crystal display panel of the first embodiment. It is sectional drawing of the IV-IV line of FIG. It is a schematic plan view which shows an example of arrangement | positioning relationship of the gate wiring electrode terminal of an array substrate, and the source wiring terminal. 6A is a cross-sectional view taken along line VIA-VIA in FIG. 5, and FIG. 6B is a cross-sectional view taken along line VIB-VIB in FIG. It is sectional drawing which showed the manufacturing process of the array substrate of 1st Embodiment later on. FIG. 8 is a cross-sectional view sequentially showing the array substrate manufacturing process subsequent to FIG. 7. It is the elements on larger scale of the board | substrate which coat | covered the silicon nitride film by the plasma CVD method on the surface of the metal wiring of the 2 layer structure which laminates | stacks Ti layer on Al layer.

Embodiments of the present invention will be described with reference to the embodiment and the drawings, taking the case of a liquid crystal display panel as an example. The embodiments shown below are not intended to limit the invention to those described herein. The present invention is not limited to the technical idea as long as it does not depart from the technical idea shown in the claims.
The present invention can be equally applied to electro-optical devices such as L display devices, plasma display devices, electrophoretic display devices, and field emission displays. In each drawing used for the description in this specification, each layer and each member are displayed in different scales so that each layer and each member can be recognized on the drawing. However, it is not necessarily displayed in proportion to the actual dimensions.

[First Embodiment]
The liquid crystal display panel 10 of the first embodiment is a TN mode transmissive liquid crystal display panel, and the configuration of the main part thereof will be described with reference to FIGS.

As shown in FIGS. 1 and 2, the liquid crystal display panel 10 includes an array substrate AR and a color filter substrate CF. On the first transparent substrate 11 (array substrate AR) made of a transparent material such as glass, a plurality of scanning lines and signal lines are formed in a matrix in the display area 12, and each is divided by the scanning lines and the signal lines. These regions form sub-pixels. A pixel electrode is formed for each subpixel, and a TFT as a switching element connected to the pixel electrode is formed in the vicinity of the intersection of the scanning line and the signal line. These metal lines such as scanning lines and signal lines, T
The specific configurations of the FT and the pixel electrode will be described in detail later, but these are schematically shown as the first structure 13 in FIG.

A driver IC 14 for driving the liquid crystal display panel 10 is disposed on the short side (the lower end in FIG. 1) of the first transparent substrate 11. The driver IC 14 may be placed on the long side (left and right ends in FIG. 1). In the case of a medium-sized or large-sized liquid crystal display panel,
In some cases, the driver IC 14 is separately mounted on a flexible wiring board or the like and electrically connected to the first transparent substrate 11. In addition, for example, four transfer electrodes 15 are provided at the four corners of the first transparent substrate 11 and are directly connected to each other or the driver I via the common wiring 16.
They are configured to be connected to each other in C14 to have the same potential. Further, the scanning line is connected to a scanning line 17 for the scanning line, and the signal line is connected to a routing line 18 for the signal line. The ends of the scanning wiring 17 and the signal wiring 18 are connected to the gate wiring terminal 41 and the source wiring terminal 42 (FIGS. 5 and 6) formed in the driver IC mounting region, respectively. And the gate wiring terminal 41 and the source wiring terminal 42 are connected to the connection terminal, the inspection terminal or the external connection terminal 1 of the driver IC 14.
Nine.

Note that the scanning line routing wiring 17 does not necessarily mean wiring formed simultaneously with the scanning line, and the signal line routing wiring 18 does not necessarily mean wiring formed simultaneously with the signal line. Absent. However, for the sake of simplicity, the following description assumes that the scanning line routing wiring 17 is a “gate wiring 17” formed simultaneously with the scanning line.
In the following description, it is assumed that the signal line routing wiring 18 is the “source wiring 18” formed simultaneously with the signal line.

2 and 4, the color filter substrate CF has a color filter layer and a light shielding member such as a black matrix on the second transparent substrate 20 made of a transparent material such as glass. The color filter layer is provided with a colored layer corresponding to each sub-pixel.
It arrange | positions so that the pixel electrode of the transparent substrate 11 may be opposed. The light shielding member is disposed at a position corresponding to at least the TFT, the scanning line, and the signal line of the first transparent substrate 11. Although a specific configuration of these color filter layers and the like is omitted, these are schematically shown as the second structure 21 in FIGS. A counter electrode (common electrode) 22 made of a transparent conductive material such as ITO or IZO is further arranged on the second transparent substrate 20 so as to face the display region 12 of the array substrate AR.

A sealing material 23 is applied around the display area 12 of the first transparent substrate 11 except for a liquid crystal injection port (not shown), and a contact material (not shown) is applied on the transfer electrode 15 to counter the electrode. 22 is electrically connected. The seal material 23 is made of, for example, a thermosetting resin such as an epoxy resin, a photo-curing resin, or the like, and is mixed with an insulating filler as necessary. It is a mixture of conductors. Liquid crystal is sealed between the substrates.

Here, a specific configuration of the array substrate AR will be described with reference to FIGS. Array substrate A
R denotes a plurality of scanning lines 31 and signal lines 32 formed in a matrix on the liquid crystal layer 24 side of the first transparent substrate 11 with the first transparent substrate 11 as a base, and the plurality of scanning lines. 31
A plurality of auxiliary capacitance lines 33 provided in parallel with the scanning line 31 between them, an auxiliary capacitance electrode 33a of each subpixel formed by widening a part of the auxiliary capacitance line 33, and a gate electrode G ,
The TFT includes a source electrode S, a drain electrode D, and a semiconductor layer 34, a pixel electrode 35 of each subpixel, and an alignment film (not shown) formed on the surface of the pixel electrode 35. The gate electrode G is formed by extending a part of the scanning line 31 to the formation position of the semiconductor layer 34, and the source electrode S is formed by extending a part of the signal line 32 to the semiconductor layer 34. ing.

The scanning line 31 and the gate electrode G (in FIG. 4, the scanning line 3 is formed on the surface of the first transparent substrate 11.
1), the auxiliary capacitance line 33 and the auxiliary capacitance electrode 33a (in FIG. 4, only the auxiliary capacitance electrode 33a formed integrally with the auxiliary capacitance line 33 is shown) Along with the gate wiring 17 (see FIG. 1) formed in the peripheral portion of the display region, it is composed of a two-layer film of Ti and Al or Al alloy as a gate material. More specifically, various wirings or electrodes made of these gate materials are mainly Al or Al alloy formed in the lower layer, and this Al
Alternatively, it has a two-layer structure of Ti / Al or Al alloy in which a thin Ti film is formed on the surface of the Al alloy layer, and is simultaneously formed in the same layer by the same process. It should be noted that the use of Ti for the surface layer of the metal wiring as described above smoothes the surface of the Al or Al alloy layer that is prone to unevenness due to heat during sputtering for film formation, and also Al or Al alloy layer. This is to prevent oxidation.

The various wirings or electrodes and the exposed surface of the first transparent substrate 11 are covered with a gate insulating film 37. The gate insulating film 37 is formed through a two-stage plasma CVD process with different plasma CVD film forming conditions, and the first gate insulating film 37a and the second gate insulating film 37 are formed.
And a gate insulating film 37b. The first gate insulating film 37a and the second gate insulating film 37b in the first embodiment are both made of silicon nitride,
Although a difference in physical properties is recognized, but a clear difference in composition is not recognized, FIG. A specific manufacturing process of the gate insulating film 37 will be described later.

On the surface of the gate insulating film 37, the signal line 32, the signal line 32, the source electrode S, the drain electrode D, and the source wiring 18 (see FIG. 1) that are formed simultaneously are formed. These various wirings and electrodes are made of Al or an Al alloy and Ti as a source material. More specifically, the various wirings or electrodes made of these source materials are mainly Ti / Al or Al alloy / Al alloy / Al alloy, which is mainly composed of Al or Al alloy constituting the central layer, and the uppermost layer and the lowermost layer are formed of a thin Ti film. T
i is a three-layer structure, and they are simultaneously formed in the same layer by the same process. The reason why the lower layer of the source material is a Ti layer is to ensure adhesion with the gate insulating film 37 made of a silicon nitride layer.

Various wirings and electrodes made of these source materials, the TFT channel region CN between the source electrode S and the drain electrode D, and the exposed surface of the gate insulating film 37 are covered with a passivation film 38. The passivation film 38 is also formed through a two-stage plasma CVD process with different plasma CVD film forming conditions, and includes a first passivation film 38a and a second passivation film 38b. As for the passivation film 38 in the first embodiment, the first passivation film 38a and the second passivation film 38b are both made of silicon nitride, and although there is a difference in physical properties, the composition is clear. Since no difference is observed, the same reference numeral 38 is used in FIG.

In order to flatten the surface of the pixel electrode 35 on the surface of the passivation film 38,
For example, an interlayer resin film (also referred to as a planarizing film) 39 made of a photosensitive resin or the like is formed, and penetrates the passivation film 38 and the planarizing film 39 in a portion located above the auxiliary capacitance electrode 33a. A contact hole 40 is provided. A pixel electrode 35 made of a transparent conductive material such as ITO or IZO, which also serves as a conductive member, is formed on the surface of the planarizing film 39 so as to cover the contact hole 40, and the drain electrode D and the pixel electrode 35 are formed. Electrically connected.

As described above, in the display region 12 of the liquid crystal display panel 10 of the first embodiment, at least the surface of the drain electrode D whose surface layer is made of Ti is plasma-etched on the passivation film 38 made of silicon nitride formed by plasma CVD. The pixel electrode 35 is electrically connected through a contact hole 40 provided by the method.

Next, the arrangement of the gate wiring 17 and the source wiring 18 as metal wiring, the gate wiring terminal 41 and the source wiring terminal 42 formed in the driver IC mounting region, and their specific structures are shown in FIGS. Based on the explanation.

A gate wiring 17 and a source wiring 18 formed on the surface of the first transparent substrate 11 extend in the driver IC mounting region of the array substrate AR, and gates 17 and source wirings 18 have gates at their ends. A wiring terminal 41 and a source wiring terminal 42 are formed. The surface of the gate wiring 17 is covered with a gate insulating film 37, the source wiring 18 is formed on the surface of the gate insulating film 37, and the surface of the source wiring 18 and the exposed gate insulating film 37 is passivation. A film 38 is formed.

The end portion of the gate wiring 17 has a gate insulating film 37 and a passivation film 3 on the surface.
8 and is connected to a gate wiring terminal 41 made of a conductive material such as ITO or IZO through a contact hole 51. Further, the end of the source wiring 18 is covered with a passivation film 38 and is connected to a source wiring terminal 42 made of a conductive material such as ITO or IZO through a contact hole 52.
These gate wiring terminals 41 and source wiring terminals 42 will not be described in detail.
It is an area where bump terminals (not shown) of the driver IC 14 are mounted, and also serves as an inspection terminal such as an inspection probe, and is also used as an external connection terminal 19. Thus, forming the gate wiring terminal 41 and the source wiring terminal 42 with a conductive material such as ITO or IZO suppresses the formation of oxide films on the surfaces of the gate wiring 17 and the source wiring 18 made of a metal material. In order to obtain a good electrical connection.

The gate wiring 17 has a two-layer structure of Ti / Al or Al alloy that is simultaneously formed in the same layer in the same process as the scanning line 31, and its end extends to the mounting area of the driver IC 14. The surface of the gate wiring 17 is directly covered with a gate insulating film 37 as in the case of the scanning line 31, and the surface of the gate insulating film 37 is further covered with a passivation film 38. The gate insulating film 37 and the passivation film 38 are integrally formed at the same time in the same process as the gate insulating film 37 and the passivation film 38 in the display region 12 shown in FIG. A contact hole 51 for electrical connection between the gate wiring 17 and the gate wiring terminal 41 is provided in the gate insulating film 37 and the passivation film 38 located above the end of the gate wiring 17. . The contact hole 51 is simultaneously formed by a plasma etching method, like the contact hole 40 shown in FIG.

Then, by forming a gate wiring terminal 41 made of a transparent conductive material such as ITO or IZO on the surface of the passivation film 38 so as to cover the contact hole 51,
The gate wiring terminal 41 and the gate wiring 17 are electrically connected. The gate wiring terminal 41 is formed at the same time as the pixel electrode 35 in the same process.

On the other hand, the source wiring 18 is formed simultaneously on the same layer in the same process as the signal line 32, Ti /
It has a three-layer structure of Al or Al alloy / Ti, its end portion is extended to the driver IC mounting region, and its surface is covered with a passivation film 38. And
The passivation film 38 positioned above the end of the source wiring 18 is formed on the source wiring 18.
And a contact hole 52 for connecting the source electrode 42 to each other. This contact hole 52 is also formed at the same time by the same plasma etching method as the contact hole 40 shown in FIG.

Further, by forming a source wiring terminal 42 made of a transparent conductive material such as ITO or IZO on the surface of the passivation film 38 so as to cover the contact hole 52, the source wiring terminal 42, the source wiring 18, Are electrically connected. The source wiring terminal 42 is also formed simultaneously with the pixel electrode 35 in the same process.

Thus, in the driver IC mounting region of the array substrate AR, at least the surface of the gate wiring 17 and the source wiring 18 whose surface layer is made of Ti has a gate insulating film 37 and a passivation film 38 made of silicon nitride formed by plasma CVD. It is covered with. The surfaces of the gate wiring 17 and the source wiring 18 are electrically connected to the gate wiring terminal 41 and the source wiring terminal 42 through contact holes 51 and 52 provided by a plasma etching method.

Next, a specific method for manufacturing the array substrate AR of the liquid crystal display panel according to the first embodiment will be described with reference to FIGS. First, the liquid crystal display panel 10 is shown in FIG.
A conductive material 36 having a two-layer structure is formed on the surface of the first transparent substrate 11 by a sputtering method using a gate material. More specifically, after an Al or Al alloy layer is formed, a Ti layer is further stacked thereon to form a film. Then, as shown in FIG. 7B, a part thereof is removed by etching so that a predetermined pattern is obtained. Through this process, a plurality of scanning lines 31 extending in the row direction (lateral direction) and the auxiliary capacitance lines 33 (see FIG. 3 above) between the plurality of scanning lines 31.
And the gate electrode G positioned at the extending end of the scanning line 31 and the auxiliary capacitance electrode 33a having a part of the auxiliary capacitance line 33 widened by patterning, and the periphery of the display region 12 of the liquid crystal display panel 10 The common wiring 16 (see FIG. 1) and the gate wiring 17 are patterned.

Next, as shown in FIG. 7C, the scanning line 31 whose surface layer is made of Ti by the above-described steps,
A thin first gate insulating film 37a is formed by plasma CVD in a reduced pressure (vacuum) atmosphere so as to cover the first transparent substrate 11 on which the auxiliary capacitance line 33 and the gate wiring 17 are formed. The first gate insulating film 37a is formed by setting the plasma CVD conditions so that the deposition rate is slower than that of the second gate insulating film 37b. As source gas, disilane gas,
A gaseous silicon compound such as silane gas and a gaseous nitrogen compound such as ammonia are used.

The film formation speed is adjusted by changing the plasma generation power applied to the source gas to the second gate insulating film 37b.
The power for generating plasma applied to the source gas during film formation by the plasma CVD method is weakened, or the flow rate or partial pressure of the gaseous silicon compound in the source gas is set to the second gate insulating film 37.
This can be realized by setting so as to be smaller than the flow rate or partial pressure during b formation. Thus, by intentionally delaying the film formation rate of the first gate insulating film 37a, even when a silicon nitride film is directly formed on the Ti surface by the plasma CVD method, the formation of ball-shaped silicon nitride is greatly increased. Can be suppressed.

Next, as shown in FIG. 7D, the second gate insulating film 37 thicker than the first gate insulating film 37a is formed by plasma CVD so as to cover the entire surface of the first gate insulating film 37a.
b is deposited. The second gate insulating film 37b is formed under the CVD film forming conditions set so as to have a higher film forming speed than the first gate insulating film 37a. The second gate insulating film 37b is
Since contact with Ti is prevented by the first gate insulating film 37a, ball-shaped silicon nitride is not formed even if the nitride film is formed at a higher speed. This is because the first gate insulating film 37 described above.
It is presumed that this is due to the fact that even the formation of relatively small ball-shaped silicon nitride that can be the nucleus of ball-shaped silicon nitride formation is suppressed during the formation of a.

Next, as shown in FIG. 7E, for example, an amorphous silicon (a-Si) layer and an ohmic contact (n) are formed on the surface of the gate insulating film 37 formed through the two-step process as described above.
^A semiconductor film 34 ′ composed of a ( ⁺ a-Si) layer is formed. Then, as shown in FIG.
By etching the semiconductor film 34 ′, the semiconductor layer 34 that becomes a part of the TFT is formed above the gate electrode G, and the semiconductor film 34 ′ that covers other regions is removed.

Next, as shown in FIG. 7G, a conductive material 43 having a three-layer structure is formed by a sputtering method using a source material. More specifically, after a Ti layer is formed, an Al or Al alloy layer is stacked thereon, and a Ti layer is further stacked thereon.

Then, as shown in FIG. 8A, a part of the semiconductor layer is removed by etching, so that a plurality of signal lines 32 extending in a direction orthogonal to the scanning lines 31 and the semiconductor layers are extended from the signal lines 32. The source electrode S superimposed on a part of 34, the drain electrode D covering one part of the auxiliary capacitance electrode 33a and one end of which is superimposed on a part of the semiconductor layer 34, and the source wiring 18 are formed by patterning. Thereby, a channel region CN of the TFT is formed between the drain electrode D and the source electrode S.

Next, as shown in FIG. 8B, the signal line 32 whose surface layer is made of Ti is formed by the above-described process.
A passivation film 38 is formed so as to cover the source electrode S, the drain electrode D, the source wiring 18, and the channel region CN of the TFT. In FIG. 8B,
Although shown as one step, in practice, the step of forming the first passivation film 38a,
It is formed through a two-step process including a process of forming a second passivation film 38b thicker than the first passivation film 38a. The first passivation film 38a and the second passivation film 38a
The passivation film 38b is formed under film formation conditions similar to those of the first gate insulating film 37a and the second gate insulating film 37b shown in FIGS. 7C and 7D, respectively. Therefore, the formation of the ball-shaped silicon nitride is greatly suppressed while the passivation film 38 is formed on the surface of the metal wiring such as the signal line 32, the drain electrode D, and the source wiring 18 made of Ti.

Next, as shown in FIG. 8C, the second passivation film 38b and the first passivation film 38 located above the gate wiring terminal formation region are formed by plasma etching.
a, the portion of the second gate insulating film 37b and the first gate insulating film 37a, and the auxiliary capacitance electrode 33a
And a second passivation film 38a positioned above the source wiring terminal formation region, respectively.
Then, the portion of the first passivation film 38a is removed. Thus, the contact hole 40 is formed at a position corresponding to the drain electrode D, and the contact hole 5 is formed at the gate wiring terminal 41 portion.
1 and a contact hole 52 are formed in the source wiring terminal 42 portion.

Next, as shown in FIG. 8D, a planarizing film 39 is formed by applying, exposing and developing, for example, a photoresist material on the surface of the substrate formed by the above process. The planarizing film 39 is formed over the entire surface of the display region 12, and a contact hole 40 is formed at a position corresponding to the drain electrode D, and a gate wiring terminal forming region and a source wiring are formed. The terminal forming region for use is formed so as not to be covered.

Next, a transparent conductive film made of ITO, IZO or the like is formed on the entire surface of the first transparent substrate 11 by a sputtering method so as to cover the contact holes 40, 51, 52. This transparent conductive film is electrically connected to the drain electrode D through the contact hole 40, electrically connected to the gate wiring 17 through the contact hole 51, and further contact hole 52
Is electrically connected to the source wiring 18 via

Next, as shown in FIG. 8E, by etching, the pixel electrode 35 is formed at a position corresponding to each sub-pixel of the display region 12, and the gate wiring terminal 41 is formed in the gate wiring terminal formation region. The source wiring terminal 42 is formed in the source wiring terminal formation region.

According to the manufacturing method of the liquid crystal display panel of the first embodiment manufactured through the above steps, even if the surface layer of the metal wiring or the like is made of Ti by the gate insulating film 37 and the passivation film 38 made of the silicon nitride film. The formation of ball-shaped silicon nitride in the gate insulating film insulating film 37 and the passivation film 38 can be suppressed. Therefore, the ball-shaped silicon nitride remains between the drain electrode D and the pixel electrode, between the gate wiring 17 and the gate wiring terminal 41, and between the source wiring 18 and the source wiring angel 42. An increase in contact resistance can be suppressed.

In addition, since the second gate insulating film 37b and the second passivation film 38b can be formed by the plasma CVD method subsequently after the first gate insulating film 37a and the second passivation film 38a are formed by the plasma CVD method, There is no longer a problem that the total time required for production increases significantly.

[Second Embodiment]
Next, the manufacturing method of the liquid crystal display panel of 2nd Embodiment is demonstrated. The manufacturing method of the liquid crystal display panel of the second embodiment is different from that of the first embodiment in that the first insulating film 37a and the first passivation film 38a in the gate insulating film 37 and the passivation film 38 are oxidized by plasma CVD. The only point is the silicon film. Accordingly, the contents of the second embodiment will be described by appropriately referring to the drawings and symbols used in the description of the first embodiment and showing the differences from the first embodiment.

The formation of the silicon oxide film as the first gate insulating film 37a and the first passivation film 38a is almost the same as the manufacturing process of the silicon nitride film shown in FIG. 7C and FIG. For example, siloxane gas and oxygen gas are used as the gas. Even if a silicon nitride film is formed on the surface of the silicon oxide film by a plasma CVD method, it is difficult to produce ball-shaped silicon nitride. Therefore, the first embodiment also provides the first method of manufacturing the liquid crystal display panel.
The same operations and effects as in the embodiment can be obtained.

In general, plasma etching of an oxide film requires a larger power for plasma generation than that for etching a silicon nitride film, and therefore contact holes are formed in the gate insulating film 37 and the passivation film 38 shown in FIG. The process for forming 40, 51, 52 requires two stages of processing. That is, the second passivation film 38b to the second gate insulating film 37b, which is a silicon nitride film, is removed by a plasma etching method to expose the first passivation film 38a to the first gate insulating film, which is a silicon oxide film, and then the plasma. It is necessary to increase the power for generation and remove the silicon oxide film by plasma etching.

Note that the Ti layer on the surface layer of the metal wiring has low selectivity with respect to plasma etching, and may be scraped if overetched. However, when a silicon oxide layer is laminated on the surface of the metal wiring, the silicon oxide layer acts as a stopper layer in the plasma etching of the second passivation film 38b or the second gate insulating film 37b made of the silicon nitride layer. The Ti layer is not scraped during the over-etching of the second passivation film 38b or the second gate insulating film 37b. The silicon oxide layer can also be wet etched using dilute hydrofluoric acid or buffered hydrofluoric acid solution.

DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display panel 11 ... Transparent substrate 12 ... Display area 13 ... Structure 14 ... Driver IC 15 ... Transfer electrode 16 ... Common wiring 17 ... Gate wiring 18 ... Source wiring 19 ... External connection terminal 20 ... Transparent substrate 21 ... Structure 22 ... Counter electrode 23
... Sealing material 24 ... Liquid crystal layer 31 ... Scanning line 32 ... Signal line 33 ... Auxiliary capacitance line 33a ...
Auxiliary capacitance electrode 34 ... semiconductor layer 35 ... pixel electrode 36 ... conductive material 37 ... gate insulating film 37a ... first gate insulating film 37b ... second gate insulating film 38 ... passivation film 38a ... first passivation film 38b ... second passivation Film 39 ... Flattening film 40 ... Contact hole 40 ... Pixel electrode 41 ... Gate wiring terminal 42 ... Source wiring terminal 43 ... Conductive material 51, 52 ... Contact hole 100 ... Ball-shaped silicon nitride

Claims (6)

A second insulating film made of silicon nitride is formed after forming the first insulating film on the surface of at least the surface of the metal wiring made of titanium by plasma enhanced chemical vapor deposition, and the second insulating film and the second insulating film A method of manufacturing an electro-optical device comprising a step of forming a contact hole in a single insulating film by a plasma etching method to expose a surface of the metal wiring made of titanium,
A method of manufacturing an electro-optical device, wherein the first insulating film is formed of a material that does not form ball-shaped silicon nitride when the second insulating film made of silicon nitride is formed. Manufacturing the electro-optical device, wherein the first insulating film is formed from silicon nitride deposited under a film forming condition whose deposition rate is slower than a film forming condition of the second insulating film made of silicon nitride. Method. 3. The method of manufacturing an electro-optical device according to claim 2, wherein the first insulating film is formed with a power smaller than a power for plasma generation when the second insulating film made of silicon nitride is formed. . The flow rate or partial pressure of the first insulating film is smaller than the flow rate or partial pressure of the gaseous silicon raw material in the raw material gas when forming the second insulating film made of silicon nitride. Item 3. A method for manufacturing the electro-optical device according to Item 2. The method of manufacturing an electro-optical device according to claim 1, wherein the first insulating film is formed of silicon oxide. The metal wiring having at least a surface layer made of titanium is formed on a surface of an insulating film which is the same as a gate insulating film covering a surface of a gate electrode of a thin film transistor as a switching element of the electro-optical device. Item 6. A method for manufacturing an electro-optical device according to any one of Items 1 to 5.