JPH05315612A - Double diffusion type mosfet device and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize an excellent double diffusion type MOSFET device which does not require mask alignment by forming a nitride film and then performing each succeeding formation process with the structure used as a mask. CONSTITUTION:An N-type epitaxial layer 2 is formed on an N-type semiconductor substrate 1 on which a gate oxide film 3, a gate polysilicon film 4 and a nitride film 5 are successively formed, and then the nitride film 5 is partly removed to make an opening and the selective oxidation is performed with the remaining nitride film 5a used as a mask to form a selective oxide film 6 in contact with the gate oxide film 3. The N-type semiconductor substrate 1 makes a drain region, the polysilicon film 4 making a gate electrode, an N<+> diffused layer 15 making a source, the substrate 1 making a drain, and a wiring metal 19 makes a source electrode. Therefore, after an opening is provided in the nitride film 5, all diffused layers and contact holes are formed with the structure used as a mask by a self-alignment technique, so that the miniaturization of a device may be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention relates to a double diffusion type MOSFET (Metal-Oxide) among semiconductor devices.
-Semiconductor Field-effe
It relates to the formation of a ctive-transistor device.

[0002]

2. Description of the Related Art A semiconductor device is required to have appropriate characteristics according to its application, and for example, a driver IC for a plasma display or an electroluminescence display requires a transistor having a high breakdown voltage. A double diffusion type MOS is one of such high breakdown voltage transistors.
FETs are known. And this double diffusion type MOS
As a conventional method of manufacturing an FET device, there has been a method described below, for example.

3A to 3F show, for example, a document (Solid State Technology (Japan Version) (1986.1).
p. FIG. 44 is a process drawing of the conventional method for manufacturing the double-diffused MOSFET device disclosed in No. 44), which is a process drawing showing a cross section of one cell portion of the device in the main process. Further, FIG. 3F shows a completed sectional view of this device.

According to this conventional manufacturing method, first, L is formed on the N-type semiconductor substrate 31 having a specific resistance of about 0.004 Ω · cm.
Specific resistance 1-3Ω by suitable crystal growth technology such as PE method.
An N-type epitaxial layer 32 of about cm is formed. Then, a P ⁺ diffusion layer 33 having a surface impurity concentration of 10 ¹⁹ ions / cm ³ and a diffusion layer depth of about 1 μm is formed in a predetermined region of the N-type epitaxial layer 32 by a known photolithography method and ion implantation method (FIG. 3 (A)).

Next, a gate oxide film having a film thickness of about 500 Å is heat-treated on the N type epitaxial layer 32 having the P ⁺ diffusion layer 33, and further an N type polysilicon film having a film thickness of about 3000 Å is formed by CVD (chemical treatment). They are formed in this order by a vapor phase growth method (not shown). Then, the polysilicon film and the gate oxide film are processed by known photolithography technique and etching technique to form a gate polysilicon pattern 34 and a gate oxide film pattern 35, respectively (FIG. 3B).

Next, a P-type impurity such as boron is injected into the N-type epitaxial layer 32 by using the gate polysilicon pattern 34 as a mask and diffused into the N-type epitaxial layer 32 at a surface impurity concentration of 10 ¹⁷ ions / cm ³ . Depth is 2
A P-type diffusion layer 36 of about μm is formed. Further, when the P type diffusion layer 36 is formed, the impurities of the P ⁺ diffusion layer 33 are diffused into the N type epitaxial layer 32 to form the P ⁺ type diffusion layer 33a having a diffusion depth of about 3 μm (FIG. Three
(C)).

Next, a resist pattern 37 is formed on a predetermined portion of the P type diffusion layer 36 by a known photolithography technique.
Then, using the gate polysilicon pattern 34 and the resist pattern 37 as a mask, an N type impurity such as arsenic is implanted into the P type diffusion layer 36 by a known method such as ion implantation to obtain a surface impurity concentration of 10 ¹⁹ ions / cm ³
Then, an N ⁺ type diffusion layer 38 (source region) having a diffusion layer depth of about 0.5 μm is formed (FIG. 3D).

Next, the resist pattern 37 is removed, and then an oxide film 39 having a thickness of about 6000 Å is deposited on the sample by the CVD method, and then the oxide film 39 is contacted by the known photolithography technique and etching technique. A hole 40 is formed (FIG. 3 (E)).

Next, a wiring metal 41 such as Al having a thickness of about 1 μm is deposited on the sample, and the wiring metal 41 passes through the contact holes 40 to form the P ⁺ type diffusion layer 33a and the N ⁺ type diffusion layer 38, respectively. It is connected (FIG. 3 (F)).

Through the above steps, the double diffusion type MOSFET
The device is formed. In this device, the N-type semiconductor substrate 31 serves as the drain region, and the current almost flows through the path indicated by the arrow in FIG.

That is, the polysilicon film 34 is a gate electrode and N
^{The +} diffusion layer 38 has a MOS type field effect transistor (MOSFET) structure in which the source is the N type substrate 31 and the drain is the N type substrate 31, and the wiring metal 41 is the source electrode. This structure is the same in the embodiments of the present invention described later, and such a structure is called a double diffusion type MOSFET.

[0012]

However, in the conventional manufacturing method, when the N ⁺ type diffusion layer 38 described with reference to FIG. 3D is formed, and when the contact described with reference to FIG. 3E is used. It was necessary to newly form a resist pattern when forming the hole 40. Therefore, in order to form these resist patterns, the gate polysilicon pattern 34 is formed.
For each, it is necessary to match the mask, and for this reason,
The width W (see FIG. 3B) exposing the N-type epitaxial layer 32 of the gate polysilicon pattern 34 must be set to allow for a mask alignment margin, which is a great obstacle to downsizing of the device. was there. For example, if the alignment margin required for one mask alignment is 2 μm,
In the gate polysilicon pattern 34, an alignment margin of 4 μm or more is required for each opening (region indicated by W in FIG. 3B). And, for example, 50 × 50 to 1
Considering a double-diffused MOSFET device using a gate polysilicon pattern having about 00 × 100 openings, it is 40,000 to 16,000 due to the alignment margin.
This leads to an increase in the area of 0 μm ² . In addition, such a conventional device has a problem that the contact resistance between the source electrode and the source region increases and the on-resistance increases with the miniaturization of the source region.

The present invention is based on the above-mentioned N ⁺ type diffusion layer 3
8 and the contact hole 40 are required to be mask-aligned with the gate polysilicon respectively, and a mask alignment margin is expected, which hinders downsizing of the device and miniaturization of the source region. Along with,
In order to eliminate the problem that the contact resistance in that portion increases, the source electrode and the source region are connected via polySi (polysilicon), and the source electrode and the polyS are connected.
It is an object of the present invention to provide an excellent double diffusion type MOSFET device in which a connection area of i is made larger than a connection area of a source region and polySi and which does not require mask alignment for each of them, and a manufacturing method thereof. ..

[0014]

To achieve the above object, the present invention provides a gate oxide film and a gate polysilicon film formed on a semiconductor substrate (N type), and a nitride film formed on the gate oxide film and the gate polysilicon film. An opening is provided in a region to be formed, and the opening is used as an oxide film by using the mask as a mask, and the oxide film in the opening is removed to leave the nitride film as an eaves-like shape on the opening. Using the structure as a mask, subsequent layers and regions are formed, a polysilicon film (N type in the embodiment) is formed between the eaves and the source region, and wiring is performed on the substrate including the opening. The layer (source electrode) is formed. That is, a polysilicon film (N type in the embodiment) is interposed between the source electrode and the source region.

[0015]

As described above, according to the present invention, after the nitride film is formed, the structure is used as a mask for each subsequent formation. Therefore, mask alignment becomes unnecessary, and it is necessary to consider the mask alignment margin. Is eliminated and miniaturization can be achieved.

Since the polysilicon film is interposed between the source electrode and the source region, the contact area with the source electrode is increased and the contact resistance can be reduced.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a manufacturing process of a first embodiment of the present invention, which will be described below in the order of FIGS.

FIG. 1 (A) First, the specific resistance is 0.004Ω.
The specific resistance is 1 to 3 Ω by the crystal growth technique such as LPE (liquid phase epitaxial) method on the N-type semiconductor substrate 1 of about cm.
The N-type epitaxial layer 2 having a size of about cm is formed. Then, a gate oxide film 3 having a film thickness of about 500 Å is thermally oxidized on the N-type epitaxial layer 2 to further reduce the film thickness to 300.
The gate polysilicon film 4 of about 0Å is formed by the CVD method.
Further, a nitride film 5 having a film thickness of about 1500 Å is formed in this order by the CVD method.

Next, a part of the above-mentioned nitride film 5 is opened to have a diameter of 3 μm, and selective oxidation is performed using the remaining nitride film 5a as a mask so that the gate oxide film 3 is contacted. A selective oxide film 6 of 1 μm is formed. At this time, the nitride film 5a
Is part of the selective oxide film 6 due to the bird's beak phenomenon.
The shape is lifted up.

FIG. 1 (C) Next, the selective oxide film 6 and the gate oxide film 3 in the opening are removed by a known isotropic etching using the nitride film 5a as a mask, and the N-type epitaxial layer is formed. 2 is exposed 8. At this time,
A part of the nitride film 5a lifted above the selective oxide film 6 in (B) has a shape protruding like an eaves due to the removal of the selective oxide film 6. This nitride film 5 protruding like an eaves
A part of a will be called eaves 7 hereinafter. The exposed surface 8 of the N-type epitaxial layer has a diameter of approximately 3 μm, like the opening of the nitride film 5 described above.

Next, the exposed surface 8 of the N-type epitaxial layer is subjected to a well-known ion implantation method and subsequent heat treatment, so that a P-type diffusion layer 9 having a surface impurity concentration of 10 ¹⁷ ions / cm ³ and a diffusion depth of about 1 μm is formed. To form.

Next, by thermal oxidation, an oxide film 10 and an oxide film 11 of 3000 Å are formed on the side surface of the opening of the gate polysilicon film 4 and the exposed surface 8 of the N-type epitaxial layer, respectively.

Next, by anisotropic dry etching, the oxide film 11 formed on the exposed surface 8 of the N-type epitaxial layer is removed to newly expose the exposed surface 8a of the N-type epitaxial layer. Form. After that, at the bottom of the eaves 7,
The entire surface of the N-type epitaxial layer including the exposed surface 8a has a thickness of 8000Å, and N-type impurities such as P are 1 × 10 ¹⁹ ion.
An s / cm ³ doped N-type polysilicon film 12 is formed. This film may be N-type amorphous silicon.

After that, the N-type polysilicon film 12 is etched back by anisotropic etching to form an N-type polysilicon film 13 that supports the eaves 7 and is in contact with the N-type epitaxial layer 2. To do. Thereby about 1.4 μm
The exposed surface 14 of the N-type epitaxial layer having a diameter is formed. Then, by heat treatment, the diffusion depth from the N-type polysilicon layer 13 is 0.5 μm and the surface concentration is 1 × 10 ¹⁹ ions.
The N ⁺ diffusion layer 15 of about / cm ³ is formed. This is the source. Therefore, the N ⁺ diffusion layer 15 is the N type polysilicon 1
3 and is formed on the lower side thereof.

FIG. 1 (G) Next, the N-type polysilicon layer 1
3 and the exposed surface 14 of the N-type epitaxial layer is oxidized, and then the oxide film formed on the surface of the exposed surface 14 of the N-type epitaxial layer is removed by anisotropic etching. Only the oxide film 16 is left. The exposed surface 14a of the newly exposed N-type epitaxial layer having a diameter of about 0.4 μm is subjected to a known ion implantation method and the subsequent heat treatment to form a P having a surface impurity concentration of 10 ¹⁹ ions / cm ^{3 and a} diffusion depth of about 0.5 μm. ^{The +} layer 18 is formed.

Next, the oxide film 16 is removed by known etching. Finally, a wiring metal 19 such as Al having a thickness of about 1 μm is formed by, for example, a vapor deposition method and is connected to the N-type polysilicon layer 13 and the P ⁺ layer 18 to complete the double diffusion MOSFET device. In this device,
The N-type semiconductor substrate 1 becomes the drain region, and the current flows almost as shown by the arrow in FIG. Similarly to the conventional structure, the polysilicon film 4 is the gate electrode, the N ⁺ diffusion layer 15 is the source, the substrate 1 is the drain, and the wiring metal 19 is the source electrode. In this embodiment, the source electrode 19 and the source 15 are used.
The N-type polysilicon layer 13 is interposed between the contact point and the contact point to widen the contact area.

The manufacturing process of the second embodiment of the present invention is the first
1D is the same as that of the first embodiment, and the subsequent manufacturing method is shown in FIGS. 2A to 2F, which will be described below in order.
However, in the second embodiment, the opening diameter of the nitride film 5 and the exposed surface of the N-type epitaxial layer are each 3.5 μm.

2A, a CVD oxide film 21 of 15000 Å is formed on the entire surface including the lower portion of the eaves (7 in FIG. 1) and the oxide film (11 in FIG. 1).

Next, as shown in FIG. 2B, the CVD oxide film 21 is etched back by anisotropic etching to obtain N.
-Type epitaxial layer (2 in FIG. 1) is exposed to 0.5 μm
The exposed surface 23 of the N-type epitaxial layer having a diameter is formed, and at the same time, the supporting oxide film 22 that supports the eaves 7 is formed. At this time, the etched side surface of the supporting oxide film 22 has a tapered shape. After that, a known ion implantation method and subsequent heat treatment are performed from the exposed surface 23 of the N-type epitaxial layer to obtain a depth of 1.2 μm and a surface impurity concentration of 1 × 10 ^19.
A P ⁺ layer 24 of ions / cm ³ is formed.

Next, anisotropic etching is further performed to remove a part of the supporting oxide film 22 to form a supporting oxide film 22a whose etching side surface is vertical.

FIG. 2 (D) Next, the entire surface has a thickness of 3000.
Å, N type impurities such as P are 1 × 10 ¹⁹ ions / cm
^{A 3-} doped N-type polysilicon film 25 is formed.

Next, as shown in FIG. 2 (E), anisotropic dry etching is performed to form an N-type polysilicon layer 26 on the side surface of the supporting oxide film 22a. Then, by heat treatment, N-type impurities are diffused from the N-type polysilicon layer 26 into the N-type epitaxial layer 2, and the surface impurity concentration is 1
0 ¹⁹ ions / cm ^3, the diffusion depth of about 0.5 [mu] m N
^{+ A} diffusion layer 27 is formed.

FIG. 2F. Finally, a wiring metal 28 of Al or the like having a thickness of about 1 μm is formed by, for example, a vapor deposition method and is connected to the N-type polysilicon 26 and the P ⁺ layer 24 to form a double diffusion MOSFET device. Is completed. The current path by this device is as shown by the arrow in FIG. The configuration is the same as that of the first embodiment except that the CVD oxide film 21 is provided below the eaves 7.

[0034]

As described above in detail, according to the method for manufacturing a double diffusion type MOSFET of the present invention, after the opening is formed in the nitride film on the gate polysilicon film, the structure is masked. As all the diffusion layers and contact holes are formed by the self-alignment technology, mask alignment becomes unnecessary, and there is no need to consider the mask alignment margin in device design. Can be achieved.

Further, in the first embodiment, the P ⁺ layer is formed by an ion implantation method using the oxide film formed on the N type polysilicon as a mask, and the N ⁺ diffusion layer is formed by the ion implantation method. Since it is formed by diffusion from above, there is no room between the P ⁺ layer and the N ⁺ diffusion layer, and the heat treatment for forming the P ⁺ layer is the same as or after the heat treatment for forming the N ⁺ diffusion layer. Therefore, there is a problem that it is difficult to deepen the P ⁺ layer for the purpose of improving the latch-up resistance. The second embodiment solves this problem by using P
^{Since the +} layer is formed by ion implantation using the supporting oxide film as a mask, the N ⁺ diffusion layer is formed by diffusion from the N-type polysilicon. Therefore, the CVD oxide film and the N-type polysilicon film are formed. By changing the thickness, it is possible to allow a gap between the P ⁺ layer and the N ⁺ diffusion layer, and the heat treatment for forming the P ⁺ layer is performed before the heat treatment for forming the N ⁺ diffusion layer. Therefore, the P ⁺ layer can be deepened and the latch-up withstand capability can be improved.

Therefore, the first and second embodiments should be properly used according to the purpose, the latch-up withstand amount is not so required, and the on-resistance is small.
The first embodiment is suitable when a low-cost one is required, and the second embodiment is suitable when a large latch-up tolerance is required.

Further, in the structure of the present invention, since the N ⁺ type diffusion layer and the wiring metal (source electrode) are connected through the N type polysilicon, the connection area between the N type polysilicon and the wiring metal is N. ⁺ Because it can be larger than the area of the diffusion layer,
The contact resistance between the N ⁺ type diffusion layer and the wiring metal can be reduced accordingly. As a result, it is possible to reduce the on-resistance of the double diffusion type MOSFET.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention.

FIG. 2 is a second embodiment of the present invention.

FIG. 3 is a conventional example.

[Explanation of symbols]

1 N-type semiconductor substrate 2 N-type epitaxial layer 3 Gate oxide film 4 Gate polysilicon film 5 Nitride film 6 Selective oxide film 7 Eaves 9 P-type diffusion layer 10, 11, 16 Oxide film 13 N-type polysilicon layer 15 N ⁺ diffusion Layer 18 P ⁺ Layer 19 Wiring metal

Claims (3)

[Claims] 1. A diffusion layer of a first conductivity type is formed on one main surface side of a semiconductor substrate, and M is formed in the diffusion layer of the first conductivity type.
A double-diffusion MOSFET device having a second-conductivity-type diffusion layer, which is a source region of an OSFET, and both the first and second-conductivity-type diffusion layers being connected to a source electrode, wherein the first-conductivity-type diffusion A double diffusion MOSFET device, wherein the layer is directly connected to the source electrode, and the second conductivity type diffusion layer is connected to the source electrode through at least a conductive film. 2. A step of: (a) forming a layer serving as a gate electrode of a MOSFET on a semiconductor substrate and forming a first insulating film on the layer; (b) partially forming the first insulating film. Opening, and using the opened first insulating film as a mask, a layer of the opening to be the gate electrode is made into an insulating film, (c) the insulating film in the opening is removed, and the opening is formed. Exposing the surface of the substrate and leaving the first insulating film in an eaves-like shape above the opening, (d) forming a diffusion layer of the first conductivity type on the substrate exposed in the opening. Step (e) An insulating film is formed on the side wall of the opening, a second conductivity type film is formed on the entire surface including the opening, and the second conductivity type film is left only under the eaves. And other portions are removed to form a contact hole, (f) a second conductivity type film under the eaves To the underlying substrate, the second
A step of forming a conductive type diffusion layer, (g) a step of forming a first conductive type high concentration diffusion layer on the substrate below the contact hole using the second conductive type film under the eaves as a mask, h) A step of forming a wiring metal on the above structure, and a double diffusion type MOSF including the above steps
ET device manufacturing method. 3. (a) The same step as the forming method up to (d) in claim 2, (b) the side wall of the opening below the eaves is in contact with the substrate surface exposed in the opening. Forming a non-shaped insulating film, (c) forming a second conductivity type film on the side wall of the insulating film on the side wall of the opening so as to be in contact with the substrate surface, (d) forming a second conductivity type film A double-diffused MOSF including the steps of forming a diffusion layer of the second conductivity type on the lower substrate, (e) the step of forming a wiring metal on the structure described above, and the above steps.
ET device manufacturing method.