JPH0529416A - Ic parallel test system - Google Patents

Abstract

PURPOSE:To shorten the time of a test by a method wherein the ratio of IC's under test as objects to be tested to IC's under test as objects not to be tested is checked and a function to automatically judge whether a testing flow is continued or not is provided. CONSTITUTION:Regarding a plurality of IC's 6a to 6n under test which are tested in parallel, the test and judgement result of the individual IC's 6a to 6n under test with reference to individual test items is obtained. Regarding the IC's which have been judged to be defective in the course of a testing flow, their test with reference to a next test item is not performed. The IC's which have been judged to be good with reference to all the test items after their final test item has been finished are judged to be good IC's. The IC's which have been judged to be detective in their halfway test item are judged to be defective IC's. At this time, their yield check inside their parallel test which compares and judges a judgment result is checked with reference to a reference value, regarding the ratio of the number of good IC's under test to the number of defective IC's by means of the test and judgment result, which has been preset for the test; a yield, regarding their test items, which judges whether the testing flow is to be continued or not on the basis of the check is monitored.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC parallel test system, and more particularly to an IC parallel test system for testing a plurality of ICs under test in parallel for a plurality of test items.

[0002]

2. Description of the Related Art Recently, in the IC parallel test system,
Development of parallel test system for testing multiple ICs under test at the same time with one IC test system as the test time per unit increases as the ICs under test become highly integrated / functionalized. That is, the improvement of test time efficiency has led to the reduction of test system equipment and the reduction of total test cost.

FIG. 3 shows the configuration of a conventional IC parallel test system.
Shown in. The test signal S4 generated from one IC tester 3a corresponding to one test item is divided into the number n of ICs to be measured, and n test objects S connected to the measuring unit 60 in the handler. It is simultaneously applied to the leads of the ICs 6a to 6n. On the other hand, Sa to Sn from the respective measured ICs 6a to 6n for the applied test signal S4 are the IC tester 3a.
Is input to the n comparison / determination units 8a to 8n individually configured for each IC to be measured, and the quality determination is performed for each n IC to be measured.

Next, this IC parallel test flow is shown in FIG. A series of test sequences consists of M test items (test A
~ Test M), and a total test is performed by sequentially executing each test item according to the flow. In the plurality of measured ICs 6a to 6n to be subjected to the parallel test, the test determination result is obtained for n individual measured ICs 6a to 6n for each of M individual test items (test A to test M). UC to be measured, which was judged to be defective in the middle of the flow
As for, the control flow is such that the flow on the right enters and the test for the next test item is not performed. At the time when the final test item (test M) is completed, those that have passed all the test items are determined to be non-defective ICs, and those that are determined to be defective in the intermediate test items are determined to be defective ICs, and a series of tests are performed. Complete.

That is, in the parallel test, in each test item, it is determined whether or not the test target is a test target because of the determination result of each IC to be measured, and only the test target IC determined to be the test target is tested. The next test item is executed, while the IC to be measured that has not been determined to be the test target stands by in the non-test state while the IC to be measured test item that is the test target ends.

That is, the plurality of ICs to be measured, which were the test object at the start of the test flow, were gradually deleted from the test object according to the test result accompanying the progress of the test flow and were made the test object at the start of the test flow. The test flow is not always the case where all n ICs to be measured are subject to the parallel test all the time.

Further, the above-mentioned IC parallel test system is connected with a handler for continuously supplying a plurality of ICs to be measured for parallel test to the measuring section and classifying according to the test result, and thus a large amount of measured ICs is measured. ICs are tested continuously.
A block diagram of this system is shown in FIG. Handler 4b
The ICs to be measured set in the supply unit 5 are simultaneously supplied to the measurement unit 60 by n for each parallel test number, and the parallel test is performed according to the above-described test flow. Then, after all the test flows are completed, the classification signal S8a from the IC tester 3a causes the measurement section 60 to discharge the batches at the same time, and the classification storage section 13a is classified into either the good product storage section 10 or the defective product section 12. ..

That is, once the n measured ICs 6a to 6n corresponding to the number of parallel tests are once supplied to the measuring section 60 of the handler 4b, they are discharged from the measuring section 60 until the sequence according to the test flow is completed. Things are impossible,
Even if most of the ICs to be measured during the parallel test are judged to be defective in the first half of the test flow, the ICs to be measured are judged to be non-defective.
The test is continued as long as there is even one, and the n measured ICs 6a to 6n supplied to the measurement unit 60 are in a standby state in the measurement unit 60 of the handler 4b until all test items are completed. There is.

[0009]

As described above, according to the conventional IC parallel test system, when the parallel test is performed according to the parallel test flow and the handler is connected to perform the parallel test, among the ICs to be measured, the parallel test is performed. Then, the measured I to be tested
As long as there is at least one C, the measured ICs excluded from the test object also need to wait for batch discharge / classification from the measurement unit of the handler until there are no measured ICs to be tested.

Therefore, the IC parallel test system used to shorten the test time for each IC to be measured also has a defective product in the ratio of good products to defective products of the measured IC supplied to the measuring section of the handler. If the number of parallel tests is large, the actual number of parallel tests is less than the number of parallel test capabilities of the device. Even if the number of parallel tests per IC test system is increased, the test time per IC under test is increased. There was a problem that the effect of shortening was lost.

It is an object of the present invention to provide an IC parallel test system for parallel test with a short test time.

[0012]

An IC parallel test system of the present invention comprises a test signal generator for supplying test signals in parallel to a plurality of external ICs under test in order according to a test flow.
A determination unit that inputs each output signal of the IC to be measured and outputs a determination signal of pass / fail by comparing with a reference value, and a yield in a predetermined test item in the test flow that receives the determination signal. Yield monitor calculation for comparing with a preset reference yield, and if this calculation result is a predetermined value or more, the test flow is continued, and if the calculation result is a predetermined value or less, the test flow An IC tester having a determination unit that suspends and outputs a defective product classification signal for a defective product and a provisional non-defective product signal for a non-defective product, and a plurality of the IC testers from the supply unit. A measuring unit which is supplied with the IC to be measured, receives the test signal from the IC to be measured and outputs the output signal, and then receives the classification signal to collectively exclude the ICs to be measured to a classification control unit;
A classification storage unit that stores the IC to be measured in a non-defective product storage unit, a defective product storage unit, and a temporary non-defective product storage unit via a classification control unit 9 that receives the classification signal.

[0013]

The present invention will be described below with reference to the drawings. Figure 1
FIG. 4 is a test flow chart for explaining a parallel IC test using an embodiment of the present invention. A series of test flows is composed of a plurality of test items (test A to test M), and a total test is performed by sequentially executing each test item according to the flow. A plurality of ICs under test 6a to 6n to be tested in parallel
In, the test judgment result is obtained for each of the measured ICs 6a to 6n in each of the test items (test A to test M), and the measured ICs determined to be defective in the middle of the test flow are The control flow is not tested in. Then, in the case of the normal flow, when the final test items are completed, those that are judged to be acceptable in all the test items are judged to be non-defective ICs, and those that are judged to be defective in the test items in the middle are judged to be defective ICs. The test is complete.

At this time, in this example, in the test A,
Yield check 1 in the parallel test for comparing and judging the judgment result against the reference value of the ratio of the number of non-defective products to the number of defective ICs (so-called yield) based on the test judgment result set in advance in test A, and this check 1 The test item yield monitor 2 for determining whether or not to continue the test flow is performed.

Next, FIG. 2 shows a block diagram of an embodiment of the present invention. The handler 4 supplies a supply unit 5 for supplying a large amount of ICs to be measured, a measurement unit 6 having measurement sites for the number n or more of parallel measurement of the IC tester 3, and a classification signal S8 from the classification signal 7 of the IC tester 3. The classification control unit 9 receives the measured ICs 6a to 6n according to the classification signal S8, and the non-defective product storage unit 1
0, temporary non-defective article storage section 11 and defective article storage section 12 are classified and stored.

The measured ICs 6a to 6n corresponding to the number of parallel measurements are collectively supplied from the supply unit 5 to the measurement unit 6, and are collectively excluded from the measurement unit 6 by the classification signal S8 after the test and are stored in the classification storage unit 13. ..

On the other hand, the IC tester 3 supplies a test signal generator 15 for supplying the test signal S4 for the parallel test to the measuring unit 6 of the handler 4, and the test results Sa to S of the individual ICs to be measured.
It comprises a determination unit 16 for determining n, a classification signal generation unit 7 for generating a classification signal S8 associated with the test flow, and a test control unit 17 for controlling the entire test flow.

When the IC parallel test is performed in the test flow shown in FIG. 1, the ICs 6a to 6n to be measured are processed according to the supply and storage operation of the hadron 4 shown in FIG. That is, n measured ICs for the number of parallel measurement are collectively supplied from the supply unit 5 to the measurement unit 6, and individual test items Test A to Test M are performed.
Are executed in order. When the test A set in the yield monitoring test item is executed in the test flow, the ratio of non-defective products and defective products in the n tested ICs 6a to 6n tested in parallel is checked by silicic acid and set in advance. When the ratio of defective products to the reference value is high, the test flow is interrupted, and the defective products are stored in the defective storage unit by the classification according to the (good / defective) judgment of the test A without waiting for the final test judgment of the test flow. 12
In addition, non-defective products are stored in the temporary non-defective product storage unit 11.

After that, the measured ICs stored in the temporary-goods storage unit 11 as temporary products are returned to the supply unit 5 again after the measurement of all the measured ICs reset in the supply unit 5 is completed. After being set, the parallel test is performed again in a state where the ratio of non-defective products is high. That is, by performing a parallel test using this IC test system, when a large number of ICs to be measured, each of which has a long test time, are tested in parallel, the execution efficiency of the parallel test is improved, so that a large number of tests can be performed. It will be possible.

In this example, the ratio of good products and defective products in the test A was calculated. For example, in the case of the test C, the good product is a good product in all the items from the test A to the test C, and the defective product is the test A to B. Then, it was defined as a good product and defective in test C.
It may be defined as cumulative failure until test C.

The classification storage unit 13 of the handler 4 shown in FIG.
It is also possible to add a retest transfer unit 18 that automatically transfers a non-defective item from the non-defective item storage unit 11 to the supply unit 5.

[0022]

As described above, according to the IC parallel test system of the present invention, in any test item in the parallel test flow, the measured IC to be tested and the measured IC not to be tested. It has a function to check the ratio of ICs and automatically judge whether to continue the test flow. By issuing an efficient classification and storage command to the handler, the parallel test capability of the IC parallel test system. Can be effectively used, and even if the test time for each IC to be measured is lengthened, this parallel measurement system can shorten the test time, reduce capital investment, and reduce test costs. effective.

[Brief description of drawings]

FIG. 1 is a test flow chart for explaining an IC parallel test using an embodiment of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a partial block diagram of an example of a conventional IC parallel test system.

FIG. 4 is a test flow chart for explaining the operation of the block of FIG.

5 is an overall block diagram of FIG. 3. FIG.

[Explanation of Codes] 1 Yield check in parallel test 2 Test item Yield monitoring monitor 3 IC test system 4 Handler 5 Supply section 6 Measuring section 6a to 6n IC to be measured 7 Classification signal generating section 8a to 8n Comparison judging section 9 Classification control section 10 Good Goods Storage Section 11 Temporary Goods Storage Section 12 Defective Product Storage Section 13 Classification Storage Section 15 Test Signal Generation Section 16 Judgment Section 17 Test Control Section 18 Retest Transfer Section Sa-Sn Judgment Signal S4 Test Signal S8 Classification Signal

Claims (1)

Claim: What is claimed is: 1. A test signal generator for supplying test signals to a plurality of external ICs to be measured in parallel in order according to a test flow, and an output signal of the ICs to be measured, respectively, for reference. A determination unit that outputs a pass / fail determination signal in comparison with a value and a yield in a predetermined test item in the test flow that receives the determination signal and compares the yield with a preset reference yield Yield monitor calculation is performed, and if the calculation result is equal to or greater than a predetermined value, the test flow is continued, and if the calculation result is less than or equal to the predetermined value, the test flow is interrupted, and a defective product in the predetermined test item is determined. On the other hand, an IC tester having a determination unit that outputs a defective product classification signal and a non-defective product classification signal for a good product, and the plurality of ICs to be measured are supplied from the supply unit to the IC to be measured. The test report And outputs the output signal, and then receives the classification signal and removes the measured ICs to the classification control unit all at once, and the classification control unit 9 that receives the classification signal An IC parallel test system including: a good product storage unit, a defective product storage unit, and a classification storage unit that stores the temporary good product storage unit.