JP3232588B2 - IC parallel test system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC parallel test system, and more particularly to an IC parallel test system for testing a plurality of ICs to be measured in parallel for a plurality of test items.

[0002]

2. Description of the Related Art In recent years, in an IC parallel test system,
With the increase in the test time per IC accompanying the high integration and high functionality of the ICs to be measured, a parallel test system for testing multiple ICs to be measured simultaneously with one IC test system has been developed. Eliminating test system equipment by improving test time efficiency and reducing total test cost are being promoted.

FIG. 3 shows the configuration of a conventional IC parallel test system.
Shown in The test signal S4 generated corresponding to one test item from one IC tester 3a is divided into the number n of ICs to be measured, and the n test signals S4 connected to the measuring unit 60 in the handler. It is simultaneously applied to the leads of the ICs 6a to 6n. On the other hand, Sa to Sn from each of the measured ICs 6a to 6n with respect to the applied test signal S4 correspond to the IC tester 3a.
Are input to the n number of comparison / determination units 8a to 8n individually configured for each of the measured ICs, and pass / fail judgment is performed for the n measured ICs.

FIG. 4 shows the flow of the IC parallel test. A series of test sequences includes M test items (test A
試 験 test M), and a total test is performed by sequentially executing each test item according to a flow. In the plurality of ICs 6a to 6n to be subjected to the parallel test, test determination results are obtained for n individual ICs 6a to 6n for each of M individual test items (tests A to M). Measured UC determined to be defective during the flow
Is a control flow in which the flow on the right is entered and no test is performed for the test item of the next rank. At the end of the final test item (test M), those that passed all the test items were judged to be good ICs, and those that were judged to be defective in the middle test items were judged to be defective ICs, and a series of tests were performed. Complete.

[0005] That is, in the parallel test, in each test item, whether or not to be a test object in the next test item is determined based on the judgment result of each of the ICs to be measured, and only the IC to be measured determined as the test object is determined. The next test item is executed, and on the other hand, the IC under test that is not determined to be a test object waits without performing a test while the test IC test item to be tested ends.

In other words, a plurality of ICs to be measured, which were being tested at the start of the test flow, were gradually deleted from the test subject due to the test results accompanying the progress of the test flow, and were made test subjects at the start of the test flow. All of the n ICs to be measured have a test flow that is not always subjected to the parallel test.

Further, the above-described IC parallel test system is connected to a handler for continuously supplying a plurality of ICs to be subjected to a parallel test to a measuring unit and for performing classification according to the test results, thereby providing a large number of measured objects. The IC is tested continuously.
A block diagram of this system is shown in FIG. Handler 4b
The ICs to be measured set in the supply unit 5 are simultaneously supplied to the measurement unit 60 in units of n for each parallel test number, and the parallel test is performed according to the test flow described above. Then, after all the test flows are completed, the data is simultaneously discharged from the measuring unit 60 at the same time according to the classification signal S8a from the IC tester 3a, and is classified into one of the non-defective product storage unit 10 and the defective product unit 12 of the classification storage unit 13a. .

That is, once the n ICs to be measured 6a to 6n corresponding to the number of parallel tests are supplied to the measuring section 60 of the handler 4b, they are discharged from the measuring section 60 until the entire sequence according to the test flow is completed. Things are impossible,
Even if the majority of the ICs under test during the parallel test are judged to be defective in the first half of the test flow, the ICs to be measured are determined to be non-defective.
As long as there is at least one test, the test is continued, and the n ICs to be measured 6a to 6n supplied to the measuring unit 60 are in a standby state in the measuring unit 60 of the handler 4b until all the test items are completed. I have.

[0009]

As described above, in the conventional IC parallel test system, when the parallel test is performed in accordance with the parallel test flow and the handler is connected, the number of ICs to be measured in which the parallel test is performed is limited. Then, the measured I to be tested
As long as at least one C exists, it is necessary to wait for batch removal / classification of the measured IC removed from the test object from the measuring unit of the handler until there is no more IC to be tested.

[0010] Therefore, the IC parallel test system used to reduce the test time per IC to be measured is also defective in the ratio of non-defective and non-defective ICs to be supplied to the measuring section of the handler. When the number of parallel tests is large, the actual number of parallel tests is smaller than the number of parallel test capabilities of the device. Even if the number of parallel tests per IC test system is increased, the test time per IC There is a problem that the effect of shortening the time is lost.

An object of the present invention is to provide an IC parallel test system for a parallel test with a short test time.

According to the IC parallel test system of the present invention, a test signal is sequentially output to a plurality of external devices under test according to a test flow.
And a test signal generator that supplies the test signal in parallel to C and outputs an output signal of the IC under test, compares the output signal with a reference value, outputs a pass / fail judgment signal, receives the judgment signal, and executes the test flow. Yield model by an arithmetic function that compares the yield in a predetermined test item with a preset reference yield.
And if the calculation result is equal to or greater than a predetermined value, the test flow is continued, and a good
Good product classification signal for product, defective product for defective product
Means for outputting a classification signal, means for interrupting the test flow when the calculation result is equal to or less than a predetermined value, and a defective product classification signal for a defective product in the predetermined test item;
A determining unit that outputs a provisional non-defective product classification signal for a non-defective product;
No., temporary good classification signal, a classification signal generator for generating, trial
An IC tester having a test control unit for controlling a test according to a test flow , a supply unit for supplying the plurality of ICs to be measured, and the plurality of ICs to be measured are supplied from the supply unit;
It was tested by receiving the test signal to the measured IC, this
After outputting the test result, the non-defective product classification signal and the defective
A measurement unit for collectively eliminate the measured IC to the classification control unit receives a goods classification signals the tentative good classification signal, the non-defective component
Receiving the kind signal, the defective product classification signal, and the temporary non-defective product classification signal, classifying the IC under test into a non-defective product storage section, a defective product storage section, and a temporary non-defective product storage section, and classifying and storing the IC under test.
And a classification storage unit.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG.
FIG. 5 is a test flow chart for explaining a parallel IC test using one embodiment of the present invention. A series of test flows includes a plurality of test items (test A to test M), and a total test is performed by executing each test item in order according to the flow. A plurality of ICs to be measured 6a to 6n for which a parallel test is performed
In, test determination results are obtained for each of the measured ICs 6a to 6n in the individual test items (test A to test M), and for the measured IC determined to be defective in the middle of the test flow, the following test items are used. Is a control flow in which the test is not performed. Then, in the case of the normal flow, when the final test item is completed, a test item determined to be acceptable in all test items is determined to be a good IC, and a test item determined to be defective in the middle test item is determined to be a defective IC. The test is completed.

At this time, in this embodiment, in test A,
Yield check 1 in the parallel test for comparing the judgment result with the reference value of the ratio of the number of non-defective ICs and the number of defective ICs (so-called yield) based on the test judgment result set in advance in test A, and this check 1 A test item yield monitoring monitor 2 for determining whether to continue the test flow is performed.

FIG. 2 is a block diagram showing an embodiment of the present invention. The handler 4 supplies a supply unit 5 for supplying a large number of ICs to be measured, a measurement unit 6 having a number of measurement sites equal to or larger than the number n of the IC testers 3 measured in parallel, and a classification signal S8 from the classification signal 7 of the IC tester 3. The non-defective product storage unit 1 receives the ICs 6a to 6n to be measured according to the classification signal S8.
0, a classification storage unit 13 that classifies and stores the temporary product storage unit 11 and the defective product storage unit 12.

The ICs 6a to 6n to be measured in the parallel measurement number are supplied collectively from the supply unit 5 to the measurement unit 6, are collectively excluded from the measurement unit 6 by the classification signal S8 after the test, and are stored in the classification storage unit 13. .

On the other hand, the IC tester 3 supplies a test signal generation section 15 for supplying a test signal S4 for the parallel test to the measurement section 6 of the handler 4, and the test results Sa to S of the individual ICs to be measured.
It comprises a determination unit 16 for determining n, a classification signal generation unit 7 for generating a classification signal S8 accompanying the test flow, and a test control unit 17 for controlling the entire test flow.

When the IC parallel test is performed according to the test flow shown in FIG. 1, the measured ICs 6a to 6n are processed in accordance with the operation of supplying and storing the hydra 4 shown in FIG. That is, n ICs to be measured for the number of parallel measurements are supplied collectively from the supply unit 5 to the measurement unit 6, and the individual test item tests A to M
Are executed in order. When the test A set in the yield monitoring test item is executed in the test flow, the ratio of non-defective and non-defective products in the n ICs to be measured 6a to 6n being tested in parallel is checked , and a predetermined reference is set. If the ratio of defective products to the value is large, the test flow is interrupted, and the test A (good / bad) is performed without waiting for the final test determination of the test flow.
According to the classification based on the judgment, the defective product is stored in the defective storage unit 12 and the non-defective product is stored in the temporary non-defective product storage unit 11.

Thereafter, the measured ICs stored in the temporary storage unit 11 as temporary products are transferred to the supply unit 5 again after the measurement of all the ICs manually reset in the supply unit 5 is completed. After being set, the parallel test is performed again with a high ratio of non-defective products. In other words, by performing a parallel test using this IC test system, when a large number of ICs to be measured have a long test time per unit, a large number of tests can be performed because the parallel test execution efficiency is improved. It becomes possible.

In this embodiment, the ratio of non-defective products to non-defective products in the test A was calculated. For example, in the case of the test C, the non-defective products are non-defective products in all the items from the test A to the test C. Then, it was defined as a good product and a failure in test C,
It may be defined as the cumulative failure up to test C.

Also, the classification storage unit 13 of the handler 4 shown in FIG.
A retest transfer unit 18 that automatically transfers the temporary product from the temporary product storage unit 11 to the supply unit 5 may be added.

[0022]

As described above, in the IC parallel test system of the present invention, in any test item in the parallel test flow, the IC under test and the IC under test not It has a function to automatically check the ratio of ICs and determine whether to continue the test flow and to issue an efficient classification and storage command to the handler, so that the parallel test capability of the IC parallel test system Can be effectively used, and even if the test time per IC under test is lengthened, this parallel measurement system can shorten the test time, reduce the capital investment, and promote the reduction of the test cost. effective.

[Brief description of the drawings]

FIG. 1 is a test flow chart for explaining an IC parallel test using one embodiment of the present invention.

FIG. 2 is a block diagram of one embodiment of the present invention.

FIG. 3 is a partial block diagram of an example of a conventional IC parallel test system.

FIG. 4 is a test flowchart for explaining the operation of the block in FIG. 3;

FIG. 5 is an overall block diagram of FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Yield check in parallel test 2 Test item yield monitoring monitor 3 IC test system 4 Handler 5 Supply unit 6 Measuring unit 6a to 6n IC to be measured 7 Classification signal generation unit 8a to 8n Comparison and judgment unit 9 Classification control unit 10 Good storage unit 11 Temporary product storage unit 12 Defective product storage unit 13 Classification storage unit 15 Test signal generation unit 16 Judgment unit 17 Test control unit 18 Retest transfer unit Sa-Sn judgment signal S4 Test signal S8 Classification signal

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-86738 (JP, A) JP-A-1-116461 (JP, A) JP-A-61-67239 (JP, A) JP-A-60-1985 10743 (JP, A) JP-A-1-237471 (JP, A) JP-A-4-137746 (JP, A) JP-A-2-257649 (JP, A) JP-A-2-216540 (JP, A) JP-A-2-24577 (JP, A) JP-A-4-354345 (JP, A) JP-A-4-340241 (JP, A) JP-A-4-276639 (JP, A) JP-A-4-186649 (JP, A) JP-A-4-23446 (JP, A) JP-A-1-313845 (JP, A) JP-A-4-178576 (JP, A) JP-A-3-136261 (JP, A) Kaisho 63-50030 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/66 B07C 5/36 G01R 31/26 H01L 21/822 H01L 27/0 Four

Claims (1)

(57) [Claims] 1. A test signal generator for supplying a test signal in parallel to a plurality of external ICs to be measured in order according to a test flow, and an output signal of the IC to be measured is input and compared with a reference value. A yield monitoring means for outputting a determination signal of rejection, receiving the determination signal and comparing the yield in a predetermined test item in the test flow with a preset reference yield, If the calculation result is equal to or greater than a predetermined value, the test flow is continued, and
In the test item, if there is a good product, a good product classification signal is
Means for outputting a defective classification signal in the case of a non-defective product, and for interrupting the test flow in a case where the calculation result is equal to or less than a predetermined value.
And a defective product classification signal for a defective product in the predetermined test item, and a tentative non-defective product classification signal for a good product.
A determination unit that outputs, the non-receiving signal of the determination unit
An IC tester having a classification signal generating unit for generating a good classification signal, a good product classification signal, and a temporary good product classification signal, and a test control unit for controlling a test according to a test flow; A supply unit for supplying an IC, and the plurality of ICs to be measured are supplied from the supply unit;
Said test signal receiving and were tested, after outputting the test results, the good classification signal and the defective classification signals and previously
The serial measurement unit for collectively eliminate the classification control unit the measured IC receiving the temporary good classification signal, the non-defective classification signal and not
Receiving the non- defective product classification signal and the tentative non-defective product classification signal , the measured IC is stored in the non-defective product storage unit, the defective product storage unit and the temporary product storage unit .
And a classification storage unit that classifies and stores the IC under test.