JPH05267355A - Manufacture of charge transfer device - Google Patents

Manufacture of charge transfer device

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Publication number
JPH05267355A
JPH05267355A JP5864492A JP5864492A JPH05267355A JP H05267355 A JPH05267355 A JP H05267355A JP 5864492 A JP5864492 A JP 5864492A JP 5864492 A JP5864492 A JP 5864492A JP H05267355 A JPH05267355 A JP H05267355A
Authority
JP
Japan
Prior art keywords
oxide film
silicon oxide
gate electrode
film
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5864492A
Other languages
Japanese (ja)
Inventor
Arata Toyoda
新 豊田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5864492A priority Critical patent/JPH05267355A/en
Publication of JPH05267355A publication Critical patent/JPH05267355A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To improve a dielectric strength between electrodes of a charge transfer device and to manufacture even a device having many number of elements in high yield. CONSTITUTION:Three films of a silicon oxide film 2, a silicon nitride film 3 and a silicon oxide film 4 are used as a gate insulating film, a first gate electrode 5 of polycrystalline silicon is formed, its surface is oxidized, a gate insulating film except a part directly under the electrode 5 is removed, a silicon oxide film 6 is grown by a CVD method as a gate insulating film of a second gate electrode 8, and a dielectric strength between the electrodes is reinforced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電荷転送装置の製造方法
に関し、特に電荷転送電極の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a charge transfer device, and more particularly to a method for forming a charge transfer electrode.

【0002】[0002]

【従来の技術】現在、固体撮像装置に広く用いられてい
る電荷転送素子である電荷結合素子(以下CCDとす
る)は、極めて狭い間隔で電気的に分離された多数のM
OSキャパシタを配列させた構造を持っており、各々の
MOSキャパシタに次々に電圧パルスを印加し、このM
OSキャパシタの列に沿って電荷を転送する機構を持
つ。このようなMOSキャパシタの列を形成する上で最
も重要な点は、各電極を数百nm程度の極めて狭い間隔
で形成しなければならないことである。現在のフォトリ
ソグラフィー技術ではこのような狭い間隔で電極を分離
することは困難なため、従来このような構造の電極列を
形成するために一般に次のような方法が用いられる。す
なわち、図3に示すように、半導体基板12上にゲート
絶縁膜13を介して多結晶シリコンの第1ゲート電極1
4をCVD法とフォトリソグラフィー法によって形成し
た後、第1ゲート電極14の表面に熱酸化によって薄い
シリコン酸化膜15を形成し、次にこの上にCVD法と
フォトリソグラフィー法によって多結晶シリコンの第2
ゲート電極16を形成する。このように複数の層の電極
を薄い絶縁膜を介して重ね合わせる構造とすることによ
って、現在のフォトリソグラフィー技術によって余裕を
もって数百nm程度の間隔でゲート電極列を形成でき
る。
2. Description of the Related Art At present, a charge-coupled device (hereinafter referred to as a CCD), which is a charge transfer device widely used in a solid-state image pickup device, has a large number of Ms electrically separated at extremely narrow intervals.
It has a structure in which OS capacitors are arranged, and voltage pulses are applied to each MOS capacitor one after another.
It has a mechanism for transferring charges along the columns of the OS capacitors. The most important point in forming such a row of MOS capacitors is that each electrode must be formed with an extremely narrow interval of about several hundred nm. Since it is difficult to separate the electrodes at such a narrow interval by the current photolithography technology, the following method is generally used to form the electrode array having such a structure. That is, as shown in FIG. 3, the first gate electrode 1 made of polycrystalline silicon is formed on the semiconductor substrate 12 via the gate insulating film 13.
4 is formed by the CVD method and the photolithography method, a thin silicon oxide film 15 is formed on the surface of the first gate electrode 14 by thermal oxidation, and then a thin film of polycrystalline silicon is formed thereon by the CVD method and the photolithography method. Two
The gate electrode 16 is formed. By thus forming a structure in which the electrodes of a plurality of layers are superposed with a thin insulating film interposed therebetween, it is possible to form gate electrode rows at intervals of about several hundreds of nm with a margin by the current photolithography technology.

【0003】[0003]

【発明が解決しようとする課題】しかしながら上述した
従来のCCDの製造方法は第1ゲート電極および第2ゲ
ート電極と形成している多結晶シリコン層の層間絶縁膜
として、多結晶シリコンを熱酸化して形成したシリコン
酸化膜を用いている。このシリコン酸化膜は、単結晶シ
リコンを熱酸化して形成したシリコン酸化膜に比べて未
酸化シリコンや導電性不純物として高濃度に添加された
リン等を多く含み膜質は著しく劣っている。また熱酸化
は多結晶の粒界に沿って進行することから、酸化後の電
極の表面は凹凸が極めて大きくなり、層間の絶縁性の低
い部分が多数存在する。従って特に素子数の多いCCD
の場合、電極間の絶縁不良が発生する確率が高く、CC
Dの製造歩留りを大幅に低下させるという問題点があっ
た。
However, in the above-described conventional method for manufacturing a CCD, polycrystalline silicon is thermally oxidized as an interlayer insulating film of the polycrystalline silicon layer formed with the first gate electrode and the second gate electrode. The formed silicon oxide film is used. This silicon oxide film contains a large amount of unoxidized silicon and phosphorus added as a conductive impurity at a high concentration as compared with a silicon oxide film formed by thermally oxidizing single crystal silicon, and thus the film quality is significantly inferior. Further, since the thermal oxidation progresses along the grain boundaries of the polycrystal, the surface of the electrode after the oxidation has extremely large irregularities, and there are a large number of portions having low insulating properties between layers. Therefore, CCD with a large number of elements
In the case of, the probability of insulation failure between electrodes is high, and CC
There is a problem that the manufacturing yield of D is significantly reduced.

【0004】本発明は上記問題点を解消し、電極間の絶
縁耐圧を十分高くすることができ、素子数の多いCCD
でも高歩留りで製造できる方法を提供するものである。
The present invention solves the above problems, makes it possible to sufficiently increase the withstand voltage between electrodes, and has a large number of elements.
However, it is intended to provide a method that can be manufactured with a high yield.

【0005】[0005]

【課題を解決するための手段】本発明の電荷転送装置の
製造方法は半導体基板表面に該半導体基板の酸化に対す
る保護性を有する膜を形成する工程と、該ゲート絶縁膜
上に多結晶シリコンの第1のゲート電極を形成する工程
と、熱酸化によって該第1のゲート電極表面にシリコン
酸化膜を形成する工程と、該シリコン酸化膜に重ねてC
VD法により層間絶縁膜を形成する工程と、該層間絶縁
膜を介して多結晶シリコンの第2のゲート電極を形成す
る工程を有する。
A method of manufacturing a charge transfer device according to the present invention comprises a step of forming a film having a protective property against oxidation of the semiconductor substrate on the surface of the semiconductor substrate, and a step of forming polycrystalline silicon on the gate insulating film. Forming a first gate electrode, forming a silicon oxide film on the surface of the first gate electrode by thermal oxidation, and superimposing C on the silicon oxide film.
The method includes a step of forming an interlayer insulating film by the VD method and a step of forming a second gate electrode made of polycrystalline silicon via the interlayer insulating film.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明す
る。図1(a)〜(e)は本発明の一実施例の手順を示
す断面図である。まず、図1(a)に示すように、半導
体基板1上に熱酸化によって厚さ40nmのシリコン酸
化膜2を形成し、次にCVD法により厚さ40nmのシ
リコン窒化膜3,厚さ20nmのCVDシリコン酸化膜
4を続けて成長する。続いて図1(b)に示すように、
CVD法により厚さ50nmの多結晶シリコン膜を成長
し、フォトリソグラフィー法により第1ゲート電極5を
形成した後、熱酸化によって第1ゲート電極5表面に厚
さ200nmのシリコン酸化膜6を形成する。この際半
導体基板1表面はシリコン窒化膜3で覆われているため
酸化は進行しない。続いて図1(c)に示すように、C
VDシリコン酸化膜4,シリコン窒化膜3,シリコン酸
化膜2を除去する。この際、シリコン窒化膜3を除去す
るときはリン酸溶液,CVDシリコン酸化膜4およびシ
リコン酸化膜2を除去するときはフッ化水素酸溶液を用
いるのが望ましいが、第1ゲート電極5表面のシリコン
酸化膜6の目減り量は100nm以下となるように過剰
のエッチングは避けなければならない。続いて図1
(d)に示すように、半導体基板1上にCVD法により
膜厚50nmのCVDシリコン酸化膜7を成長する。C
VDシリコン酸化膜は、多結晶シリコンを熱酸化して得
られたシリコン酸化膜に比べて絶縁耐圧がはるかに優れ
ているため、これによって十分な特性の層間絶縁膜が形
成される。続いて図1(e)に示すように、CVD法と
フォトリソグラフィー法によって多結晶シリコンの第2
ゲート電極8を形成する。
The present invention will be described below with reference to the drawings. 1 (a) to 1 (e) are sectional views showing the procedure of one embodiment of the present invention. First, as shown in FIG. 1 (a), a silicon oxide film 2 having a thickness of 40 nm is formed on a semiconductor substrate 1 by thermal oxidation, and then a silicon nitride film 3 having a thickness of 40 nm 3 and a thickness of 20 nm are formed by a CVD method. The CVD silicon oxide film 4 is continuously grown. Then, as shown in FIG.
A polycrystalline silicon film having a thickness of 50 nm is grown by the CVD method, the first gate electrode 5 is formed by the photolithography method, and then a silicon oxide film 6 having a thickness of 200 nm is formed on the surface of the first gate electrode 5 by thermal oxidation. .. At this time, since the surface of the semiconductor substrate 1 is covered with the silicon nitride film 3, the oxidation does not proceed. Then, as shown in FIG.
The VD silicon oxide film 4, silicon nitride film 3, and silicon oxide film 2 are removed. At this time, it is desirable to use a phosphoric acid solution when removing the silicon nitride film 3 and a hydrofluoric acid solution when removing the CVD silicon oxide film 4 and the silicon oxide film 2. Excessive etching must be avoided so that the depletion amount of the silicon oxide film 6 is 100 nm or less. Continuing with Figure 1
As shown in (d), a 50-nm-thick CVD silicon oxide film 7 is grown on the semiconductor substrate 1 by the CVD method. C
Since the VD silicon oxide film has a much higher dielectric strength than the silicon oxide film obtained by thermally oxidizing polycrystalline silicon, this forms an interlayer insulating film having sufficient characteristics. Then, as shown in FIG. 1 (e), a second polysilicon film is formed by CVD and photolithography.
The gate electrode 8 is formed.

【0007】このようにして多結晶シリコンの電極列を
形成することにより、素子数の多いCCDにおいても電
極間の絶縁不良が発生する確率が極めて低く、CCDの
製造歩留りを大幅に向上させることができる。
By forming the polycrystalline silicon electrode array in this way, the probability of occurrence of insulation failure between electrodes is extremely low even in a CCD having a large number of elements, and the manufacturing yield of the CCD can be greatly improved. it can.

【0008】図2(a)〜(c)は本発明の第2の実施
例の手順を示す断面図である。すなわち、図1(a)お
よび(b)と同様に半導体基板1上にシリコン熱酸化膜
2,シリコン窒化膜3,CVDシリコン酸化膜4をそれ
ぞれ40nm,40nm,20nmの厚さで積層して形
成した後、CVD法とフォトリソグラフィー法によって
多結晶シリコンの第1ゲート電極5を形成し、熱酸化に
よって第1ゲート電極5の表面に厚さ200nmのシリ
コン酸化膜6を形成する。続いて図2(a)に示すよう
に、CVDシリコン酸化膜4およびシリコン窒化膜5を
それぞれフッ化水素酸溶液およびリン酸溶液で除去す
る。ここでシリコン熱酸化膜2は除去せずにそのまま残
す。またCVD酸化膜4を除去する際、シリコン酸化膜
6の目減り量は40nm以下となるようにする。続いて
図2(b)に示すように、半導体基板1上にCVD法で
シリコン窒化膜9,およびCVDシリコン酸化膜10を
それぞれ40nm,20nmの厚さで成長する。シリコ
ン酸化膜6の絶縁耐圧はこのシリコン窒化膜9,および
CVDシリコン酸化膜10によって補強されるため、十
分な特性の層間絶縁膜を形成することができる。続いて
図2(c)に示すように、CVD法とリソグラフィ法に
よって多結晶シリコンの第2ゲート電極11を形成す
る。
FIGS. 2A to 2C are sectional views showing the procedure of the second embodiment of the present invention. That is, as in FIGS. 1A and 1B, a silicon thermal oxide film 2, a silicon nitride film 3, and a CVD silicon oxide film 4 are formed on the semiconductor substrate 1 to have a thickness of 40 nm, 40 nm, and 20 nm, respectively. After that, the first gate electrode 5 of polycrystalline silicon is formed by the CVD method and the photolithography method, and the silicon oxide film 6 having a thickness of 200 nm is formed on the surface of the first gate electrode 5 by thermal oxidation. Subsequently, as shown in FIG. 2A, the CVD silicon oxide film 4 and the silicon nitride film 5 are removed by a hydrofluoric acid solution and a phosphoric acid solution, respectively. Here, the silicon thermal oxide film 2 is not removed but left as it is. Further, when the CVD oxide film 4 is removed, the reduction amount of the silicon oxide film 6 is set to 40 nm or less. Subsequently, as shown in FIG. 2B, a silicon nitride film 9 and a CVD silicon oxide film 10 are grown on the semiconductor substrate 1 by the CVD method to have a thickness of 40 nm and 20 nm, respectively. Since the withstand voltage of the silicon oxide film 6 is reinforced by the silicon nitride film 9 and the CVD silicon oxide film 10, an interlayer insulating film having sufficient characteristics can be formed. Subsequently, as shown in FIG. 2C, a second gate electrode 11 of polycrystalline silicon is formed by the CVD method and the lithography method.

【0009】この実施例では、第1ゲート電極と第2ゲ
ート電極直下のゲート絶縁膜がそれぞれ同じ構造となる
ため特性の差を生じることがないという利点を持つ。
In this embodiment, the first gate electrode and the gate insulating film immediately below the second gate electrode have the same structure, and therefore, there is an advantage that there is no difference in characteristics.

【0010】[0010]

【発明の効果】以上説明したように本発明は半導体基板
表面に、ゲート絶縁膜として階半導体基板の酸化に対す
る保護性を有する膜を形成する工程と、階ゲート絶縁膜
上に多結晶シリコンの第1のゲート電極を形成する工程
と、熱酸化によって該第1のゲート電極表面にシリコン
酸化膜を形成する工程と、該シリコン酸化膜に重ねてC
VD法により層間絶縁膜を形成する工程と、該層間絶縁
膜を介して多結晶シリコンの第2のゲート電極を形成す
る工程を有しており、これによって電極間の絶縁耐圧を
十分高くすることができ素子数の多いCCDを高歩留り
で製造できるという効果がある。
As described above, according to the present invention, the step of forming a film as a gate insulating film on the surface of a semiconductor substrate and having a protection property against oxidation of the semiconductor substrate, and the step of forming polycrystalline silicon on the gate insulating film are performed. No. 1 gate electrode, a step of forming a silicon oxide film on the surface of the first gate electrode by thermal oxidation, and a step of overlaying C on the silicon oxide film.
The method includes a step of forming an interlayer insulating film by the VD method and a step of forming a second gate electrode made of polycrystalline silicon via the interlayer insulating film, thereby sufficiently increasing the dielectric strength voltage between the electrodes. Therefore, there is an effect that a CCD having a large number of elements can be manufactured with a high yield.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の手順を示す断面図。FIG. 1 is a sectional view showing a procedure of an embodiment of the present invention.

【図2】本発明の第2の実施例の手順を示す断面図。FIG. 2 is a sectional view showing the procedure of the second embodiment of the present invention.

【図3】従来の電荷転送装置の断面図。FIG. 3 is a cross-sectional view of a conventional charge transfer device.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 シリコン酸化膜 3 シリコン窒化膜 4 CVDシリコン酸化膜 5 第1ゲート電極 6 シリコン酸化膜 7 CVDシリコン酸化膜 8 第2ゲート電極 9 シリコン窒化膜 10 CVDシリコン酸化膜 11 第2ゲート電極 12 半導体基板 13 ゲート絶縁膜 14 第1ゲート電極 15 シリコン酸化膜 16 第2ゲート電極 1 semiconductor substrate 2 silicon oxide film 3 silicon nitride film 4 CVD silicon oxide film 5 first gate electrode 6 silicon oxide film 7 CVD silicon oxide film 8 second gate electrode 9 silicon nitride film 10 CVD silicon oxide film 11 second gate electrode 12 Semiconductor substrate 13 Gate insulating film 14 First gate electrode 15 Silicon oxide film 16 Second gate electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板表面に、ゲート絶縁膜として
該半導体基板の酸化に対する保護性を有する膜を形成す
る工程と、該ゲート絶縁膜上に多結晶シリコンの第1の
ゲート電極を形成する工程と、熱酸化によって該第1の
ゲート電極表面にシリコン酸化膜を形成する工程と、該
シリコン酸化膜に重ねてCVD法により層間絶縁膜を形
成する工程と、該層間絶縁膜を介して多結晶シリコンの
第2のゲート電極を形成する工程とを有することを特徴
とする電荷転送装置の製造方法。
1. A step of forming a film having a protection property against oxidation of the semiconductor substrate as a gate insulating film on a surface of the semiconductor substrate, and a step of forming a first gate electrode of polycrystalline silicon on the gate insulating film. A step of forming a silicon oxide film on the surface of the first gate electrode by thermal oxidation, a step of forming an interlayer insulating film on the silicon oxide film by a CVD method, and a polycrystal via the interlayer insulating film. And a step of forming a second gate electrode made of silicon.
JP5864492A 1992-03-17 1992-03-17 Manufacture of charge transfer device Withdrawn JPH05267355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5864492A JPH05267355A (en) 1992-03-17 1992-03-17 Manufacture of charge transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5864492A JPH05267355A (en) 1992-03-17 1992-03-17 Manufacture of charge transfer device

Publications (1)

Publication Number Publication Date
JPH05267355A true JPH05267355A (en) 1993-10-15

Family

ID=13090296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5864492A Withdrawn JPH05267355A (en) 1992-03-17 1992-03-17 Manufacture of charge transfer device

Country Status (1)

Country Link
JP (1) JPH05267355A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007086204A1 (en) * 2006-01-30 2007-08-02 Matsushita Electric Industrial Co., Ltd. Double gate isolation structure for ccds and corresponding fabricating method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007086204A1 (en) * 2006-01-30 2007-08-02 Matsushita Electric Industrial Co., Ltd. Double gate isolation structure for ccds and corresponding fabricating method
US7964451B2 (en) 2006-01-30 2011-06-21 Panasonic Corporation Solid state imaging device and method for fabricating the same

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