JPH1012837A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable increase of charge storage amount of a capacitance element, by forming an anti-oxidizing film on the surface of a lower part electrode, a dielectric film constituted of a high permitivity film on the surface of the anti-oxidiging film, and an upper electrode on the surface of the dielectric film. SOLUTION: A capacitance element C of a memory cell is formed on the surface of an interlayer insulating film 11, and constituted of STC structure wherein a lower electrode 15, a dielectric film 17 and an upper electrode 18 are laminated in order. In the capacitance element C, an anti-oxidzing film 16 constituted of a silicon nitride Si3 N4 film is formed between the lower electrode 15 and the dielectric film 17. Since composition balance of Si and N is stable in the silicon nitride, reaction between Si of the lower electrode 15 constituted of a silicon film 14 and O5 of the dielectric film 17 constituted of tantalum pentoxide Ta2 O5 film can be prevented. The upper electrode 18 of the capacitance element C is constituted of a tungsten film, and covered with an interlayer insulating film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having a capacitive element in which a lower electrode, a dielectric film made of a high dielectric constant film, and an upper electrode are sequentially laminated. And effective technology.

[0002]

DRAM is a semiconductor integrated circuit device (D y
namic R andom In A ccess M emory), 1 [ bi
t] is stored in a MOSFET ( M
etal O xide S emiconductor F ield E ffect T ransis
and a series circuit of a tor) and a capacitance element. MOS
FET is mainly a semiconductor region which is a channel forming region,
The semiconductor device includes a gate insulating film, a gate electrode, and a pair of semiconductor regions which are a source region and a drain region. This MO
The SFET is formed on the main surface of the active region of the semiconductor substrate. Capacitive element includes a lower electrode, a dielectric film, and a sequentially laminated STC (St acked C apacitor) structures respectively of the upper electrode. This capacitive element is formed above the MOSFET in order to reduce the planar size of the memory cell.

[0003] In recent years, the planar size of the capacitance element of a memory cell has tended to decrease with the increase in the degree of integration of the DRAM, and it has become difficult to secure the amount of charge stored in the capacitance element. Therefore, in order to secure the accumulated charge amount of the capacitor, the dielectric film of the capacitor is made of a tantalum pentoxide (Ta ₂ O ₅ ) film which is a high dielectric constant film having a higher dielectric constant than a silicon oxide film or a silicon nitride film. Attempts have been made to form However, the lower electrode
Usually, since the impurity is formed of a polycrystalline silicon film which has been introduced, O ₅ of this on the surface of the lower electrode when forming a tantalum pentoxide film as a dielectric film, the lower electrode Si and tantalum pentoxide film Reacts, and a natural silicon oxide film grows at the interface between the lower electrode and the tantalum pentoxide film. Since this natural silicon oxide film is connected in series with the capacitance of the dielectric film, the amount of charge stored in the capacitance element is significantly reduced.

Accordingly, as described in, for example, Japanese Patent Application Laid-Open No. 5-243524, silicon nitride (Si ₃ N _{4) is provided} between a lower electrode made of a polycrystalline silicon film and a dielectric film made of a tantalum pentoxide film. ) An anti-oxidation film made of a film is formed to prevent a reaction between Si of the lower electrode and O _{5 of the} tantalum pentoxide film. This capacitive element is formed by the following manufacturing process.

First, a polycrystalline silicon film into which impurities are introduced is formed on a main surface of a semiconductor substrate (semiconductor wafer). Next, a photosensitive resist film is formed on the surface of the polycrystalline silicon film by a spin coating method, and then, the photosensitive resist film is subjected to a baking process, an exposure process, a developing process, etc. A resist mask is formed on a predetermined area of the substrate. Next, using the resist mask as an etching mask, the polycrystalline silicon film is patterned to form a lower electrode. Next, the resist mask is removed, and thereafter, an oxidation prevention film made of a silicon nitride (Si ₃ N ₄ ) film is formed on the surface of the lower electrode. Next, a dielectric film made of a tantalum pentoxide film is formed on the surface of the antioxidant film,
Thereafter, a capacitor is formed by forming an upper electrode on the surface of the dielectric film.

[0006]

In the manufacturing process of the capacitive element, each of the polycrystalline silicon film and the photosensitive resist film is formed by a different device. The semiconductor substrate must be transported. During the transportation of the semiconductor substrate, the surface of the polycrystalline silicon film is exposed to the atmosphere, so that a natural silicon oxide film is formed on the surface of the polycrystalline silicon film. Since this natural silicon oxide film remains after patterning the polycrystalline silicon film,
A natural silicon oxide film is formed on the surface of the lower electrode formed by patterning the polycrystalline silicon film.

Therefore, after removing the resist mask, the natural silicon oxide film on the surface of the lower electrode is removed. The removal of the natural oxide film is performed by, for example, a removal apparatus using a hydrofluoric acid aqueous solution. However, since the semiconductor substrate must be transported from the device for removing the native silicon oxide film to the device for forming the antioxidant film, the surface of the lower electrode is exposed to the air during this movement, and the surface of the lower electrode is again exposed to the air. A natural silicon oxide film is formed. That is, a natural silicon oxide film is always formed on the surface of the lower electrode before the formation of the oxidation preventing film.

[0008] Thus, the reaction between O ₅ of the lower Si and tantalum pentoxide electrode (Ta ₂ O ₅₎ made of film dielectric layer was prevented by anti-oxidation film, to suppress the growth of a natural oxide silicon film Also,
Since the natural silicon oxide film is formed between the lower electrode and the antioxidant film, the amount of charge stored in the capacitor is reduced by an amount corresponding to the thickness of the natural silicon oxide film.

An object of the present invention is to increase the amount of charge stored in a capacitance element in a semiconductor integrated circuit device having a capacitance element in which a lower electrode, a dielectric film composed of a high dielectric constant film, and an upper electrode are sequentially laminated. It is to provide a technology that can.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A lower electrode, a dielectric film made of a high dielectric constant film,
A method of manufacturing a semiconductor integrated circuit device having a capacitor element in which respective upper electrodes are sequentially stacked, the method including: forming an electrode pattern made of a first silicon film into which an impurity is introduced; Selectively forming a second silicon film by a growth method, forming a lower electrode including the second silicon film and the electrode pattern, and forming the lower electrode using the same film forming apparatus as the second silicon film. Forming an antioxidant film on the surface, forming a dielectric film made of a high dielectric constant film on the surface of the antioxidant film, and then forming an upper electrode on the surface of the dielectric film Is provided.

According to the above-described means, after forming the lower electrode composed of the electrode pattern and the second silicon film, the oxidation preventing film is formed on the surface of the lower electrode by the same film forming apparatus as the second silicon film. Therefore, a natural oxide film is not formed between the lower electrode and the antioxidant film. As a result, a capacitance value corresponding to the entire film thickness obtained by adding the film thickness of the antioxidant film to the film thickness of the dielectric film made of the high dielectric constant film can be obtained, so that the charge storage amount of the capacitor can be increased. it can. The electrode pattern and the second
A natural silicon oxide film is formed between the silicon film and the silicon film.
Since the thickness of the natural silicon oxide film is such that impurities can move from the electrode pattern to the second silicon film, the electrode pattern and the second silicon film can be regarded as a single body.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the structure of the present invention
A description will be given together with an embodiment in which the present invention is applied to a RAM (semiconductor integrated circuit device).

In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 1 shows a DRA according to an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of a memory cell mounted on M, and FIG. 2 is a sectional view of a main part of the DRAM. Note that, in FIG. 2, illustration of an upper portion of a capacitive element described later is omitted for easy viewing of the drawing.

As shown in FIG. 1, a memory cell M mounted on a DRAM is constituted by a series circuit of a MOSFET Q and a capacitor C. The memory cell M is arranged at an intersection of a word line WL extending in the row direction (Y direction) and a data line DL extending in the column direction (X direction), and stores information of 1 [bit].

One semiconductor region of the MOSFET Q is electrically connected to the data line DL, the other semiconductor region is electrically connected to one electrode of the capacitive element C, and its gate electrode is electrically connected to the word line WL. Connected.

When the memory cell M is selected, the word line WL is fixed at a potential of, for example, 5 [V]. When the memory cell M is not selected, the word line WL is fixed at a potential of, for example, 0 [V]. The data line DL is fixed at a potential of, for example, 3.3 [V] when charges are stored in the capacitor C, and is 0 [V] when charges are not stored in the capacitor C, for example.
The potential is fixed to the potential.

A plurality of the memory cells M are arranged in a row direction in which the word lines WL extend and in a column direction in which the data lines DL extend, and constitute a memory cell array. The memory cell array includes a word driver circuit, an X decoder circuit,
The peripheral circuit is formed in a memory cell array forming region surrounded by a peripheral circuit forming region in which peripheral circuits such as a Y decoder circuit are arranged.

Next, a specific structure of the memory cell M mounted on the DRAM will be described with reference to FIG.

As shown in FIG. 2, the DRAM mainly includes a semiconductor substrate 1. The semiconductor substrate 1 is formed of a p-type semiconductor substrate made of, for example, single crystal silicon.

A p-type well region 2 is formed on the main surface of the memory cell array forming region of the semiconductor substrate 1.

The MOSFET Q of the memory cell M is formed on the main surface of the active region of the p-type well region 2. The periphery of the main surface of the active region of the p-type well region 2 is defined by a field insulating film 3 formed on the main surface of the non-active region. That is, the MOSFET Q is the field insulating film 2
Are formed on the main surface of the p-type well region 2 whose periphery is defined.

On the main surface of the p-type well region 2 whose periphery is defined by the field insulating film 3, MOSFETs Q of two memory cells M are formed.

The MOSFET Q mainly includes a p-type well region 2, which is a channel forming region, a gate insulating film 4, a gate electrode 5, and a pair of n, which is a source region and a drain region.
And a pair of n + -type semiconductor regions 9.

The gate insulating film 4 is formed on the main surface of the active region of the p-type well region 2. The gate insulating film 3 is formed of, for example, a thermal silicon oxide film. The gate electrode 5 is formed on the gate insulating film 3. The gate electrode 5 is formed, for example, of an impurity (for example, phosphorus
(P)). Each of the pair of n-type semiconductor regions 7 serving as the source region and the drain region is formed on the main surface of the active region of the p-type well region 2. Each of the pair of n-type semiconductor regions 7 is formed in self-alignment with the gate electrode 5.
Each of the pair of n + -type semiconductor regions 9 serving as the source region and the drain region is formed on the main surface of the active region of the p-type well region 2. Each of the pair of n + -type semiconductor regions 9 is formed in a self-alignment manner with a sidewall spacer 8 that covers a side wall surface of the gate electrode 5 in the gate length direction.

Each of the pair of n-type semiconductor regions 7 as the source region and the drain region is set to have a lower impurity concentration than each of the pair of n + -type semiconductor regions 9 as the source region and the drain region. . That is, MOSFETQ memory cell M LDD (L ightly D oped D rain)
It has a structure.

The gate electrode 5 of the MOSFET Q extends on the gate insulating film 4 in the same direction as the extending direction of the word line WL extending on the field insulating film 2.
L. That is, the gate electrode 5 is electrically connected to the gate electrode 5 of the MOSFET of another memory cell M arranged in the extending direction (Y direction) of the word line WL.

The respective upper surfaces of the gate electrode 5 and the word line WL are covered with an insulating film 6. Also, the gate electrode 5,
Each side wall surface of the word line WL is covered with a side wall spacer 8. The insulating film 6 is formed of, for example, a silicon oxide film. The sidewall spacers 8 are formed by forming, for example, a silicon oxide film on the gate insulating film 4 including the insulating film 6, and then performing anisotropic etching on the silicon oxide film.

A data line DL is electrically connected to one n-type semiconductor region 9 of the MOSFET Q of the memory cell M. The data line DL is formed of, for example, a polycrystalline silicon film 10A into which an impurity for reducing the resistance value is introduced and a tungsten (W) film 10B formed on the surface of the polycrystalline silicon film 10A.

The capacitance element C of the memory cell M is formed on the surface of the interlayer insulating film 11. This capacitive element C
It has an STC structure in which a lower electrode 15, a dielectric film 17, and an upper electrode 18 are sequentially laminated.

The lower electrode 15 includes, for example, an electrode pattern 13 made of a polycrystalline silicon film into which an impurity (for example, phosphorus (P)) for reducing a resistance value has been introduced.
Formed on the surface of the silicon film 14. This silicon film 14 is selectively formed by a selective growth method after patterning the polycrystalline silicon film to form an electrode pattern 13. The dielectric film 17 is, for example,
It is formed of a tantalum pentoxide (Ta ₂ O ₅ ) film which is a high dielectric constant film having a higher dielectric constant than the silicon oxide film and the silicon nitride film. The upper electrode 18 is formed of, for example, a tungsten film.

In the capacitor C, an oxidation preventing film made of a silicon nitride (Si ₃ N ₄ ) film is formed between the lower electrode 13 and the dielectric film 17. Silicon nitride film (Si ₃ N ₄ film)
Because the composition balance between i and N is stable, it is possible to prevent the reaction between O ₅ dielectric film 17 made of Si and tantalum pentoxide (Ta ₂ O ₅₎ film of the lower electrode 15 made of a silicon film it can.

The lower electrode 15 of the capacitive element C is connected to a MOSFE through a connection hole 12 formed in the interlayer insulating film 11.
It is electrically connected to the other n-type semiconductor region 9 of TQ.

Although not shown, the upper electrode 18 of the capacitor C is covered with an interlayer insulating film. A wiring layer is formed on the surface of the interlayer insulating film, and the wiring layer is covered with a final protective film.

The DRAM thus constructed is formed by a manufacturing process using a film forming apparatus shown in FIG. 8 (block diagram). As shown in FIG. 8, the film forming apparatus includes a first chamber 31, a second chamber 32, a third chamber 33, a transfer chamber 34, a load cassette chamber 35, and an unload cassette chamber 36. First chamber 31, second chamber 32, third chamber 33, load cassette 3
5. Each of the unload cassette chambers 36 has a load lock mechanism. The semiconductor substrate 1 in a wafer state set in the load cassette chamber 35 is transferred to the first chamber 31 via the evacuated transfer chamber 34 and processed. The semiconductor substrate 1 processed in the first chamber 31 is
The second chamber 32 via the evacuated transfer chamber 34
And processed. The semiconductor substrate 1 processed in the second chamber 32 is transferred to the third chamber 33 via the evacuated transfer chamber 34 and processed. The semiconductor substrate 1 processed in the third chamber 33 is transferred to the unload cassette chamber 35 through the transfer chamber 34 that has been evacuated.

Next, a method of manufacturing the DRAM will be described.
3 to 8 (cross-sectional views of main parts for explaining a manufacturing method)
This will be described with reference to FIG. The DRAM is manufactured in a wafer state before the semiconductor substrate is divided into a plurality of chip sizes.

First, a semiconductor substrate 1 in a wafer state formed of a p-type semiconductor substrate made of single crystal silicon is prepared.

Next, a p-type well region 2 is formed on the main surface of the memory cell array forming region of the semiconductor substrate 1.

Next, a field insulating film 3 is formed on the main surface of the inactive region of the p-type well region 2. The field insulating film 3 is formed of, for example, a silicon oxide film formed by a known selective oxidation method.

Next, a gate insulating film 4 is formed on the main surface of the active region of the p-type well region 2. The gate insulating film 4 is formed of, for example, a thermal silicon oxide film.

Next, a polycrystalline silicon film and an insulating film are sequentially formed on the entire surface of the semiconductor substrate 1 including the gate insulating film 4 and the field insulating film 3. The polycrystalline silicon film
During or after the deposition, impurities that reduce the resistance value are introduced. Thereafter, the insulating film and the polycrystalline silicon film are sequentially patterned to form a gate electrode 5 whose upper surface is covered with the insulating film 6 and a word line WL whose upper surface is covered with the insulating film 6.

Next, an n-type impurity is introduced into the main surface of the active region of the p-type well region 2 in a self-aligned manner with respect to the gate electrode 5 to form a pair of n-type semiconductor regions 7 serving as a source region and a drain region. Form.

Next, sidewall spacers 8 are formed on the respective sidewall surfaces of the gate electrode 5 and the word lines WL. The sidewall spacers 8 are formed by forming, for example, a silicon oxide film on the gate insulating film 4 including the insulating film 6, and then performing anisotropic etching on the silicon oxide film.

Next, n is self-aligned with the sidewall spacer 8 on the main surface of the active region of the p-type well region 2.
A pair of n-type semiconductor regions 9 serving as a source region and a drain region are formed by introducing a type impurity. In this step, the MOSFET Q of the memory cell M is formed.

Next, a data line DL electrically connected to one n-type semiconductor region 9 of the MOSFET Q is formed.

Next, an interlayer insulating film 11 is formed on the entire surface of the semiconductor substrate 1 including on the data lines DL. Interlayer insulating film 1
1 is formed of, for example, a silicon oxide film.

Next, a MOSFE is formed on the interlayer insulating film 11.
A connection hole 12 exposing the surface of the other n-type semiconductor region 9 of TQ is formed.

Next, as shown in FIG.
Polycrystalline silicon film 13A is formed on the entire surface of semiconductor substrate 1 including the inside. An impurity (for example, phosphorus (P)) that reduces the resistance value during or after the deposition is introduced into the polycrystalline silicon film 13A. This polycrystalline silicon film 13A is formed by, for example, a CVD apparatus.

Next, the semiconductor substrate 1 is transported from the CVD apparatus to a resist coating apparatus. At this time, the polycrystalline silicon film 1
The surface of 3A is exposed to the atmosphere, and a natural silicon oxide film is formed on the surface of polycrystalline silicon film 13A.

Next, in the resist coating apparatus, a photosensitive resist film is formed on the surface of the polycrystalline silicon film 13A. Thereafter, the photosensitive resist film is baked, exposed, developed, and the like, and a resist mask 20 is formed on a predetermined region of the polycrystalline silicon film 13A as shown in FIG. That is, the resist mask 20 is formed by photolithography.

Next, the electrode pattern 13 is formed by patterning the polycrystalline silicon film 13A using the resist mask 20 as an etching mask.

Next, as shown in FIG. 5, the resist mask 20 on the electrode pattern 13 is removed.

Next, the natural silicon oxide film formed on the surface of the electrode pattern 13 is removed. The removal of the natural silicon oxide film is performed by, for example, a removal apparatus using a hydrofluoric acid aqueous solution.

Next, the semiconductor substrate 1 is transferred from the removing apparatus to the load cassette chamber 35 of the film forming apparatus shown in FIG.
At this time, since the surface of the polycrystalline silicon film 13A is exposed to the air, a natural silicon oxide film is formed again on the surface of the polycrystalline silicon film 13A.

Next, the semiconductor substrate 1 is transferred from the load cassette chamber 35 to the first chamber 31 via the transfer chamber 34 evacuated.

Next, in the first chamber 31,
The silicon film 1 is formed on the surface of the electrode pattern 13 by selective growth.
4 is selectively formed. The silicon film 14 is, for example, 30 [n]
m]. The silicon film 14 is formed, for example, under a low pressure of about 1 [Torr] and 1000
In a high-temperature atmosphere of [° C.], H _{2 of} about 10 [SLM] and SiH ₂ Cl _{2 of} about 5 [sccm] are mixed and flown for about 60 seconds. In this step, as shown in FIG. 6, a lower electrode 15 including an electrode pattern 13 and a silicon film 14 is formed. The electrode pattern 1
3 and a silicon film 14, a natural silicon oxide film is formed.
The electrode pattern 13 and the silicon film 14 can be regarded as a single body because the film thickness allows impurities to move from the silicon film 14 to the silicon film 14.

Next, the semiconductor substrate 1 is transferred from the first chamber 31 to the second chamber 32 via the transfer chamber 34 evacuated. At this time, since the surface of the silicon film 4 is not exposed to the atmosphere, no natural silicon oxide film is formed on the surface of the silicon film 4.

Next, in the second chamber 32,
As shown in FIG. 7, silicon nitride is formed on the surface of the silicon film 14.
An anti-oxidation film 16 made of a (Si ₃ N ₄ ) film is formed. This silicon nitride (Si ₃ N ₄ ) film is formed, for example, at 700 to 900
This is performed in an atmosphere at a temperature of about [° C.]. Note that silicon nitride (S
The i ₃ N ₄ ) film may be formed by using either the CVD method or the direct nitriding method.

Next, the semiconductor substrate 1 is transferred from the second chamber 32 to the third chamber 33 via the transfer chamber 34 evacuated. At this time, since the surface of the antioxidant film 16 is not exposed to the air, the surface of the antioxidant film 16 is not contaminated by the impurity contained in the air.

Next, in the third chamber 33,
A dielectric film 1 made of a tantalum pentoxide (Ta ₂ O ₅ ) film is formed on the surface of an oxidation prevention film 16 made of a silicon nitride (Si ₃ N ₄ ) film.
7 is formed. The formation of this tantalum pentoxide (Ta ₂ O ₅ ) film is performed, for example, under the condition that Ta (OC ₂ H ₅ ) is flowed as a process gas into an atmosphere at a temperature of about 400 ° C.

Next, the semiconductor substrate 1 is transferred from the third chamber 33 to the unloading chamber 36 via the transfer chamber 34 evacuated.

Next, the semiconductor substrate 1 is transferred from the unloading chamber 36 to, for example, an electric furnace, and in the electric furnace, for example, the dielectric film 17 is formed in an atmosphere at a temperature of about 700 to 1000 ° C. An oxygen annealing treatment is performed on the tantalum oxide (Ta ₂ O ₅ ) film.

Next, an upper electrode 18 is formed on the surface of the dielectric film 17 by another film forming apparatus. The upper electrode 18 is formed of, for example, a tungsten film. In this step, as shown in FIG. 2, a lower electrode 15 composed of an electrode pattern 13 and a silicon film 14, a dielectric film 17 composed of a tantalum pentoxide (Ta ₂ O ₅ ) film, and an upper electrode 18 composed of a tungsten film
Are sequentially laminated to form a capacitive element C.

Next, an interlayer insulating film is formed to cover the upper electrode 18 of the capacitive element C, a wiring layer is formed on the interlayer insulating film, and a final protective film is formed on the wiring layer. The DRAM of the embodiment is almost completed. Thereafter, the semiconductor substrate 1 is divided into a plurality of chip sizes, and each divided semiconductor substrate 1 is sealed with a package.

As described above, the lower electrode 15 and the dielectric film 1 made of a tantalum pentoxide (Ta ₂ O ₅ ) film as a high dielectric constant film are used.
7. A method of manufacturing a DRAM (semiconductor integrated circuit device) having a capacitive element C in which each of the upper electrodes 18 is sequentially laminated, the method including a step of forming an electrode pattern 13 made of a polycrystalline silicon film 13A into which impurities are introduced; , The electrode pattern 1
Forming a silicon film 14 selectively on the surface of the silicon film 14 by a selective growth method, and forming a lower electrode 15 comprising the silicon film 14 and the electrode pattern 13; Silicon nitride (Si ₃ N) on the surface of the lower electrode
₄ ) forming an antioxidant film 16 made of a film, and forming a dielectric film 17 made of a tantalum pentoxide (Ta ₂ O ₅ ) film, which is a high dielectric constant film, on the surface of the antioxidant film 16; Thereafter, a step of forming an upper electrode 18 on the surface of the dielectric film 17 is provided.

Thus, the electrode pattern 13 and the silicon film 1
After the formation of the lower electrode 15 made of the silicon oxide film 14, the anti-oxidation film 15 is formed on the surface of the lower electrode 15 by the same film forming apparatus.
A natural oxide film is not formed between these two. As a result, a capacitance value corresponding to the total film thickness obtained by adding the film thickness of the antioxidant film 16 to the film thickness of the dielectric film 17 made of a tantalum pentoxide (Ta ₂ O ₅ ) film which is a high dielectric constant film is obtained. Therefore, the amount of charge stored in the capacitor C can be increased.

A natural silicon oxide film is formed between the electrode pattern 13 and the silicon film 14. The thickness of the natural silicon oxide film is such that impurities can move from the electrode pattern 13 to the silicon film 14. , Electrode pattern 13 and silicon film 14
Can be regarded as one.

Further, since the amount of charge stored in the capacitor C can be increased, the plane size of the memory cell can be further reduced, and the degree of integration of the DRAM can be increased correspondingly.

In the above embodiment, the dielectric film 17 of the capacitance element C is formed of a tantalum pentoxide (Ta ₂ O ₅ ) film, but is formed of another type of tantalum oxide (TaxOx) film. Is also good. In this case, the same effect as in the above-described embodiment can be obtained.

The dielectric film 17 of the capacitive element C is made of a high dielectric constant film such as a strontium titanate ((Ba, Sr) TiO ₃ ) film, a PTO (PbTiO ₃ ) film,
PZT (Pb (Zr, Ti) O ₃ ) film or PLZT ((Pb,
La) (Zr, Ti) O ₃ ) film. In this case, the same effect as in the above-described embodiment can be obtained.

The electrode pattern 13 of the lower electrode 15 of the capacitor C may be formed of an amorphous silicon film. In this case, the same effect as in the above-described embodiment can be obtained.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

[0075]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

A lower electrode, a dielectric film made of a high dielectric constant film,
In a semiconductor integrated circuit device having a capacitor in which each of the upper electrodes is sequentially stacked, the amount of charge stored in the capacitor C can be increased.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a memory cell mounted on a DRAM according to an embodiment of the present invention.

FIG. 2 is a sectional view of a main part of the DRAM.

FIG. 3 is a fragmentary cross-sectional view for explaining the method for manufacturing the DRAM.

FIG. 4 is a fragmentary cross-sectional view for explaining the method for manufacturing the DRAM.

FIG. 5 is a fragmentary cross-sectional view for explaining the method for manufacturing the DRAM.

FIG. 6 is an essential part cross sectional view for describing the method of manufacturing the DRAM;

FIG. 7 is a fragmentary cross-sectional view for describing the method for manufacturing the DRAM.

FIG. 8 is a block diagram showing a schematic configuration of a film forming apparatus used in a manufacturing process of the DRAM.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate, 2 p-type well region, 3 field insulating film, 4 gate insulating film, 5 gate electrode, 7 n-type semiconductor region, 9 n-type semiconductor region, 11 interlayer insulating film,
12 ... connection hole, 13 ... electrode pattern, 14 ... silicon film, 1
5 lower electrode, 16 antioxidant film, 17 dielectric film, 1
8: Upper electrode, C: Capacitance element, Q: MOSFET, M ...
Memory cells, WL: word lines, DL: data lines.

Claims (5)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device having a capacitor in which a lower electrode, a dielectric film made of a high dielectric constant film, and an upper electrode are sequentially laminated, wherein the first silicon film doped with an impurity is provided. Forming an electrode pattern composed of: and selectively forming a second silicon film on the surface of the electrode pattern by a selective growth method, and forming a lower electrode composed of the second silicon film and the electrode pattern. Forming an antioxidant film on the surface of the lower electrode using the same film forming apparatus as the second silicon film; and forming a dielectric film made of a high dielectric constant film on the surface of the antioxidant film. Forming a top electrode on the surface of the dielectric film, and thereafter forming a semiconductor integrated circuit device. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step of forming the electrode pattern includes the step of forming a first silicon film into which an impurity is introduced.
Forming a resist mask on a predetermined region of the first silicon film using a photolithography technique; and patterning the first silicon film using the resist mask as an etching mask. A method of manufacturing a semiconductor integrated circuit device. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said oxidation preventing film is a silicon nitride film, and said high dielectric constant film is a silicon oxide film and a silicon nitride film. A method of manufacturing a semiconductor integrated circuit device, comprising: a tantalum oxide film, a barium strontium titanate film, a PTO film, a PZT film, or a PLZT film having a higher dielectric constant than that of a semiconductor integrated circuit device. 4. One of claims 1 to 3
The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step of selectively forming a second silicon film on the surface of the electrode pattern by a selective growth method includes forming the second silicon film on the surface of the electrode pattern. A method for manufacturing a semiconductor integrated circuit device, comprising a step of removing a natural silicon oxide film. 5. The method according to claim 1, wherein:
13. The method for manufacturing a semiconductor integrated circuit device according to item 8, wherein the capacitance element is a capacitance element of a memory cell that stores 1-bit information.