JP3162440B2 - Method for manufacturing solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a charge transfer device.
And a method for manufacturing a solid-state imaging device.

[0002]

2. Description of the Related Art A charge transfer element is constituted by using a buried n-type transfer channel using two or three layers of polysilicon gates. In order to transfer efficiently in a continuous channel, a three-layer structure (generally called an ONO film) of a silicon oxide film, a silicon nitride film, and a silicon oxide film is often used for a gate insulating film. This is because a gate insulating film having the same thickness is used to suppress the fluctuation of the potential in the transfer path, and a thick silicon oxide film formed under the lower gate end when forming a second or more gate. (So-called gate bird's beak) is suppressed. Also, the dielectric strength is improved as compared with a simple silicon oxide film.

An example of a charge transfer device using an ONO film is disclosed in Japanese Patent Application Laid-Open No. 220450/1990. Next, the charge transfer device disclosed in the above publication and a method for manufacturing the same will be described with reference to the drawings. FIG.
FIG. 1 shows a cross-sectional view of the charge transfer device. In FIG. 11, 1
Is a charge transfer section, 2 is a peripheral circuit section, 3 is a semiconductor substrate, 4 is an isolation region for electrically separating the charge transfer section 1 from the peripheral circuit section 2, and 5 is silicon as a gate insulating film of the charge transfer section 1. An oxide film, 6 is a silicon nitride film, 7 is a silicon oxide film, and 8 is a laminated insulating film composed of a silicon oxide film 5, a silicon nitride film 6, and a silicon oxide film 7. 9
Is a first transfer electrode, 10 is a silicon oxide film, and 11 is a second transfer electrode.
Transfer electrode. Reference numeral 12 denotes a gate insulating film of the peripheral circuit section 2, 13 denotes a source / drain, and 14 denotes a gate electrode. Reference numeral 16 denotes a surface protective film.

As described above, in the conventional charge transfer device, while the laminated insulating film 8 is formed as the gate insulating film below the transfer electrodes 9 and 11 of the charge transfer unit 1, the peripheral circuit unit 2
The gate insulating film 12 is composed of a single-layer insulating film.
In such a configuration, since the gate electrode of the peripheral circuit unit 2 is formed of a single-layer insulating film, it is easy to obtain a desired threshold voltage. Since the electrodes 9 and 11 are formed on the laminated insulating film 8, there is no possibility that the pinhole phenomenon occurs.

FIG. 12 is a cross-sectional view in the order of steps for explaining a method of manufacturing the charge transfer device of FIG. Here, FIG.
The manufacturing method will be described in detail below using the numbers used in the above. First, as shown in FIG.
An isolation insulating film 4 is formed on a semiconductor substrate 3. Next, FIG.
As shown in FIG. 2B, a silicon oxide film 5 is formed on the semiconductor substrate 3 by thermal oxidation. Subsequently, a silicon nitride film 6 is formed on the silicon oxide film 5 by a CVD method. Further, a silicon oxide film 7 is formed on the silicon nitride film 6. Thus, the laminated insulating film 8 is obtained .

[0006] Next, as shown in FIG.
The transfer electrode 9 of the layer is formed by the CVD method and the selective etching. Further, a silicon oxide film 10 as an interlayer insulating film is formed. Next, as shown in FIG.
The charge transfer unit 1 is covered with a resist 15. Then, the laminated insulating film 8 formed on the peripheral circuit section 2 is removed by etching using the resist 15 as a mask.

Next, as shown in FIG. 12E, the surface of the semiconductor substrate 3 is thermally oxidized to form a gate insulating film 12 in the peripheral circuit section 2. Next, the transfer electrode 11 and the gate electrode 14 are formed of the second layer of polycrystalline silicon. Finally,
Source / drain 13 is formed in peripheral circuit section 2.

[0008]

[Problems to be solved by the invention]

[0009]

[0010]

In the above-mentioned conventional configuration, it is not possible to set a plurality of types of film thickness of the gate insulating film of the MIS transistor. Cannot be used together with a transistor used only as a transistor. In addition, in the method of manufacturing the charge transfer element, the thickness of the silicon oxide film in the peripheral circuit portion is composed of only one type, and a plurality of types of the silicon oxide film cannot be formed according to the purpose of the peripheral circuit. .

Further, the ONO film formed on the charge transfer portion is once removed to form the gate insulating film of the peripheral circuit portion. For this reason, the process becomes complicated, and the first transfer electrode is formed in the upper layer of the charge transfer section when the gate insulating film of the peripheral circuit section is formed. If the gate insulating film is oxidized in this state, a silicon oxide film exposed above the ONO film grows, and becomes a bird's beak of the first transfer electrode, resulting in deterioration of the characteristics of the charge transfer element.

Further, since the silicon oxide film with the exposed ONO film grows due to the formation of the gate insulating film in the peripheral circuit portion, the thickness of the insulating film immediately below the first transfer electrode and the thickness of the insulating film immediately below the second transfer electrode are increased. There is a difference in film thickness. For this reason, a uniform channel is not formed immediately below the transfer electrode, which causes deterioration in the reliability of characteristics as a charge transfer element. In addition, the region where the silicon nitride film of the peripheral circuit portion is removed is affected by the stress when the isolation region is formed, and causes a fatal defect in the peripheral circuit characteristics.

Further, when different transistors are formed in the peripheral circuit portion, only transistors having a single silicon oxide film thickness can be obtained.

[0015]

[0016] The purpose of this invention is
A transistor that reduces noise by reducing the resistance,
A transistor used only as a resistor, such as a load transistor
Transistors can coexistSolid-state imaging deviceManufacturing of
Is to provide a way.

Another object of the present invention is to provide a method of manufacturing a solid-state imaging device capable of changing the thickness of a silicon oxide film according to the purpose of a peripheral circuit section.

[0018]

[Means for Solving the Problems]

[0019]

[0020]

[0021]

According to a first aspect of the present invention, there is provided a method of manufacturing a solid-state imaging device, comprising: forming a first silicon oxide film on a main surface of a semiconductor substrate ; and forming a silicon nitride film on the first silicon oxide film. Removing the silicon nitride film in a first region to be a peripheral circuit portion; removing the first silicon oxide film in the first region; and a second portion to be a charge transfer portion Forming a second silicon oxide film on the semiconductor substrate in a state where the silicon nitride film is entirely exposed on an upper surface of the region, and forming a first transfer electrode in the second region, Forming a gate electrode in the first region through the second silicon oxide film; forming a third silicon oxide film on the semiconductor substrate; and forming the third silicon oxide film through the third silicon oxide film. Second
And forming a second transfer electrode in the region.

The manufacturing method of a solid-state imaging device according to claim 2 includes the steps of forming a first silicon oxide film on the semiconductor substrate main surface, and then forming a silicon nitride film on the first silicon oxide film Removing the silicon nitride film in a third region in a first region to be a peripheral circuit portion, and then removing the first silicon oxide film in a third region in the first region And forming a second silicon oxide film on the semiconductor substrate in a state where the silicon nitride film is entirely exposed on the upper surface of a second region serving as a charge transfer portion. Forming a first transfer electrode in the first area and simultaneously forming a first gate electrode in the third area in the first area via the second silicon oxide film; and then forming the first area in the first area 4th territory of
Removing the silicon nitride film in the region, forming a third silicon oxide film on the semiconductor substrate, and then performing a second transfer to the second region via the third silicon oxide film. Forming a second gate electrode in the fourth region in the first region via the third silicon oxide film at the same time as forming the electrode.

[0024]

[Action]

[0025]

[0026]

[0027]

[0028]

According to the present invention, the thickness of the gate insulating film of the MIS transistor can be set to an optimum value in the peripheral circuit portion depending on the application. Therefore, it is possible to easily reduce the size of the device and optimize the device characteristics. Furthermore, since the thickness of the gate insulating film of the MIS transistor can be arbitrarily selected, a transistor that reduces on-resistance at the time of switching and reduces noise and a transistor such as a load transistor that is used only as a resistor coexist. be able to. Therefore, may become the transconductance g _m is large, it is not necessary to increase the size of the transistor. Further, it is possible to prevent the additional capacity from being increased and the high frequency characteristics from being deteriorated.

According to the present invention, since the silicon nitride film in the peripheral circuit portion is removed, the MIS transistor can be formed in a portion where the influence of the interface state is small.
Therefore, the threshold voltage _Vth does not deteriorate due to the stress. Further , according to the present invention, since the gate insulating film of the peripheral circuit portion is simultaneously formed on the charge transfer portion having the silicon nitride film as the upper surface, the process is simple, and the thickness of the gate insulating film is changed according to the purpose. it can.

Further, since the first transfer electrode of the charge transfer section and the gate electrode of the peripheral circuit section can be formed in a self-aligned manner, the process is easy. When a different transistor is formed in the peripheral circuit section, the gate insulating film of the peripheral circuit, the first transfer electrode of the charge transfer section, and the gate electrode of the peripheral circuit section are formed in a self-aligned manner in the charge transfer section. ,
Further, a gate insulating film of a different transistor can be formed simultaneously with an insulating film for electrically isolating the first transfer electrode. At this time, the gate electrode and the second transfer electrode of a different transistor can be formed at the same time. Therefore, the process is easy.

According to the present invention, a stacked film of a silicon oxide film and a silicon nitride film is removed to form a gate insulating film in a peripheral circuit portion. For this reason, the process is simpler than the conventional one. Further, when the gate insulating film of the peripheral circuit portion is formed, a silicon nitride film is formed above the charge transfer portion. When the gate insulating film is oxidized in this state, the silicon nitride film does not change, that is, 5 nm.
Only by forming a silicon oxide film of a degree, a gate insulating film of a peripheral circuit portion can be formed at the same time.

For this reason, the thickness of the insulating film immediately below the first transfer electrode and the thickness of the insulating film immediately below the second transfer electrode become substantially uniform.

[0034]

Embodiments of the present invention will be described below with reference to the drawings. First, the solid-state imaging in the present invention
In a solid-state imaging device manufactured by a device manufacturing method,
Details of the first example of the charge transfer element will be described. Figure 1 shows a sectional view of the charge transfer device. Sectional view shown here, that is disposed and a surface channel MIS transistor comprising an end portion and a peripheral circuit portion of the buried channel type charge transfer sections.

A p-type diffusion layer 52 is formed on the main surface of n-type silicon substrate 51. The impurity concentration of the p-type diffusion layer 52 is 1 to 5 × 10 ¹⁶ / cm ³ . The impurity concentration affects the saturation capacity and transfer efficiency of the signal charge of the CCD channel described below. For this reason, it is necessary to keep a predetermined impurity concentration. Also, the p-type diffusion layer 52
Is formed to be about 5 μm from the surface of the silicon substrate 51. The depth of the p-type diffusion layer 52 has a relationship with the withstand voltage with respect to the silicon substrate 51. For this reason, a predetermined depth is set in accordance with the impurity concentration so that the withstand voltage does not deteriorate.

An n-type diffusion layer 53 serving as a CCD channel is formed at a portion where the buried charge transfer section is formed in the p-type diffusion layer 52. The impurity concentration of the n-type diffusion layer 53 is 5 to 10 × 10 ¹⁶ / cm ³ . The impurity concentration is p
Like the diffusion layer 52, it affects the saturation capacity and transfer efficiency of signal charges in the CCD channel. For this reason, it is necessary to keep a predetermined impurity concentration.

As described above, the impurity concentration of the n-type diffusion layer 53 is related to the impurity concentration of the p-type diffusion layer 52. That is, the potential applied to these diffusion layers is optimized so that the channels of the CCD are depleted. The depth of the n-type diffusion layer 53 is about 0.5 μm from the surface of the silicon substrate 51.
m. The depth of the n-type diffusion layer 53 is set to an appropriate depth so that the transfer efficiency and the saturation capacity do not deteriorate.

The substrate edge on the surface of the silicon substrate 51 has MI
An S transistor is formed. The MIS transistor and the buried charge transfer section are electrically insulated by a thick oxide film isolation region 54 called LOCOS. An n-type diffusion layer 55 serving as a source and a drain is formed in the MIS transistor region.

Silicon substrate 51 of embedded charge transfer section
A silicon oxide film 56 is formed on the surface. The silicon oxide film 56 is formed to a thickness of about 80 nm by thermally oxidizing the silicon substrate 51 to be a gate insulating film. The thickness of the silicon oxide film 56 affects the transfer efficiency of the charge transfer element and the saturation characteristic of the CCD channel for signal charges. For this reason, 10 nm to 2
The thickness is preferably set to 00 nm.

When the film thickness is less than 10 nm, the value (φ _L ) of the driving voltage on the low voltage side becomes too low. That is, the pulse amplitude of the drive voltage decreases. For this reason, the transfer efficiency deteriorates. If the film thickness is 200 nm or more, the value (φ _H ) of the driving voltage on the high voltage side becomes too high. For this reason, it is necessary to make the pulse generator for driving high withstand voltage. This is not very practical.

In order to lower the driving voltage, the impurity concentration of the n-type diffusion layer 53 must be reduced.
There is a disadvantage that the saturation capacity of the signal charge of the D channel is reduced. On the silicon oxide film 56, a reduced pressure CV
A silicon nitride film 57 having a thickness of 40 nm formed by the method D is formed. As described above, in the embedded charge transfer section, a stacked film of the silicon oxide film 56 and the silicon nitride film 57 is used as the gate insulating film.

The thickness of the silicon nitride film 57 affects the withstand voltage of the charge transfer element and the saturation characteristic of signal charges of the CCD channel. For this reason, 10 nm to 100 n
m. When the film thickness is 10 nm or less, the withstand voltage is deteriorated and the stability of film formation is deteriorated. For this reason, there is a disadvantage that the reliability of the device is deteriorated.

If the thickness is 100 nm or more, the total thickness of the gate insulating film becomes large and the silicon oxide film 56 becomes thick.
As in the case where the thickness is large, the driving voltage increases or the saturation capacity of the signal charge of the CCD channel decreases. Also,
The silicon nitride film 57 has a large amount of charge trap levels in the film. As the film thickness increases, the amount of trap levels increases. If the charge transfer element is used for a long time, the effective voltage applied to the CCD channel changes, and the reliability of the element deteriorates.

The transfer electrode 58 is formed on the silicon nitride film 57.
Are formed. The transfer electrode 58 is formed of the silicon oxide film 5
9 and is electrically separated from the adjacent transfer electrode 60. The transfer electrodes 58 and 60 are formed of a polycrystalline silicon film doped with phosphorus. The thickness of the polycrystalline silicon film is about 0.2 to 0.6 μm. Here, it is important that the end of the silicon nitride film 57 and the end of the polycrystalline silicon film of the transfer electrode 58 match. Silicon nitride film 5
If the the end portion of the polycrystalline silicon film of the transfer electrode 58 end of 7 to try one <br/> Itasa, silicon nitride film 57 surface layer on the buried type charge transfer portion, the transfer electrodes 58 and 60 and silicon It will be completely covered with the oxide film 59.
Thus, the gate electrodes 58 and 60 and the silicon oxide film 5
Stress applied to the entire charge transfer devices by eliminating the silicon nitride film 5 7 except the bottom of 9 can be reduced.

Further, even when this charge transfer element is used as a solid-state imaging device, light incident on the photodiode is not attenuated because there is no silicon nitride film. To explain this in more detail, FIG.
The electric charge transferring elements Nico shows the cross-sectional shape when used in the solid-state imaging device.

A p-type diffusion layer 61 is formed from the surface of the silicon substrate 51 in the depth direction of the substrate. p-type diffusion layer 61
In the figure, a charge transfer section A and a photodiode section B are formed. In the charge transfer section A, the p-type diffusion layer 52 is formed from the surface of the silicon substrate 51 in the depth direction of the substrate.
An n-type diffusion layer 53 is formed thereon. A diffusion layer 62 is formed adjacent to the n-type diffusion layer 53.

Further, a photodiode portion B is formed adjacent to the diffusion layer 62. The photodiode section B is provided with an n-type diffusion layer 63 having a certain depth,
Further, a p-type diffusion layer 64 is provided above the n-type diffusion layer 63 on the surface of the silicon substrate 51. Normally, light incident on the photodiode section B forms an electron pair in these diffusion layers. Thus, light can be converted into an electric signal.

On the silicon substrate 51, a silicon oxide film 56 is formed on the entire surface of the substrate. Silicon oxide film 56
Above, a silicon nitride film 57 is formed in a region substantially corresponding to the charge transfer portion A. Further, the silicon nitride film 5
Polycrystalline silicon to be the transfer electrode 58 is formed on 7. Further, a silicon oxide film 65 for insulation is formed so as to surround the transfer electrode 58. The solid-state imaging device transfers the signal that has entered the photodiode unit B and is electrically extracted through a channel immediately below the transfer electrode 58.

Therefore, the transfer electrode 58 and the photodiode section B have a pair of structures. A solid-state imaging device is formed by forming a plurality of these components. The plurality of paired elements are electrically insulated from the adjacent paired elements by the diffusion layer 66. A certain transfer electrode 58
And the silicon substrate 51 in the opening region 67 of the adjacent transfer electrode 58
A photodiode section B is formed immediately below. On the silicon substrate 51 on which the photodiode portion B is formed, only the silicon oxide film 56 is formed. Normal,
When a gate insulating film of such a multilayer transfer electrode is used, the multilayer film is left on the photodiode portion B, but the incident light is attenuated. However, with such a method, it has been difficult to fulfill the demand for higher sensitivity of the solid-state imaging device.

On the other hand, in FIG. 1, a normal MIS transistor is formed in the MIS transistor region. That is, a silicon oxide film 68 serving as a gate insulating film is formed with a thickness of 50 nm on the surface of the silicon substrate 51 between the source and the drain. Further, a gate electrode 69 is formed on the silicon oxide film 68. Gate electrode 69 is formed of a polycrystalline silicon film doped with phosphorus. The film thickness of the polycrystalline silicon is about 0.2-0.
6 μm.

In the charge transfer element configured as described above, even if a stacked film of a silicon oxide film and a silicon nitride film is used for the gate insulating film in the buried charge transfer portion, the transfer characteristics may be adversely affected. Absent. On the other hand, when such a stacked film composed of a silicon oxide film and a silicon nitride film is used as a gate insulating film of a MIS transistor constituting a peripheral circuit portion like a conventional charge transfer element, a single-layer gate of a silicon oxide film is used. As compared with the case of the first example using the insulating film, the transistor characteristics are deteriorated by the interface states generated in the stacked film and the trap states existing in the insulating film.
As the interface state density of the stacked film increases, noise characteristics and frequency characteristics of the MIS transistor deteriorate. Also,
As the trap density in the film increases, the threshold voltage V _th of the MIS transistor shifts, and the mutual conductance g _m deteriorates. Due to these factors, the reliability of the charge transfer element using the stacked film is reduced.

In the charge transfer device of the first example, the device characteristics do not deteriorate as in the MIS transistor of the conventional charge transfer device. In order to describe the effects as described above in more detail, FIG. 3 shows the charge transfer device of the first example and an M-type transistor using a conventional laminated film as a gate insulating film.
FIG. 4 is a diagram comparing amplifier noise and frequency characteristics of a charge transfer element having an IS transistor and a gate insulating film type of an amplifier section;

In the figure, black circles indicate frequency characteristics, and white circles indicate amplifier noise. The type of the gate insulating film is written as SiO _{2 in} the MIS transistor of the first example. ONO indicates a conventional MIS transistor. Thus, the MIS transistor of the first example has low amplifier noise and can be suppressed to about 2/5 times that of the conventional MIS transistor. For this reason, when the operation of the charge transfer element is performed, minute signal charges can be sufficiently amplified.

The frequency characteristic of the MIS transistor of the first example can be about 1.4 times higher than that of the conventional MIS transistor. Figure 4 shows a cross-sectional view of a second embodiment of <br/> charge transfer device. Sectional view shown here, that is the surface channel MIS transistor comprising an end portion and a peripheral circuit portion of the buried channel type charge transfer sections arranged.

The difference from the charge transfer element of the first example is that C
The laminated film provided on the channel portion of the CD is formed of a laminated film called an ONO film made of a silicon oxide film and a silicon oxide film further above the silicon oxide film and the silicon nitride film. That is, the p-type diffusion layer 52 is formed on the surface of the main surface of the silicon substrate 51. An n-type diffusion layer 53 serving as a CCD channel is formed at a portion where the buried charge transfer section is formed by the p-type diffusion layer 52.

At the edge of the substrate on the surface of the silicon substrate 51, M
An IS transistor is formed. The MIS transistor and the buried charge transfer section are electrically insulated by a thick oxide film isolation region 54 called LOCOS. An n-type diffusion layer 55 serving as a source and a drain is formed in the MIS transistor region.

Silicon substrate 51 of embedded charge transfer section
A silicon oxide film 56 is formed on the surface. The silicon oxide film 56 is formed to a thickness of about 80 nm by thermally oxidizing the silicon substrate 51 to be a gate insulating film. On the silicon oxide film 56, a reduced pressure CV
A silicon nitride film 57 having a thickness of 40 nm formed by the method D is formed.

Further, a silicon oxide film 70 is formed on silicon nitride film 57. The thickness of the silicon oxide film 70 is about 5 nm. The silicon oxide film 70 is formed simultaneously when a silicon oxide film that is a gate insulating film of the MIS transistor is formed in a manufacturing process described later. When forming the gate insulating film of the MIS transistor, the region of the charge transfer element
And a silicon nitride film 57 are laminated. When the silicon oxide film 68 as the gate insulating film is formed, the surface of the silicon nitride film 57 is oxidized by 5 nm.

This thickness changes according to the change of the thickness of the gate insulating film of the MIS transistor. However, the oxide film thickness does not exceed several tens of nm.
Further, such an ON state is formed in the gate insulating film of the charge transfer element.
By forming the O film, the reliability of the withstand voltage is improved.
Further, since the gate insulating film is formed of a laminated film of two or more layers, the thickness of the insulating film is constant under any electrode. Therefore, the potential under the electrode does not change. Normally, the gate insulating film below the gate electrode is oxidized in a subsequent step, and abnormal oxidation at the electrode end called bird's beak occurs. However, bird's beak is not caused by subsequent oxidation when used as the gate insulating film a multilayer film as in the example of this, it is possible to form a uniform channel.

The effect described in the first example can also be sufficiently obtained. Further, a transfer electrode 58 is formed on the silicon nitride film 57. The transfer electrode 58 is electrically separated from an adjacent transfer electrode 60 via a silicon oxide film 59. The transfer electrodes 58 and 60 are formed of a polycrystalline silicon film doped with phosphorus. The thickness of the polycrystalline silicon film is about 0.2 to 0.6 μm.

Here, the end of the silicon nitride film 57 and the end of the polycrystalline silicon film of the transfer electrode 58 are aligned.
A normal MIS transistor is formed in the MIS transistor region. That is, a silicon oxide film 68 serving as a gate insulating film is formed with a thickness of 50 nm on the surface of the silicon substrate 51 between the source and the drain. Further, a gate electrode 69 is formed on the silicon oxide film 68. Gate electrode 69 is formed of a polycrystalline silicon film doped with phosphorus. The thickness of the polycrystalline silicon is about 0.2 to 0.6 μm.

In the charge transfer device configured as described above, even if a stacked film of a silicon oxide film and a silicon nitride film is used for the gate insulating film in the buried charge transfer portion, the transfer characteristics may be adversely affected. Absent. On the other hand, when a stacked film including such a silicon oxide film, a silicon nitride film, and a silicon oxide film is used for a gate insulating film of a MIS transistor that forms a peripheral circuit portion like a conventional charge transfer element,
A gate insulating film of a single layer of silicon oxide film as compared with the case of the example of Mochiiruko, the transistor characteristics are lower degradation by trap level is present at the interface level and the insulating film caused in the laminated film. As the interface state density of the laminated film increases, the MIS
Noise characteristics and frequency characteristics of the transistor deteriorate. In addition, an increase in trap density in the film causes an increase in MIS.
Or shifted threshold voltage V _th of the transistor, the transconductance g _m is deteriorated. Due to these factors, the reliability of the charge transfer element using the stacked film is reduced.

[0063] In the charge transfer device of the example of this, since the gate insulating film of the MIS transistor is formed of a silicon oxide film of a single layer, that the device characteristics as MIS transistors of the conventional charge transfer device is degraded There is no. In Figure 5
It shows a cross-sectional view of a third example of the electric charge transferring elements. Sectional view shown here, that is the surface channel MIS transistor comprising an end portion and a peripheral circuit portion of the buried channel type charge transfer sections arranged.

A p-type diffusion layer 52 is formed on the main surface of n-type silicon substrate 51. The impurity concentration of the p-type diffusion layer 52 is about 1 to 5 × 10 ¹⁶ / cm ³ . The impurity concentration is
This affects the saturation capacity and transfer efficiency of signal charges in the CCD channel. For this reason, it is necessary to keep a predetermined impurity concentration. The depth of the p-type diffusion layer 52 is formed to be about 5 μm from the surface of the silicon substrate 51. The depth of the p-type diffusion layer 52 is
Is set in accordance with the impurity concentration and the voltage to be applied so that the dielectric breakdown voltage between the two does not decrease.

An n-type diffusion layer 53 serving as a CCD channel is formed in a portion where the buried charge transfer section is formed in the p-type diffusion layer 52. The impurity concentration of the n-type diffusion layer 53 is 5 to 10 × 10 ¹⁶ / cm ³ . The impurity concentration affects the saturation capacity of the signal charge of the CCD channel described below. For this reason, it is necessary to keep a predetermined impurity concentration.

The impurity concentration of the n-type diffusion layer 53 is p
The potential applied to these diffusion layers is optimized so that the channels of the CCD are depleted in relation to the impurity concentration of the diffusion layers 52. Further, the depth of the n-type diffusion layer 53 is formed to be about 0.5 μm from the surface of the silicon substrate 51. The depth of the n-type diffusion layer 53 is
It is set appropriately in accordance with the impurity concentration so that the withstand voltage between them does not deteriorate.

The edge of the substrate on the surface of the silicon substrate 51 has M
An IS transistor is formed. The MIS transistor and the embedded charge transfer section are electrically insulated by an isolation region 54 called LOCOS. MIS
An n-type diffusion layer 55 serving as a source / drain is formed in the transistor region.

Silicon substrate 51 of buried charge transfer section
A silicon oxide film 56 is formed on the surface. The silicon oxide film 56 is formed to a thickness of about 80 nm by thermally oxidizing the silicon substrate 51 to be a gate insulating film. The thickness of the silicon oxide film 56 affects the transfer efficiency of the charge transfer element and the saturation characteristics of signal charges in the CCD channel. Therefore, 10 nm to 20
The thickness is preferably 0 nm. It is necessary to use this film thickness in the range specified here for the same reason as in the first example .

On the silicon oxide film 56, a silicon nitride film 57 having a thickness of 40 nm formed by a low pressure CVD method. As described above, in the embedded charge transfer section, a stacked film of the silicon oxide film 56 and the silicon nitride film 57 is used as the gate insulating film. The thickness of the silicon nitride film 57 affects the withstand voltage of the charge transfer element and the saturation characteristics of signal charges in the CCD channel. Therefore, 10n
The thickness is preferably from m to 100 nm. This film thickness also needs to be formed in a film thickness in the range shown here for the same reason as shown in the first example .

The transfer electrode 58 is formed on the silicon nitride film 57.
Are formed. The transfer electrode 58 is formed of the silicon oxide film 5
9 and is electrically separated from the adjacent transfer electrode 60. The transfer electrodes 58 and 60 are formed of a polycrystalline silicon film doped with phosphorus. The thickness of polycrystalline silicon is
It is about 0.5 μm. On the other hand, a normal MIS transistor is formed in the MIS transistor region. That is, a silicon oxide film 71 serving as a gate insulating film has a thickness of 50 n on the surface of the n-type diffusion layer 52 between the source and the drain.
m. Further, a gate electrode 72 is formed on the silicon oxide film 71. Gate electrode 72
Is formed of a polycrystalline silicon film doped with phosphorus. The thickness of the polycrystalline silicon is about 0.5 μm.

Further, another MIS transistor having a common source or drain of the MIS transistor is also formed. This MIS transistor has p
On the surface of the mold diffusion layer 52, a silicon oxide film 73 serving as a gate insulating film is formed with a thickness of 100 nm. Further, a gate electrode 74 is formed on the silicon oxide film 73. Gate electrode 74 is formed of a polycrystalline silicon film doped with phosphorus. The thickness of the polycrystalline silicon is about 0.4 μm.

The difference between the two MIS transistors described above is that the thicknesses of the silicon oxide films 71 and 73 serving as the gate insulating films of the two are different. The gate insulating film of the embedded charge transfer section is formed of a laminated film, and the charge transfer element is formed such that the gate insulating films of the MIS transistors of the peripheral circuit section have at least two different thicknesses. On the point.

When a thin film having a constant thickness is formed on the gate insulating film of the MIS transistor in the peripheral circuit portion (particularly, the amplifier portion, etc.) of the charge transfer element, the MIS transistor determined according to the purpose of use of the peripheral circuit portion is formed. If it must, the desired properties cannot be obtained. For example, in an MIS transistor using a thin gate insulating film, on-resistance at the time of switching of the transistor is reduced, noise can be reduced, and element characteristics can be improved. However, it is to be used only as a resistor as a load transistor MIS transistor, the transconductance g _m is increased. Therefore, in order to provide a predetermined resistance value, the size of the transistor that must be formed when the thickness of the gate insulating film is small must be increased. In order to form MIS transistors having different purposes in the peripheral circuit portion as described above, it is necessary to use a gate insulating film having a desired thickness suitable for each MIS transistor.

Further, in such a peripheral circuit section, the additional capacitance also increases. For this reason, the high frequency characteristics deteriorate. Example of this, it is possible to form a MIS transistor having a gate insulating film thickness optimal for some applications. Therefore, it is possible to easily reduce the size of the device and optimize the device characteristics.

In the charge transfer device configured as described above, even if a stacked film of a silicon oxide film and a silicon nitride film is used for the gate insulating film in the embedded charge transfer portion, the transfer characteristics are hardly affected. On the other hand, M
When such a laminated film is used for the gate insulating film of the IS transistor, compared with the case where a single-layered gate insulating film of a silicon oxide film is used, the interface state generated in the laminated film and in the insulating film are present. Transistor characteristics deteriorate due to the trap level. In the charge transfer device of this example has never deterioration in characteristics of the MIS transistor of such a charge transfer device occurs.

[0076] shows the plan view of one transistor for explaining the area where the silicon nitride film is removed of the MIS transistor in the peripheral circuit portion in FIG. 6. The hatched area 75 is the area from which the silicon nitride film has been removed. An MIS transistor is formed on the surface of an n-type diffusion layer of a silicon substrate. MI
The S transistor is provided with an isolation region 76 called LOCOS so as to be electrically isolated from peripheral elements.
The separation area 76 is provided around the rectangle. Oblique line 7
The region 5 is slightly smaller than the separation region 76. The hatched area 75 also has a rectangular shape like the separation area 76.

A gate electrode 77 is formed substantially at the center of the isolation region 76. In the left and right n-type diffusion layers on the long side of the gate electrode 77, diffusion layers serving as the source and drain of the MIS transistor are formed. The source / drain contact holes 78 are formed by etching predetermined positions of a protective film provided above the MIS transistor. A wiring 79 connected to the source / drain diffusion layer through the contact hole 78 is formed.

As described above, the region where the silicon nitride film of the peripheral circuit portion is removed is formed at a predetermined position in order to reduce the influence of the interface state. The position is formed in a flat portion formed in the isolation region 76 so that the stress generated at the time of forming the LOCOS has no adverse effect. Such a flat portion extends from the end of the separation region 76 to the separation region 7.
6 and the thickness of the silicon oxide film that is partially removed by etching the silicon nitride film.

In the first example , the thickness of the isolation region 76 is 50
At 0 nm, the thickness of the silicon oxide film to be removed by etching is 80 nm. 0.58 from the separation area 76
If the distance from the end of the separation region 76 is at least μm, the influence of the stress is small. If the peripheral circuit portion is formed in a region affected by the stress, reliability problems such as an increase in interface order and a decrease in threshold voltage _Vth will occur.

[0080] illustrates a cross-sectional view of a fourth example of FIG. 7 second electrodeposition charge transferring elements. The cross-sectional view shown here shows an end of a buried channel type charge transfer section and a surface channel MI serving as a peripheral circuit section.
S transistor are located. 5 is different from the charge transfer device of the example of FIG. 5 in that the stacked film provided on the channel portion of the CCD has a three-layer structure including a silicon oxide film, a silicon nitride film, and a silicon oxide film as an upper layer, that is, ONO.
It is formed of a laminated film called a film.

That is, the p-type diffusion layer 52 is formed on the main surface of the silicon substrate 51. An n-type diffusion layer 53 serving as a CCD channel is formed at a portion where the buried charge transfer section is formed by the p-type diffusion layer 52. An MIS transistor is formed at a substrate edge on the surface of the silicon substrate 51. The MIS transistor and the buried charge transfer section are electrically insulated by a thick oxide film isolation region 54 called LOCOS.

In the MIS transistor region, an n-type diffusion layer 55 serving as a source / drain is formed. A silicon oxide film 56 is formed on the surface of the silicon substrate 51 of the embedded charge transfer section. This silicon oxide film 5
6 is formed to a thickness of about 80 nm by thermally oxidizing the silicon substrate 51 to be a gate insulating film.

On the silicon oxide film 56, a silicon nitride film 57 having a thickness of 40 nm formed by a low pressure CVD method. Further, a silicon oxide film 70 is formed on silicon nitride film 57. The thickness of the silicon oxide film 70 is about 5 nm. The silicon oxide film 70 is formed simultaneously when a silicon oxide film that is a gate insulating film of the MIS transistor is formed in a manufacturing process described later.

When forming the gate insulating film of the MIS transistor, the region of the charge transfer element is
6 and a silicon nitride film 57 are laminated.
When the silicon oxide film 71 as the gate insulating film is formed, the surface of the silicon nitride film 57 is oxidized by 5 nm. This thickness changes according to the change in the thickness of the gate insulating film of the MIS transistor. However, the oxide film thickness does not exceed several tens of nm.

Further, by forming such an ONO film on the gate insulating film of the charge transfer element, the reliability of the withstand voltage is improved. Further, since the gate electrode is formed of a laminated film of two or more layers, the thickness of the insulating film is constant under any electrode. Therefore, the potential under the electrode does not change. Normally, the gate insulating film below the gate electrode is oxidized in a subsequent step, and abnormal oxidation at the electrode end called bird's beak occurs. However, bird's beak is not caused by subsequent oxidation when used as the gate insulating film a multilayer film as in the example of this, it is possible to form a uniform channel.

The transfer electrode 58 is formed on the silicon oxide film 70.
Are formed. This transfer electrode 58 is electrically separated from an adjacent transfer electrode 60 via a silicon oxide film 59. The transfer electrodes 58 and 60 are formed of a polycrystalline silicon film doped with phosphorus. The thickness of the polycrystalline silicon is about 0.5 μm. On the other hand, a normal MIS transistor is formed in the MIS transistor region.
That is, on the surface of the n-type diffusion layer 52 between the source and the drain, a silicon oxide film 71 serving as a gate insulating film has a thickness of 5
It is formed at 0 nm. Further, the silicon oxide film 71
A gate electrode 72 is formed thereon. Gate electrode 7
2 is formed of a polycrystalline silicon film doped with phosphorus. The thickness of the polycrystalline silicon is about 0.5 μm.

Further, another MIS transistor having a common source or drain of the MIS transistor is also formed. This MIS transistor has p
On the surface of the mold diffusion layer 52, a silicon oxide film 73 serving as a gate insulating film is formed with a thickness of 100 nm. Further, a gate electrode 74 is formed on the silicon oxide film 73. Gate electrode 74 is formed of a polycrystalline silicon film doped with phosphorus. The thickness of the polycrystalline silicon is about 0.4 μm.

The difference between the two MIS transistors described here is that the thicknesses of the silicon oxide films 71 and 73 serving as the gate insulating films of the two are different. The gate insulating film of the embedded charge transfer section is formed of a laminated film, and the charge transfer element is formed such that the gate insulating films of the MIS transistors of the peripheral circuit section have at least two different thicknesses. On the point.

When a thin film having a constant thickness is formed on the gate insulating film of the MIS transistor in the peripheral circuit portion (particularly, the amplifier portion, etc.) of the charge transfer element, the MIS transistor determined according to the purpose of use of the peripheral circuit portion is formed. If it must, the desired properties cannot be obtained. For example, in an MIS transistor using a thin gate insulating film, on-resistance at the time of switching of the transistor is reduced, noise can be reduced, and element characteristics can be improved. However, it is to be used only as a resistor as a load transistor MIS transistor, the transconductance g _m is increased. Therefore, in order to provide a predetermined resistance value, the size of the transistor that must be formed when the thickness of the gate insulating film is small must be increased. In order to form MIS transistors having different purposes in the peripheral circuit portion as described above, it is necessary to use a gate insulating film having a desired thickness suitable for each MIS transistor.

Further, in such a peripheral circuit section, the additional capacitance also increases. For this reason, the high frequency characteristics deteriorate. Example of this, MIS transistor having a gate insulating film thickness optimal for some applications can be formed. Therefore, it is possible to easily reduce the size of the device and optimize the device characteristics.

In the charge transfer device having the above structure, even if a buried charge transfer portion is formed by using a stacked film of a silicon oxide film and a silicon nitride film as a gate insulating film, the transfer characteristics are hardly affected. On the other hand, when such a laminated film is used for the gate insulating film of the MIS transistor constituting the peripheral circuit portion, the interface state and the interface state generated in the laminated film are reduced as compared with a case where a single-layered gate insulating film of a silicon oxide film is used. Transistor characteristics deteriorate due to trap levels existing in the insulating film. In the charge transfer device of this example has never deterioration in characteristics of the MIS transistor of such a charge transfer device occurs.

Next, FIG. 8 is a plan view of an FIT (frame transfer) type solid-state imaging device. The FIT-type charge transfer element enables high-speed transfer as compared with the above-described charge transfer element. For this purpose, a storage unit for holding signal charges is provided. The signal charge from the photoelectric conversion unit is
Usually, it is taken out using a sense amplifier. In this case, the transfer time required for the signal charge to be sent to the sense amplifier can be said to be the transfer speed capability of the charge transfer element. On the other hand, since the FIT type charge transfer element has a storage portion, signals can be taken out to the outside directly from the storage portion. Therefore, high-speed operation is possible as compared with the conventional charge transfer element.

Reference numeral 80 denotes a pixel unit that performs photoelectric conversion, 81 denotes a storage unit that temporarily holds the photoelectrically converted charges, and 82 denotes a horizontal charge transfer unit that sequentially outputs the stored charges. Storage unit 8
1, the silicon nitride film is not removed by self-alignment like the transistor in the peripheral circuit portion. For this reason, the entire surface is covered with a silicon nitride film. In this case, the interface order increases due to the stress of the silicon nitride film. Further, since the silicon nitride film has a low hydrogen transmittance, the effect of improving the interface by hydrogen treatment used in the process of manufacturing the charge transfer element is reduced.

FIG. 9 is a process sectional view for explaining the first embodiment of the method of manufacturing the solid-state imaging device according to the present invention (corresponding to claim 1 ). First, as shown in FIG.
Boron is ion-implanted on the entire surface of the n-type silicon substrate 51. Thereafter, heat treatment is performed to form the p-type diffusion layer 52.
The ion implantation conditions at this time were as follows: an acceleration voltage of 100 keV,
The injection is performed at a dose of 5 × 10 ¹¹ / cm ² . The heat treatment was performed at a treatment temperature of 1200 degrees for 10 hours. At this time, the diffusion depth of the p-type diffusion layer 52 was about 5 μm.

Next, the surface of the silicon substrate 51 is thermally oxidized to form a silicon oxide film 83 with a thickness of 50 nm.
Thereafter, a silicon nitride film 84 is formed on the silicon oxide film 83 by a low pressure CVD method. The thickness of the silicon nitride film 84 is 120 nm. Thereafter, a resist pattern is formed using normal photolithography to cover a region other than the portion to be the separation region 54. The resist pattern as a mask, the silicon nitride film 8 4 is removed by etching.

Further, the silicon oxide film 83 is removed,
The surface of the silicon substrate 51 is exposed. After this,
The resist pattern is removed. The silicon substrate 51 from which the silicon nitride film 84 and the silicon oxide film 83 have been removed is thermally oxidized to grow the isolation region 54. The isolation region 54 is called LOCOS, and an oxide film having a thickness of about 500 nm is formed.

Next, as shown in FIG. 9B, the silicon nitride film 84 formed on the entire surface of the semiconductor substrate 51 is removed by etching. Thereafter, a resist pattern is formed in a region where the MIS transistor is to be formed by using normal photolithography (not shown). Thereafter, the semiconductor substrate 5
1. Phosphorus ion implantation is performed on the entire surface. The ion implantation conditions are
The acceleration voltage is 100 keV and the injection amount is 3 × 10 ¹² / cm ² . After that, the resist pattern is removed.

Further, heat treatment is performed to form an n-type diffusion layer 53 serving as a transfer channel. At this time, the n-type diffusion layer 5
The diffusion depth of No. 3 is 0.5 μm. Further, the silicon oxide film 83 used as the surface protection film is removed by etching. By this etching, the oxide film of the isolation region 54 is also etched by a thickness corresponding to the thickness of the silicon oxide film 83.

Next, as shown in FIG. 9C, the semiconductor substrate 51 is thermally oxidized to form a silicon oxide film 56 with a thickness of 80 nm. Further, the thickness is reduced to 40 nm by low pressure CVD.
Of silicon nitride film 57 is grown on silicon oxide film 56. At this time, the thickness of the silicon oxide film 56 is 10 nm to
Within the range of 200 nm, the thickness of the silicon nitride film 57 is
Within the range of 10 nm to 100 nm, it is possible to find the optimum film thickness for the characteristics of the charge transfer device and the circuit driving conditions.

Thereafter, a resist pattern having an opening in a peripheral circuit region for forming a MIS transistor is formed by using ordinary photolithography. Using this resist pattern as a mask, silicon nitride film 57 is removed by a plasma etching method. Thus, the silicon nitride film in the region where the MIS transistor is to be formed is removed.

Further, the silicon oxide film 56 exposed in this region is removed by wet etching with a mixed solution of hydrofluoric acid and ammonium fluoride. It goes without saying that the silicon oxide film 56 may be etched by a plasma etching method. Here, the silicon substrate 51 is exposed in a region where the MIS transistor is formed. However, the amount of etching of the silicon oxide film 56 is performed until the semiconductor substrate 51 is exposed on the surface, and even if the silicon oxide film 56 is slightly left, there is no adverse effect on the subsequent steps.

Further, before the silicon oxide film 56 is wet-etched, a process may be performed in which the silicon oxide film 56 is exposed to oxygen plasma for the purpose of removing dirt on the surface thereof to facilitate wet etching. Next,
The resist pattern is removed. Thereafter, a silicon oxide film 68 is formed on the peripheral circuit portion on the semiconductor substrate 51 exposed by the thermal oxidation.

At this time, the embedded charge transfer device section includes:
A two-layer film of a silicon oxide film 56 and a silicon nitride film 57 is formed. Since the upper silicon nitride film 57 has a low oxidation rate, there is no influence from the increase in the film thickness. Therefore, the thickness of the silicon oxide film 68 serving as the gate insulating film of the MIS transistor can be freely set.

At this time, a silicon oxide film 70 having a thickness of about 5 nm is simultaneously grown on the silicon nitride film 57 in the charge transfer section. In this embodiment, a silicon oxide film 68 having a thickness of about 50 nm is formed so as to optimize the dielectric breakdown voltage characteristics, the frequency characteristics, and the noise characteristics.

Thereafter, as shown in FIG. 9D, a first polycrystalline silicon film is deposited and doped with phosphorus to reduce the resistance, and the first transfer electrode 58 of the charge transfer element and the periphery thereof are etched by photoetching. The gate electrode 69 of the circuit portion is formed at the same time. At this time, the etching condition of the polycrystalline silicon film is set to a large etching rate ratio with respect to the underlying silicon nitride film 57 so that the silicon nitride film 57 is hardly etched.

Next, as shown in FIG. 9E, the polycrystalline silicon film is oxidized to form a silicon oxide film 59.
As a result, the first transfer electrode 58 becomes the second transfer electrode 60
Electrically insulated from Thereafter, a second polycrystalline silicon film is deposited and doped with phosphorus to reduce the resistance, and the second transfer electrode 60 of the charge transfer element is formed by photoetching.

Thereafter, the gate insulating film below the second transfer electrode 60 of the second polycrystalline silicon film is changed to the first transfer electrode 58.
It has the same thickness as the lower gate insulating film. That is, the gate insulating films under both electrodes have the sum of the thicknesses of the silicon oxide film 56 and the silicon nitride film 57. Therefore, when the charge transfer element is operated, a uniform CCD channel can be obtained.

As described above, according to the method of manufacturing the solid-state imaging device of this embodiment, the stacked film of the silicon oxide film 56 and the silicon nitride film 57 is removed to form the silicon oxide film 68 of the gate insulating film in the peripheral circuit portion. I do. For this reason, the process is simpler than the conventional one. Further, when the gate insulating film 68 of the peripheral circuit portion is formed, the silicon nitride film 57 is formed on the charge transfer portion. When the silicon oxide film 68 of the gate insulating film is oxidized in this state, the silicon nitride film 57 does not change, that is, only the silicon oxide film 70 of about 5 nm is formed, and at the same time, the gate insulating film of the peripheral circuit portion is formed. Can be.

Therefore, the thickness of the insulating film immediately below the first transfer electrode 58 and the thickness of the insulating film immediately below the second transfer electrode 60 become uniform. The second transfer electrode 60 is also formed by the same photo etching, but the first transfer electrode 58 and the second transfer electrode 6 are formed.
When the second transfer electrode 60 is etched in a self-aligned manner, the silicon nitride film 57 in a region other than the region below the zero is etched away at the same time.

At this time, the polycrystalline silicon film is etched under such a condition that the etching rate ratio between the polycrystalline silicon film and the underlying silicon nitride film 57 is small. Transfer electrode 58,
By removing the silicon nitride film 57 other than the lower part of 60, stress applied to the entire device is reduced. When this charge transfer element is used in a solid-state imaging device , the attenuation of light incident on the photodiode can be prevented by removing the silicon nitride film.

Thereafter, formation of an insulating film and aluminum wiring are performed to form a charge transfer element. Through the above steps, a gate insulating film can be formed with a laminated film having excellent stability in the CCD channel portion, and a transistor can be formed with the gate insulating film of the silicon oxide film 68 having a small interface state in the peripheral circuit portion.

Surface channel MOS transistor in peripheral circuit section
Silicon with few interface states and trap levels in the film
Since an oxide film is used, noise characteristics due to interface state density
And the threshold voltage V due to the trap density in the film_thShi
Shift and transconductance g _mO with reliability such as deterioration of
Better than a charge transfer element formed only with NO film
An element is obtained.

FIG. 10 is a process sectional view for explaining a second embodiment of the method of manufacturing the solid-state imaging device according to the present invention (corresponding to claim 2 ). The second embodiment describes a manufacturing method in the case where two or more MIS transistors are formed in the manufacturing method shown in the first embodiment. First, as shown in FIG. 10A, boron is ion-implanted on the entire surface of the n-type silicon substrate 51. Thereafter, heat treatment is performed to form the p-type diffusion layer 52. At this time, the diffusion depth of the p-type diffusion layer 52 is about 5 μm.

Next, the surface of the silicon substrate 51 is thermally oxidized to form a silicon oxide film 83 with a thickness of 50 nm.
Thereafter, a silicon nitride film 84 is formed on the silicon oxide film 83 by a low pressure CVD method. The thickness of the silicon nitride film 84 is 120 nm. Thereafter, a resist pattern is formed using normal photolithography to cover a region other than the portion to be the separation region 54. Using this resist pattern as a mask, the silicon nitride film 84 is removed by etching.

Further, the silicon oxide film 83 is removed,
The surface of the silicon substrate 51 is exposed. After this,
The resist pattern is removed. The silicon substrate 51 from which the silicon nitride film 84 and the silicon oxide film 83 have been removed is thermally oxidized to grow the isolation region 54. The isolation region 54 is called LOCOS, and an oxide film having a thickness of about 500 nm is formed.

Next, as shown in FIG. 10B, the silicon nitride film 84 formed on the entire surface of the semiconductor substrate 51 is removed by etching. Thereafter, a resist pattern is formed in a region where the MIS transistor is to be formed by using normal photolithography (not shown). After that, ion implantation is performed on the entire surface of the semiconductor substrate 51. After that, the resist pattern is removed.

Further, heat treatment is performed to form an n-type diffusion layer 53 serving as a transfer channel. At this time, the n-type diffusion layer 5
The diffusion depth of No. 3 is 0.5 μm. Further, the silicon oxide film 83 used as the surface protection film is removed by etching. Next, as shown in FIG.
1 is thermally oxidized to form a silicon oxide film 56 with a thickness of 80 nm.

Further, a silicon nitride film 57 having a thickness of 40 nm is grown on the silicon oxide film 56 by a low pressure CVD method.
Thereafter, a resist pattern having an opening in a region where the first MIS transistor is to be formed in the peripheral circuit portion is formed by using normal photolithography (not shown). Using this resist pattern as a mask, silicon nitride film 57 is removed by a plasma etching method. Thus, the silicon nitride film 57 in the region where the first MIS transistor is to be formed is removed.

Further, the silicon oxide film 56 exposed in this region is removed by wet etching with a mixed solution of hydrofluoric acid and ammonium fluoride. It goes without saying that the silicon oxide film 56 may be etched by a plasma etching method. Here, the silicon substrate 51 is exposed in a region where the MIS transistor is formed. Next, the resist pattern is removed.

Thereafter, as shown in FIG. 10D, a silicon oxide film 71 is formed on the semiconductor substrate 51 exposed by thermal oxidation. At this time, the embedded charge transfer section includes:
A two-layer film of a silicon oxide film 56 and a silicon nitride film 57 is formed. Since the upper silicon nitride film 57 has a low oxidation rate, there is no influence from the increase in the film thickness. Therefore, the thickness of the silicon oxide film 71 serving as the gate insulating film of the MIS transistor can be freely set. Here, the film thickness was set to 50 nm.

At this time, a silicon oxide film 70 having a thickness of about 5 nm is simultaneously grown on the silicon nitride film 57 of the charge transfer section. Thereafter, a first polycrystalline silicon film is deposited and doped with phosphorus to have a low resistance, and the first transfer electrode 58 of the charge transfer element and the gate electrode 72 of the peripheral circuit portion are simultaneously formed by photoetching. At this time, the silicon oxide film 71 serving as the gate oxide film of the first MIS transistor is etched.
Quenching performed simultaneously with the etching of the gate electrode 72.

Thereafter, a resist pattern having an opening in a region for forming the second MIS transistor in the peripheral circuit portion is formed by using ordinary photolithography (not shown). Then, as shown in FIG. 10E, using the resist pattern as a mask, the silicon nitride film 57 in the peripheral circuit portion is removed by a plasma etching method. Thus the second
The silicon nitride film 57 in the region where the MIS transistor is formed is removed.

Further, the silicon oxide film 56 exposed in this region is removed by wet etching with a mixed solution of hydrofluoric acid and ammonium fluoride. Here, the silicon substrate 51 is exposed in a region where the MIS transistor is formed. Next, the resist pattern is removed. Thereafter, a silicon oxide film 73 is formed on the semiconductor substrate 51 exposed by thermal oxidation. By this oxidation step, the polycrystalline silicon film of the transfer electrode 58 is also oxidized, and a silicon oxide film 59 is formed. Thereby, the first transfer electrode is electrically insulated from the second transfer electrode.

At this time, the region of the embedded charge transfer portion where the first transfer electrode 58 is not formed is the silicon oxide film 7
0 is formed. With the formation of the silicon oxide film 73 as the gate insulating film of the second MIS transistor, the silicon oxide film 70 further grows. However, here too, the lower silicon nitride film 57 has a low oxidation rate,
There is no effect of increasing the film thickness. For this reason, MI
Silicon oxide film 7 serving as a gate insulating film of S transistor
The film thickness of No. 3 can be freely set. Here, the film thickness is 80 nm.
Set to.

Thereafter, a second polycrystalline silicon film is deposited and doped with phosphorus to reduce the resistance, and the second transfer electrode 60 of the charge transfer element and the gate electrode 74 of the peripheral circuit portion are simultaneously formed by photoetching. I do. At this time, the silicon oxide film 73 serving as the gate oxide film of the second MIS transistor is etched.
Simultaneously with the etching of the gate electrode 74 of the etching.
Next, as shown in FIG. 10F, the second gate electrode 74 is formed by photoetching. At this time, the first
The silicon nitride film in a region other than the region below the transfer electrode 58 and the second transfer electrode 60 is etched away by self-alignment using these as a mask.

As described above, the semiconductor device has two types of film thicknesses, the first peripheral circuit portion of 50 nm and the second peripheral circuit portion of 80 nm, and has a small interface level and a small trap level in the film. To form a surface channel transistor, a peripheral circuit portion having an optimal gate insulating film is formed. Although the silicon oxide films of 50 nm and 80 nm are formed in this embodiment, the oxide film thickness can be arbitrarily changed as long as the dielectric strength is allowed.

Thereafter, after an insulating film is formed, aluminum wiring is performed to complete a charge transfer element. In the case of a device having three or more gates, a silicon oxide film can be formed by removing the silicon nitride film in the peripheral circuit portion in the same manner. As described above, since the silicon nitride film in the peripheral circuit is removed, the MIS transistor can be formed in a portion where the influence of the interface state is small. Therefore, the threshold voltage _Vth does not deteriorate due to the stress.

Further, since the gate insulating film of the peripheral circuit portion is simultaneously formed on the charge transfer portion having the silicon nitride film as the upper surface, the process is simple, and the thickness of the gate insulating film can be changed according to the purpose. Further, since the first transfer electrode of the charge transfer section and the gate electrode of the peripheral circuit section can be formed in a self-aligned manner, the process is easy.

Further, when the gate insulating film of the peripheral circuit section is formed, a silicon nitride film is formed on the charge transfer section. If the gate insulating film is oxidized in this state, the silicon nitride film does not change, that is, only a silicon oxide film of about 5 nm is formed, and the gate insulating film of the peripheral circuit portion can be formed at the same time.

[0130]

【The invention's effect】

[0131]

[0132]

[0133]

[0134]

According to the present invention, the thickness of the gate insulating film of the MIS transistor can be arbitrarily selected, so that the on-resistance at the time of switching is reduced and the noise is reduced. A transistor used only can be used together. Therefore, may become the transconductance g _m is large, it is not necessary to increase the size of the transistor. Further, it is possible to prevent the additional capacity from being increased and the high frequency characteristics from being deteriorated.

In addition, since the silicon nitride film in the peripheral circuit portion is removed, the MIS transistor can be formed in a portion where the influence of the interface state is small. Therefore, the threshold voltage _Vth does not deteriorate due to the stress. Further , according to the present invention , since the gate insulating film of the peripheral circuit portion is simultaneously formed on the charge transfer portion having the silicon nitride film as the upper surface, the process is simple, and the thickness of the gate insulating film is changed according to the purpose. it can.

Further, since the first transfer electrode of the charge transfer section and the gate electrode of the peripheral circuit section can be formed in a self-aligned manner, the process is easy. When a different transistor is formed in the peripheral circuit section, the gate insulating film of the peripheral circuit, the first transfer electrode of the charge transfer section, and the gate electrode of the peripheral circuit section are formed in a self-aligned manner in the charge transfer section. ,
Further, a gate insulating film of a different transistor can be formed simultaneously with an insulating film for electrically isolating the first transfer electrode. At this time, the gate electrode and the second transfer electrode of a different transistor can be formed at the same time. Therefore, the process is easy.

Further , according to the present invention , a stacked film of a silicon oxide film and a silicon nitride film is removed to form a gate insulating film of a peripheral circuit portion. For this reason, the process is simpler than the conventional one. Further, when the gate insulating film of the peripheral circuit portion is formed, a silicon nitride film is formed above the charge transfer portion. If the gate insulating film is oxidized in this state, the silicon nitride film does not change, that is, 5n
Only by forming a silicon oxide film of about m, a gate insulating film of a peripheral circuit portion can be formed at the same time.

For this reason, the thickness of the insulating film immediately below the first transfer electrode and the thickness of the insulating film immediately below the second transfer electrode become substantially uniform.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a first example of a charge transfer element .

FIG. 2 is an element cross-sectional view when the first example of the charge transfer element is applied to a solid-state imaging device.

3 is a characteristic diagram for explaining an amplifier noise characteristics and frequency characteristics of the electric charge transferring elements.

FIG. 4 is a cross-sectional view of a second example of the charge transfer element .

FIG. 5 is a cross-sectional view of a third example of the charge transfer element .

6 is a plan view of the peripheral portion of the peripheral circuit portion of the electric charge transferring elements.

FIG. 7 is a sectional view of a fourth example of the charge transfer element .

8 is a plan view of the electric charge transferring device is applied to a FIT type CCD solid-state imaging device.

FIG. 9 is a cross-sectional view illustrating a method of manufacturing the solid-state imaging device according to the first embodiment of the present invention in the order of steps;

FIG. 10 is a cross-sectional view illustrating a method of manufacturing a solid-state imaging device according to a second embodiment of the present invention in the order of steps;

FIG. 11 is a cross-sectional view of a conventional charge transfer element.

FIG. 12 is a cross-sectional view illustrating a method of manufacturing a conventional charge transfer element in the order of steps.

[Explanation of symbols]

 Reference Signs List 51 silicon substrate 52 p-type diffusion layer 53 n-type diffusion layer 54 isolation region 55 n-type diffusion layer 56 silicon oxide film 57 silicon nitride film 58 transfer electrode 59 silicon oxide film 60 transfer electrode 68 silicon oxide film 69 gate electrode

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuji Matsuda 1006 Kazuma Kadoma, Kadoma City, Osaka Inside Matsushita Electronics Corporation (56) References JP-A-60-35568 (JP, A) JP-A-2-2 260542 (JP, A) JP-A-2-220450 (JP, A) JP-A-1-185970 (JP, A) JP-A-62-243365 (JP, A) JP-A-63-102261 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/148 H01L 21/339 H01L 29/762

Claims (2)

(57) [Claims] 1. A forming a first silicon oxide film on the semiconductor substrate main surface, forming a silicon nitride film on the first silicon oxide film, a first region to be a peripheral circuit portion Removing the silicon nitride film; and removing the first silicon oxide film in the first region; and exposing the silicon nitride film entirely on the upper surface of the second region serving as a charge transfer portion. Forming a second silicon oxide film on the semiconductor substrate while forming a first transfer electrode in the second region,
Forming a gate electrode in the first region via the second silicon oxide film; forming a third silicon oxide film on the semiconductor substrate; Forming a second transfer electrode in the second region by using the method. 2. A step of forming a first silicon oxide film on a main surface of a semiconductor substrate, a step of forming a silicon nitride film on the first silicon oxide film, and a first step of forming a peripheral circuit portion. removing the third of said silicon nitride film in a region in the region of, and then removing the first silicon oxide film of the third region of the first region, then a charge transfer section A second region is formed on the semiconductor substrate in a state where the silicon nitride film is entirely exposed on the upper surface of the second region.
Forming a first transfer electrode in the second region, and simultaneously forming a first transfer electrode in a third region in the first region via the second silicon oxide film. Forming a second gate electrode, and then forming the silicon nitride in a fourth region in the first region.
Removing the oxide film, then forming a third silicon oxide film on the semiconductor substrate, and forming a second transfer electrode in the second region via the third silicon oxide film Simultaneously forming a second gate electrode in a fourth region in the first region via the third silicon oxide film.