JPH04212451A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a trench-dug capacitor structure of a substrate electrode type capable of decreasing electric field applied on a capacitor insulating film, by completely isolating a common capacitor electrode from an MOS transistor substrate. CONSTITUTION:A capacitor electrode constituted of a first polycrystalline silicon film 8 and a second polycrystalline silicon film 10 is limited, buried, and formed in a trench 6. An N-type layer 11 which is linked with the diffusion layer of an MOS transistor in the later process can be formed in a self-alignment manner. Thus an N<+> type Si substrate 1 is applied to the common electrode of all capacitors; capacitor electrodes 8, 10 buried in each trench are turned into independent storage nodes for each capacitor; an MOS transistor part turns to the common electrode. Thereby a substrate electrode type trench-dug memory cell structure constituted of a substrate 3 dielectrically isolated from the N<+> type Si substrate is obtained.

Description

[Detailed description of the invention]

0001 [Purpose of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (DRAM) in which a memory cell is composed of one MOS transistor and one capacitor, and a method for manufacturing the same.

0003

2. Description of the Related Art In recent years, the degree of integration of DRAMs has been remarkable. Various types of memory cell structures have been proposed for further increasing the integration density of DRAMs, in which a trench is dug in a semiconductor substrate and the inner wall of the trench is used to form a capacitor. Among these types of memory cells, those in which the substrate is used as a common electrode and an independent capacitor electrode is embedded for each capacitor in the trench have excellent soft error resistance because the storage node is separated from the substrate. (For example, IEDM85; p. 710-713).

As a first conventional example, FIG. 22 is a plan view showing such a memory cell structure and a cross-sectional view taken along the line A-A'.
Two adjacent bits are shown. P+ type Si substrate 2
A wafer 1 on which a P-type layer 22 is epitaxially grown is used, and a memory cell consisting of a capacitor and a MOS transistor is formed in each memory cell region separated by a field insulating film 31. That is, a trench 23 is formed in each memory cell region, and a capacitor electrode 25 is embedded in the trench 23 with a capacitor insulating film 24 interposed therebetween. A gate electrode 27 made of a third layer polycrystalline silicon film is formed in a region adjacent to the capacitor region via a gate insulating film 26, and using this as a mask, impurities are doped to form source and drain diffusion layers 281 and 282. A MOS transistor is configured. The gate electrodes 27 are successively arranged in a plurality of memory cells in one direction of the substrate and serve as word lines. Here, capacitor electrode 2
5 consists of a first layer polycrystalline silicon film electrode 251 buried halfway into the groove 23 and a second layer polycrystalline silicon film electrode 252 superimposed thereon. The second layer polycrystalline silicon film electrode 252 is connected to the substrate through a hole formed on the upper surface of the substrate. Then, the impurity of the second layer polycrystalline silicon film electrode 252 is diffused into the substrate, and this diffusion layer becomes integrated with the diffusion layer 281 formed using the gate electrode 27 as a mask. In this way, the capacitor electrode 25 is electrically connected to the diffusion layer of the MOS transistor on the upper surface of the substrate, and this becomes a storage node. The P+ type Si substrate 21 serves as a common electrode for all capacitors in place of the conventional cell plate. The substrate on which the elements are formed is covered with a CVD insulating film 29, a contact hole is made in this, and a bit line 30 electrically connected to one diffusion layer 282 of the MOS transistor is provided.

However, with this substrate electrode type memory cell structure, it is not possible to apply a positive voltage of 1/2 Vcc to the substrate (if it is applied, a forward bias will be applied to the P-N junction, causing an abnormal current to flow). ) Normally, 0V is applied. In this case, compared to the 1/2 Vcc method, twice the electric field is applied to the capacitor insulating film, and the capacitor insulating film is more likely to be destroyed, which is a major reliability problem.

On the other hand, as MOS type DRAMs become more highly integrated, the area of a capacitor for storing information is reduced, and this reduction results in a reduction in the amount of charge stored.

[0007] Therefore, problems arise in that the memory contents are read out incorrectly or the memory contents are destroyed by radiation such as alpha rays.

In order to solve this problem, a trench is dug in the area of the MOS capacitor to substantially increase the surface area without increasing the area occupied by the MOS capacitor, thereby increasing the capacitance of the MOS capacitor. A method of increasing the charge storage capacity has been proposed.

[0009] The second conventional example DRAM 40 will be described below.
0 is shown in FIG.

The DEAM 400 includes a capacitor section 402 formed in a groove dug in a semiconductor substrate 401, and a MOS transistor section 4 formed between the capacitor sections 402.
03.

The capacitor section 402 includes a diffusion layer 404 that diffuses around the groove, an insulating SiO2 film 405 covering the surface of the substrate 401, and an insulating layer 405 formed on the SiO2 film 405 and the surface of the diffusion layer 404. a capacitor insulating film 406, a plate electrode 407 that fills the groove and holds charges between the capacitor insulating film 406 and the diffusion layer 404, and a capacitor part 402 that covers the surface of the plate electrode 407. It is composed of an oxide film 408 for protection and insulation.

The MOS transistor section 403 is provided on the substrate 401 through an insulating gate insulating film 409 that covers the surface of the substrate 401, and between the gate electrode 401 constituting a word line and the gate electrode 410 and the gate insulating film 409. An n-type layer 411 is provided on the substrate 401 with a gate insulating film 409 interposed between the electrode 410 and the capacitor section 402 .

Furthermore, the DRAM 400 has a gate electrode 4
10 and the oxide film 408, a CVD insulating film 412 is formed, and the gate electrode 4 is wired above the CVD insulating film 412.
The bit line 41 electrically contacts the n-type layer 411 between the
3 and a protective film 414 covering the surface of the bit line 413.

In the above-described conventional DRAM 400 configuration, when a charge is applied to the gate electrode 410 constituting the word line, the voltage between the gate electrode 410 and the n-type layer 411 and between the gate electrode 410 and the diffusion layer 404 increases. conducts. Next, when a signal is sent to the DRAM 400 via the bit line 413, the charge included in the signal is accumulated in the capacitor section 402 via the n-type layer 411 and the diffusion layer 404. In other words, the signal sent from the outside is written into the capacitor section 402. Moreover, conversely, the gate electrode 41
When a charge is applied to 0, the charge accumulated in the capacitor section 402 is read out to the outside via the bit line 413 as a signal.

Therefore, in the conventional RAM 400, signals can be freely written and read.

[0016]

[Problems to be Solved by the Invention] As described above, in the memory cell of the substrate electrode type grooved capacitor structure proposed in the first conventional example, the electric field applied to the capacitor insulating film increases, resulting in a serious problem in terms of reliability. Occur.

Furthermore, the second conventional example has the following problems.

First, since the shape of the bottom of the groove of the capacitor portion 402 becomes non-uniform, the insulation performance is impaired in a portion of the bottom of the groove, resulting in deterioration of the capacitor breakdown voltage.

Second, since each member constituting the capacitor section 402 has a different coefficient of thermal expansion, thermal stress concentrates at the bottom of the groove, causing crystal defects, and increasing leakage current from the capacitor section 402 to the substrate 401. It turns out.

Third, the grooves suffer from damage such as lattice defects due to etching during their formation. Since it is difficult to remove this etching damage, the quality of the oxide film formed at the bottom of the trench deteriorates, leading to an increase in leakage current as in the second problem.

SUMMARY OF THE INVENTION Accordingly, a first object of the present invention is to provide a semiconductor memory device having a trenched capacitor structure of substrate electrode type, which can reduce the electric field applied to the capacitor insulating film and improve reliability, and its manufacture. The purpose is to provide a method.

[0022] A second object of the present invention is to provide a semiconductor memory device and a method for manufacturing the same, which can suppress the occurrence of leakage current to a minimum without causing deterioration of the capacitor breakdown voltage inside the trench. be.

[0023] [Structure of the invention]

[0024]

Means for Solving the Problems To achieve the above object, a semiconductor memory device according to claim 1 has a substrate electrode type grooved capacitor structure, and a region where a MOS transistor is formed is completely separated from the substrate. The common electrode of the capacitor using a substrate is characterized in that it has a structure to which an arbitrary voltage such as +1.5V can be applied.

Further, the manufacturing method according to claim 2, in realizing such a DRAM cell structure, uses a highly doped substrate and a normal doped substrate (for example, 5 Ω cm) having a thickness of about 1000 angstroms. After preparing a multilayer substrate separated by, for example, a silicon oxide film and forming an element isolation region between memory cells, a trench is formed, and a first conductor is inserted into the trench through a capacitor insulating film. A part of the capacitor electrode is embedded with a film, and then the capacitor insulating film on the side surface of the upper substrate is removed by etching to expose the side surface of the upper substrate, and in this state, a second conductive film is further embedded. Here, impurities from the second conductor film are diffused to the side surface of the upper substrate. This diffusion layer is integrated with one of the source and drain diffusion layers of the MOS transistor that will be formed later, and as a result, the capacitor electrode consisting of the first and second conductor films is connected to the side surface of the substrate 2 above the groove of the MOS transistor. It will be electrically connected to one of the diffusion layers.

The method for manufacturing a semiconductor memory device according to claim 3 further includes a step of forming an insulating film layer at a certain depth within a semiconductor substrate, and a step of forming an insulating film layer at a certain depth from the surface of the substrate. and a step of forming a groove having a flat interface with the substrate insulating layer, a step of covering the inner wall of the groove with an insulating film, leaving a part of the inner wall, and a step of connecting the substrate with electricity through the insulating film. forming a storage electrode on an inner wall on the insulating film that is electrically insulated and in electrical contact with the substrate only through the inner wall that is partially left exposed; and an insulator that covers the surface of the storage electrode. a step of forming a capacitor insulating film;
forming a plate electrode for holding charge between the capacitor insulating film and the storage electrode on the surface of the capacitor insulating film; forming in the substrate adjacent to the groove so as to be in electrical contact with the storage electrode through an inner wall thereof.

Further, the semiconductor memory device according to claim 4 includes:
an insulating film layer formed at a certain depth within the semiconductor substrate;
a groove that reaches the insulating film layer at a certain depth from the surface of the substrate and has a flat interface with the insulating film layer; an insulating film that covers an inner wall of the groove with only a portion remaining; and the insulating film. a storage electrode that is electrically insulated from the substrate through the substrate and electrically contacts the substrate only through the partially exposed inner wall; and an insulating capacitor that covers the surface of the storage electrode. a plate electrode that holds charges between the film and the storage electrode via the capacitor insulating film; and an inner wall in which one of the source or drain diffusion layers is partially exposed in the substrate adjacent to the groove. and a MOS transistor electrically in contact with the storage electrode via a MOS transistor.

[0028]

[Operation] In the DRAM structure according to claim 1, since the common capacitor electrode is completely separated from the MOS transistor substrate, a positive voltage can be applied to the substrate common electrode even though it is a substrate common electrode type. As a result, the same 1/2 Vcc method as in conventional memory cells can be used. Therefore, the electric field applied to the capacitor insulating film is about half that of the case where only 0V can be applied, and the reliability of the capacitor insulating film can be improved. This also shows that a thin capacitor insulating film can be used, and the storage capacity (Cs) of the cell can be increased.

Furthermore, since the substrate common electrode method is used, large steps do not protrude on the substrate, making it easier to perform processing in the next process and stabilizing the manufacturing process. Further, since a mask process and an etching process for forming the substrate common electrode are not necessary, the process can be simplified.

[0030] Also serves as a substrate common electrode, and also serves as a MOS
Since the transistor section is completely insulated from the substrate, it is extremely resistant to soft errors caused by alpha rays.

Furthermore, since the MOS transistor is made of a thin film silicon layer that is completely insulated from the substrate, punch-through is less likely to occur and short channel effects can be suppressed.

Furthermore, in the method according to the second aspect of the present invention, since the capacitor electrode of each memory cell is completely buried in the trench, no special mask process is required, and the process can be simplified.

Furthermore, since the silicon substrate on which the MOS transistor is formed is thin, complete element isolation can be achieved by simply etching the thin film substrate and burying the insulating film, thereby simplifying the process.

In the method for manufacturing a semiconductor memory device according to claim 3, since the insulating film layer is formed at a certain depth within the semiconductor substrate, the depth of each groove is equal to the distance from the surface of the semiconductor substrate to the insulating film layer. become. Therefore, the storage capacitance of the capacitor region formed by the storage electrode, the capacitor insulating film, and the plate electrode can be easily set to a constant value.

Furthermore, since the bottom of the trench formed in the semiconductor substrate is formed along the insulating film layer, it has a flat structure at the interface with the insulating film layer. Therefore, even if the etching conditions change, the bottom of the groove will not have a sharp shape, and the capacitor withstand voltage will not deteriorate.

Furthermore, since the bottom of the groove has a flat structure,
Even if thermal stress occurs after groove formation, crystal defects can be prevented from occurring. Therefore, generation of leakage current can be suppressed.

Furthermore, since a relatively thick insulating film exists at the bottom of the trench, even if the insulating film suffers etching damage, the insulating performance of the insulating film is stable. Therefore, a stable and high quality insulating film can be formed on the inner wall surface of the trench.

Furthermore, since the MOS transistor and capacitor regions are separated from the substrate below the insulating film layer by the insulating film layer, α rays etc.
The influence of secondary electrons generated at a depth of about m can be prevented. Therefore, the occurrence of soft errors can be significantly reduced.

Since the semiconductor memory device according to the fourth aspect of the present invention is manufactured by the above-described manufacturing method, it is possible to suppress the occurrence of leakage current to a minimum without causing deterioration of the capacitor breakdown voltage.

[0040]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

As a first embodiment of the semiconductor memory device according to claim 1, FIGS. 1(a), 1(b), and 1(c) are plan views showing a DRAM having a substrate electrode type trench structure. A
-A' sectional view and BB' sectional view are shown.

In this DRAM, an insulating film layer 2 is provided on an N-type silicon substrate 1, and a P-type silicon layer 3 is formed on it.
A so-called S0I substrate is used, and the regions separated by a field insulating film 4 are each memory cell region. In each memory cell region, a groove 6 that cuts into the N-type Si substrate 1 to a predetermined depth is formed, and a capacitor electrode 8 is embedded in the groove 6 with a capacitor insulating film 7 interposed therebetween. A gate insulating film 1 is formed in the region adjacent to the trench of the capacitor region.
A gate electrode 14 serving as a word line is formed through 3,
Source and drain n-type diffusion layers 15 are formed in a self-aligned manner on this gate electrode 14 to constitute a MOS transistor. The capacitor electrode is made up of a first polycrystalline silicon film 8 buried halfway into the groove and a second polycrystalline silicon film 10 buried thereover. A portion of the capacitor insulating film 7 above the first polycrystalline silicon film 8 is removed to expose a side surface region of the substrate for forming a MOS transistor, from which impurities in the second polycrystalline silicon film 10 are removed. is diffused to form an n-type diffusion layer 11 that is integrated with the n-type diffusion layer 15. That is, the capacitor electrode 8 is electrically connected to the diffusion layers 15 and 11 of the MOS transistor at the upper side surface of the groove 6. 16 is CV
A contact hole 17 is formed in the D insulating film, and a bit line 18 connected to the diffusion layers 151 and 154 of the MOS transistors is provided. 19 is a protective film.

Next, the manufacturing process of this DRAM will be explained. Figures 2 (a), (b), (c) to Figure 9 (a), (b)
) and (c) show the manufacturing process of this DRAM.
), (b), and (c).

To explain the manufacturing process specifically, a SiO2 film layer 2 with a thickness of about 200 nm is formed on an N+ type Si substrate 1 with an impurity concentration of about 1×10 19 /cm 3 .
On top of that, the impurity concentration is 5 x 1015 with a thickness of about 100 nm.
A laminated structure substrate having a P-type Si layer 3 of about /cm3 is prepared (FIGS. 2(a), (b), and (c)). There are several methods for preparing such a laminated structure substrate, and here we will show a typical method among them.

First, as shown in FIG. 12, the insulating film layer 103 is formed by implanting oxygen ions at about 1.0×10 18 cm −2 at 170 KeV, for example, and annealing at about 1275° C. for about 16 hours. can be formed. At this time, a P-type layer 102 having a thickness of about 400 nm is epitaxially grown on an N-type substrate 101 in advance.

Next, the second method uses a wafer bonding method as shown in FIG. First, prepare two wafers (silicon substrates 201 and 203), one of which is N-type and has a high concentration (1 x 1019/cm3).
shall belong to. This N-type wafer is used as a common electrode on the substrate side of the capacitor. Alternatively, a highly doped N-type layer may be grown on a normally doped N-type substrate by epitaxial growth. This method can also easily form a thick film with uniform concentration. P
On the (100) type substrate 201, for example, an N- type epitaxial growth layer 202 is grown to a thickness of about 100 nm, for example. Next, P type (100) substrate 201 and N type (10
0) The surface of the substrate 203 has a thickness of 50 nm to 1 μm (here, for example, 20 nm) due to thermal oxidation in an H2 + O2 atmosphere.
0 nm) oxide films 2041 and 2042 are formed. Thereafter, the two silicon substrates 201 and 203 with the oxide film 2 formed on their surfaces in this way are stacked on a supporting silicon substrate 203 as shown in FIG. are stacked so that the n-type epitaxial layer 202 is on the inside. Like this 2
When overlapping the surfaces of two substrates, for example, a pulse voltage (±100
~±500 V), and the pressure is reduced to, for example, about 10 −1 Pa for bonding. At this time, the substrate is heated to a maximum of about 800°C. After this, further normal heat treatment (for example, 110
0° C. for 30 minutes in N2). After bonding the two silicon substrates 201 and 203 in this way,
As shown in FIG. 13(c), normal polishing is performed from the silicon substrate 201 side to reduce the thickness. The polishing may be performed in combination with ordinary physical polishing and chemical polishing using an etching method using a mixed solution of hydrofluoric acid, nitric acid, and acetic acid as an etching solution. Further, chemical polishing may be performed using the difference between P type and N type to provide an etching stop effect. The surface is then mirror-polished in the same way as a regular silicon substrate. A Si substrate having a laminated structure in which an oxide film 2 and an n- type impurity layer 3 are sequentially laminated on an N-type silicon substrate 1 as shown in FIG. 2 can be obtained.

Furthermore, a laser annealing method or the like may be used. FIG. 14 shows an example. First, an oxide film 302 is formed on the surface of a substrate 301, and the oxide film is removed from at least a part of the region for element isolation and the region for forming a trench, thereby exposing the substrate 301. Next, for example, polycrystalline silicon is deposited on the entire surface, and laser annealing is performed to form a single crystal (FIG. 14(b)).

Next, for example, a 100 nm thick S layer is formed in the field insulating film formation region of the multilayer substrate thus formed.
Etching away the i-substrate 3 by anisotropic etching,
The lower insulating film (here, an oxide film) 2 having a thickness of, for example, 400 nm is exposed. Further, an oxide film is deposited over the entire surface by, for example, the CVD method, and the oxide film 4 is buried only in the field region using a so-called etch-back method using a flattening film such as a resist (FIG. 3). (In the example of FIG. 14, the oxide film buried in this manner is indicated by 304, and the trench forming mask is indicated by 305.) After this, a PWell layer is formed in the NMOS transistor region, and an N-Well layer is formed in the PMOS transistor region. This step may also be performed in the subsequent channel ion implantation step of each HAN transistor. After this, a CVD oxide film 51 with a thickness of, for example, 50 nm and a silicon nitride film 52 with a thickness of, for example, 100 nm are formed.
A CVD oxide film 53 with a thickness of, for example, 200 nm is sequentially deposited, a resist pattern for forming a groove is formed, and the laminated film (51,
52, 53) and the buried oxide film 4 are etched. Next, using the remaining laminated films (51, 52, 53) as a mask, the substrate 1 is anisotropically etched to form grooves 61, 62 with a depth of about 5 μm. (Figure 4). At this time,
The trench 6 is formed so as to partially cover the oxide film 4 in the field region. In this way, the sides of the trench are covered with oxide film 4 except for the cell side.
It is possible to obtain a structure surrounded by

After that, a wet process containing an alkaline solution is performed to remove etching damage during trench formation, and then the exposed inner wall of the trench 6 is further oxidized in an oxygen atmosphere at 850° C. to reduce the film thickness, for example. A silicon oxide film 7 with a thickness of 10 nm is formed. Although a thermal oxide film is used here as the capacitor insulating film, a so-called NO film made of a nitride film and an oxide film may also be used.

Furthermore, a first polycrystalline silicon layer 8 doped with P is deposited on the entire surface by the CVD method, and then this polycrystalline silicon film 18 is subjected to, for example, chemical dry etching (CDE) containing CF4 and O2 gas. The grooves 6 are filled up to the middle by etching back using a method. That is, the surface of the first polycrystalline silicon film 8 left in the groove 6 is at a position lower than the surface of the substrate 3, and the surface of the first polycrystalline silicon film 8 is
(Figure 5)
). Thereafter, after forming a resist pattern in which a hole is formed so as to include the region where side contact is desired, on the side surface of the groove on the first polycrystalline silicon film 8,
Then, the capacitor insulating film 7, which is a part of the side surface of the substrate 3, is removed by etching to expose a part of the side surface of the substrate 3 (FIG. 6).
).

Thereafter, the resist is removed, a phosphorus-doped second polycrystalline silicon film 10 is deposited on the entire surface by CVD, and heat treatment is performed for 30 minutes in N2 at 900° C. to form the second polycrystalline silicon film. The impurity (phosphorus) in 10 is diffused to the side surface of the substrate 3 to form an n-type layer 11. Thereafter, the second polycrystalline silicon film 10 is etched back, for example, by the same CDE method as in the case of the first polycrystalline silicon film 8, and is buried in the trench 6 (FIG. 7). In this way, in this embodiment, the capacitor electrode consisting of the first polycrystalline silicon film 8 and the second polycrystalline silicon film 10 is buried and formed within the groove 6 as shown in the figure, and the capacitor electrode is formed to be buried within the groove 6, and also to be used as a MOS in the future. N-type layer 11 connected to the diffusion layer of the transistor
can be formed in a self-consistent manner.

After this, the CVD oxide film 53 is coated with NH4F.
The protective film 12 is removed by etching with a liquid or the like, and further oxidizes the exposed surface of the second polycrystalline silicon film 10 to a depth of about 50 nm, for example, to remove the silicon nitride film 52.
(Figure 8). After this, although it is omitted in the figure,
Using the protective film 12 as a mask, the silicon nitride film 52 is CF
Chemical treatment in an atmosphere using 4, N2, and O2 gases.
Perform dry etching (CDE) to remove.

After that, the oxide film 51 is removed to expose the surface of the substrate 3, a gate insulating film 13 made of a thermal oxide film of about 15 nm is formed, and a third polycrystalline silicon film is formed on the gate insulating film 13. A gate electrode 14 that becomes a line is formed, and using this gate electrode 14 as a mask, ions of, for example, phosphorus are implanted to form n-type diffusion layers 151 and 1 that become a source and a drain.
52... is also formed. For NMOS transistors, to adjust the threshold voltage of MOS transistors,
Before forming the gate insulating film 13, a so-called channel ion implantation process is performed to implant a P-type impurity such as boron, or for a PMOS transistor, an N-type impurity such as P. Furthermore, as described above, the diffusion layers 152 and 153 are connected to the diffusion layer 11 and together form the source or drain region of the MOS transistor. Although not shown in the drawings, for example, in the peripheral circuit section, a spacer is formed on the side wall of the gate electrode to form an LDD structure, and this is used as a mask to form an n+ type diffusion layer. Then, a CVD insulating film 16 is deposited on the entire surface, a contact hole 17 is opened in this, and a bit line 18 connected to the diffusion layer 15 is formed by a so-called polycide film using a molybdenum silicide film and a polycrystalline silicon film (Fig. 9). In this way, the N+ type Si substrate 1 is used as a common electrode for all capacitors, and the capacitor electrode 8 embedded in each groove is
, 10 serve as independent storage nodes for each capacitor, and the MOS transistor portion serves as a common electrode N+
A trench type memory cell structure of substrate electrode type is obtained, which is composed of a type Si substrate 1 and a substrate 3 which is insulated and separated.

For example, +1.5 V is applied as a plate potential to the N+ type Si substrate 1, and information is stored by storing signal electrodes in the capacitor electrodes 8 and 10 in the groove 6.

Further, as another embodiment, a method of forming a substrate common capacitor electrode (plate electrode) will be explained. Conventionally, the substrate plate electrode terminals can be drawn out from the back surface of the N+ type substrate 1, but there is also a method in which the terminals are drawn out from the front surface of the substrate, as shown in FIG. First, when drilling the grooves 6, grooves 6 are also simultaneously opened in the area where the plate terminals are to be taken in the peripheral field area. Thereafter, the insulating film 7 on the side surfaces of the groove is removed by lithography using a resist, and the surface of the groove of the substrate 1 is exposed. (Figure 10(a)). Thereafter, the first polycrystalline silicon layer 8 and the second polycrystalline silicon layer 10 are sequentially buried, impurities are diffused to the substrate side, and electrical connection is established. After that, after depositing interlayer insulating films 16 and 17, a contact hole is opened to the second polycrystalline silicon film, an Al wiring 20 is arranged, and the wiring is taken out from the surface to the plate electrode (substrate 1). It is possible. In this way, all the terminals can be removed from the surface of the board, increasing the degree of freedom during assembly.

In addition, in this embodiment, when making contact between the substrate 3 in the MOS transistor region and the capacitor electrode 8, a method was shown in which sidewall contact was made during the process of embedding the polycrystalline silicon film twice. Sidewall contacts of the MOS transistors to the substrate may be realized by conventional lithographic processes used. FIG. 11 shows an example of the process. In this case, embedding of the polycrystalline silicon film as the capacitor electrode only needs to be done once, and the process can be simplified.

In this embodiment, the mutual relationship between a plurality of memory cells adjacent in the word line direction is not shown. If the memory cell arrangement is a folded bit line method, the gate electrodes of memory cells adjacent in the word line direction will pass over the regions of the capacitor electrodes 8 and 10 in the figure. In the manufacturing process of the above embodiment, in this case, the gate electrode and the capacitor electrode are capacitively coupled via the oxide film obtained by thermally oxidizing the capacitor electrode 10. Since this thermal oxide film is a thermal oxide film of a polycrystalline silicon film, it is thicker than the gate insulating film 13, which is a thermal oxide film on single crystal Si, but a separate capacitor is used to reduce the coupling capacitance between the electrodes. It is effective to deposit a CVD oxide film or the like in the region. Of course, the present invention can also be applied to a DRAM with an open bit line configuration.

Next, an embodiment of the semiconductor memory device (hereinafter referred to as DRAM) according to claim 4 is shown in FIG.
Shown in a), (b) and (c).

FIG. 15(a) is a plan view showing two adjacent bits of the DRAM, and FIG. 15(b) is a plan view showing two adjacent bits of the DRAM.
15(c) is a cross-sectional view taken along line A-A' in FIG.
5(a) is a sectional view taken along the line BB'.

In FIGS. 15(a), 15(b), and 15(c), the insulating film layer 42 is formed between the semiconductor substrate 41 and the P-type Si substrate 43.
A trench is formed in the memory cell region so as to reach the insulating film layer 42. Insulating films 49, (491, 492, 493
) are formed inside the trench, and storage electrodes 51 (511, 512, 513) made of a first layer polycrystalline silicon film are formed inside the groove.
) is formed for each memory cell. Storage electrode 51 in the groove
A capacitor insulating film 54 (541, 542,
Plate electrodes 55 (551, 552) made of a second layer polycrystalline silicon film are embedded through the second layer polycrystalline silicon film 543). In this embodiment, the capacitor insulating film 54 is a Si3 N4 film formed by CVD and a so-called NO film whose surface is oxidized. Plate electrode 55 is commonly provided to a plurality of memory cells. In addition, capacitor regions 49, 51, 5
4 and 55, a gate electrode 58 (58
1,582) are disposed, and an n-type layer 59 (591, 592, 593), which is a source/drain diffusion layer of a MOS transistor, is self-aligned with each gate electrode. This n-type layer 59 is formed to be electrically connected to the storage electrode 51. For example, a partial diffusion layer 53 (531) of impurities from the storage electrode 51 to the substrate 43 side
, 532 , 533 ) and the n-type layer 59 are formed so as to be in contact with each other and are electrically connected to each other. As a result, the storage electrode 51 in the groove is connected to the MOS transistors 57, 58, 5.
It is electrically connected to one of the source/drain 59 of No. 9. Further, the gate electrode 58 is continuously arranged in one direction of the memory cells arranged in a matrix to form a word line. In this way, the MOS transistors 57, 58, 5
The substrate 43 on which the capacitors 9 and capacitors 49, 51, 54, and 55 are formed is covered with a CVD insulating film 60. Further, a contact hole is formed between the gate electrodes 58, and a bit line 63 made of polycide and connected to the n-type layer 59 is arranged in this contact hole. The bit line 63 is formed perpendicularly to the word line 58 without contacting it.

An embodiment of the method for manufacturing a semiconductor memory device according to claim 3 will be described below with reference to FIGS. 16 to 21.

Note that FIGS. 16(a), 17(a), . . . 21(a) are plan views of each DRAM manufacturing process, and FIGS. 16(b), 17(b), . . . (b) is a sectional view taken along the line A-A' of the DRAM in the corresponding manufacturing process.

As shown in the first manufacturing process in FIGS. 16(a) and 16(b), first, two Si substrates 41 and 43 are prepared, and one of them, the P- type Si substrate 43, has a memory cell. is formed.

Next, an oxide film 42 (42a, 42b) with a thickness of about 400 nm is formed on the surface of each Si substrate 41, 43 by thermal oxidation in a normal H2 + O2 atmosphere.
An oxide film 42b is superimposed on 2a to form a supporting Si substrate 4.
1 and a P- type Si substrate 43 are combined. In the joining method, for example, the pressure is reduced to about 10-1 Pa, and then a pulse voltage (±100 to ±50
0V) and bond. At this time, the substrate may be heated to about 800°C. Further, after this, a normal heat treatment (for example, at 1100° C. in a N2 atmosphere for about 30 minutes) may be performed. In this way, two Si substrates 41, 4
After adhering 3, normal polishing is performed from the side of the Si substrate 43 to thin the Si substrate 43. The polishing involves normal physical polishing and a mixture of hydrofluoric acid, nitric acid, and acetic acid as an etching solution. It may also be carried out in combination with chemical polishing using the etching method used. Next, the surface is mirror-polished in the same way as normal Si substrates are handled, and the Si
A Si substrate having a laminated structure in which an oxide film 42 and a P- type layer 43 are sequentially laminated on a substrate 41 can be obtained. As another method, SOI technology using a laser annealing method may be used to obtain this laminated structure substrate. Alternatively, a so-called SIMOX method (high temperature treatment after oxygen ion implantation) may be used.

In either case, the thickness of the P- type Si substrate 43 is set to a desired thickness, for example, about 5 μm, from the viewpoint of securing capacitor capacity.

Next, an oxide film 46 with a thickness of about 20 nm is formed on the surface of the Si substrate 43 by thermal oxidation, and a film with a thickness of 15 nm is formed by CVD.
A Si3 N4 film 47 of about 0 nm is sequentially formed. After this, a resist (
(not shown) Si3 N4 film 47, SiO2 with a mask
The film 46 and the Si substrate 43 are sequentially etched. At this time, the depth of the concave area obtained by etching is 0.5 μm.
Make sure that the amount is within the range. Furthermore, the size of the pattern formed at this time is smaller than the expected pattern size of the groove 8 which will be further etched in a later step.
The O2 film 46 and the Si3 N4 film 47 are left in place. The reason for this is to allow some leeway for pattern matching when creating the grooves 48. Next, after performing thermal oxidation to treat damage to the etched surface of the Si substrate 13,
After depositing, for example, a SiO2 film 44 on the entire surface of the Si substrate by the VD method, the recessed region (element isolation region) of the Si substrate 43 is etched back using a resist or the like.
Membrane 44 is selectively embedded.

Thereafter, as shown in the second manufacturing step in FIG. 17, the Si3 N4 film 47 and the SiO2 membranes 46, 44,
The Si substrate 43 is sequentially etched to remove the oxide film 42 in the substrate.
Groove 48 (481, 482, 483) to reach
form. Thereafter, in order to remove etching damage on the side surfaces of the grooves 48, for example, thermal oxidation may be performed, and then the resulting oxide film may be removed.

Next, as shown in the third manufacturing step in FIG. 18, an oxide film 49 (491, 492, 4
93) to a thickness of, for example, 50 nm, using a resist R by a normal photolithography method,
A part of the oxide film on the side surface of the groove is selectively removed using NH4F solution or the like to expose the Si substrate 43 and form an exposed portion 50 (501, 501,
502, 503).

Next, after removing the resist R by O2 ashing in an oxygen plasma atmosphere, as shown in the fourth manufacturing step in FIG. Storage electrode 51 (511, 51
2,513).

Next, arsenic (As+) is ion-implanted obliquely into the P- type Si substrate 43 through the storage electrode 51 on the exposed portion 10, thereby ion-implanting the sides of the trench 44 and filling the entire surface with arsenic. For example, 900
A heat treatment is performed for 30 minutes in N2. By re-diffusing the n-type impurity (As) into the Si substrate 43 in this way, the storage electrode 51 is formed as a part 53 (53) of the Si substrate 43.
1,532,533). After that, a photoresist is applied to the entire surface, and then the entire surface is exposed and developed to form a photoresist 5 only in the grooves 48.
2 (521, 522, 523) at the desired position. This photoresist 52 has the role of protecting the storage electrode 51 from etching described later. Furthermore, groove 4
The polycrystalline Si other than those in 8 is removed using, for example, a reactive ion etching method, leaving an N-type polycrystalline Si film 51 serving as a storage electrode only in the groove.

After that, the resist 52 is removed and the storage electrode 5
After cleaning the surface of the storage electrode 51, a capacitor insulating film 54 (541, 542) is deposited on the cleaned surface of the storage electrode 51, as shown in the fifth manufacturing step in FIG. As the capacitor insulating film 54, a Si3N4 film and an oxide film on its surface, or a multilayer film of these can be used. At this time, the Si3N4 film is formed by the CVD method, and the groove 48 is
A uniform film is also formed on the sidewalls and bottom surface of the capacitor, and the reliability of the capacitor insulating film 54 can be improved. For example, the thickness of each film is about 8 nm for the Si3 N4 film and about 2 nm for the thermal oxide film on its surface. Next, a second layer polycrystalline Si film 55 (551, 552) doped with n-type impurities is deposited on the entire surface and patterned to form a plate electrode 55 that will become a common cell plate.

At this time, the plate electrode 55 is precisely patterned and processed so as not to extend beyond the groove 48 into the MOS transistor region. The reason for this is that it becomes possible to reduce the margin for mask alignment of the gate electrode with respect to the plate electrode 55 in a later process, and further miniaturization of the memory cell becomes possible.

Next, as shown in the sixth manufacturing step in FIG. 21, thermal oxidation is performed in a steam atmosphere at 850° C., for example.
An oxide film 56 of about 100 nm is formed on the surface of the plate electrode 55.
(561,562) is formed. At this time, the groove 48
As shown in FIG. 20, a part of the Si3N4 film 47 is left in the MOS transistor formation region between the two.
Its surface is not oxidized. Alternatively, although not shown, before forming the capacitor insulating film 54 in the step shown in FIG.
The N4 film 47 is removed, and in the fifth manufacturing process, SiO2 is deposited by CVD to cover the plate electrode 55.
A film may be deposited and processed and used in place of the oxide film 56. In this way, it is possible to prevent the plate electrode 55 from becoming thinner and having high resistance due to oxidation of the plate electrode 55. Next, impurities are passed through the Si3N4 film 47 and the SiO2 film 46 so that the MOS transistor has a desired threshold voltage (Vth), and the channel impurity layer (
(not shown) is selectively formed on the P- type Si substrate 43, and then the Si3N4 film 4 in the MOS transistor region is formed.
7 and the oxide film 46 are once removed to expose the surface of the Si substrate 43, and a gate oxide film 57 of, for example, about 10 nm is formed. At this time, the gate insulating film 57 may be formed first, and then the channel impurity layer may be formed. Furthermore, a third layer polycrystalline Si film doped with n-type impurities is deposited and patterned to become a word line and gate electrode 58 (581
, 582) are formed above the channel impurity layer. Next, using this gate electrode 58 as a mask, for example, arsenic (As)
) or phosphorus (P) is ion-implanted through the gate oxide film 57 to form an n-type layer 59 (59
1,592,593,594). n
The type diffusion layer 59 partially overlaps the re-diffusion layer 53 which is in electrical contact with the storage electrode 51 already formed. Therefore, the storage electrode 51 on the inner wall of the groove 48 and the n-type diffusion layer 59 of the source/drain of the MOS transistor are electrically contacted.

Thereafter, as shown in FIG. 15, an insulating film of, for example, SiO2 is formed on the entire upper surface of the substrate 43 by CVD.
A film 60 is deposited, a contact hole 62 is opened in this SiO2 film 60 between the gate electrodes 58, and a contact hole 62 is formed between the gate electrodes 58.
A bit line 63 electrically connected to the n-type diffusion layer 592 is formed using a so-called polycide film made of i and tungsten silicide (WSi2). Other materials can also be used to form the bit line 63.

Further, a DRAM cell is manufactured by depositing a CVD insulating film, for example, a BPSG film, for passivation on the entire surface.

Therefore, in the DRAM of the above embodiment, since the insulating film layer 42 is formed at a certain depth within the semiconductor substrate, the depth of each groove is the distance from the surface of the semiconductor substrate to the insulating film layer 42. . Therefore, the storage electrode 51 and the capacitor insulating film 5
4 and the storage capacitance of the capacitor region formed by the plate electrode 55 can be easily set to a constant value.

Furthermore, since the bottom of the groove formed in the semiconductor substrate is formed along the insulating film layer 42, it has a flat structure at the interface with the insulating film layer 42. Therefore, even if the etching conditions fluctuate, the bottom of the groove will not have a sharp shape, and the withstand voltage of the capacitor will not deteriorate. Therefore, product yield is greatly improved.

[0078] Furthermore, since the bottom of the groove has a flat structure,
Even if thermal stress occurs after groove formation, crystal defects can be prevented from occurring. Therefore, generation of leakage current can be suppressed.

Furthermore, since the relatively thick insulating film 42 exists at the bottom of the trench, even if the insulating film 42 suffers etching damage, the insulating performance of the insulating film 42 is stable. Therefore, a stable and high quality insulating film 49 can be formed on the inner wall surface of the trench.

Furthermore, since the MOS transistor and capacitor regions are separated from the substrate below the insulating film layer by the insulating film layer, alpha rays etc.
The influence of secondary electrons generated at a depth of about m can be prevented. Therefore, the occurrence of soft errors can be significantly reduced.

In the above embodiments, the mutual relationship between memory cells adjacent in the direction of the word line 58 is not shown. If the memory cell arrangement is a folded bit line configuration, the plate electrode 55
Gate electrodes of memory cells adjacent in the direction of the word line 58 pass over the region. Of course, the present invention can also be applied to a DRAM with an open bit line configuration.

The present invention is not limited to the above-mentioned embodiments, but can be implemented in other suitable forms by making appropriate design changes.

[0083]

[Effect of the invention] As stated above, claims 1 and 2
According to the described semiconductor memory device and its manufacturing method, since the common capacitor electrode (plate electrode) is completely insulated and separated from the substrate forming the MOS transistor, a positive voltage is applied to the substrate electrode despite the substrate electrode type. can be applied, which makes it possible to apply 1/2 the same amount as conventional memory cells.
Vcc method can be used. Therefore, the electric field applied to the capacitor insulating film is about half that of a conventional substrate electrode type cell, and the reliability of the capacitor insulating film can be improved. Furthermore, since a thinner capacitor insulating film can be used, the storage capacity of the memory cell can be increased and stable operation of the memory cell can be achieved.

Further, since the plate electrode does not protrude onto the substrate and maintains a flat surface shape, subsequent processing of the gate electrode, etc., becomes easier, and the manufacturing process can be stabilized. Further, since a mask process and an etching process for forming a capacitor electrode and a plate electrode are not necessary, the process can be simplified.

Furthermore, the MOS transistor section is completely insulated and is extremely resistant to soft errors caused by α rays and the like.

Furthermore, since the MOS transistor section is made of a thin silicon layer that is completely insulated from the substrate, punch-through is less likely to occur, and the short channel effect is suppressed compared to conventional structures, so the MOS transistor can be miniaturized and increased in height. It is advantageous for densification.

Furthermore, since the silicon substrate on the insulating film forming the MOS transistor is thin, complete element isolation can be achieved by simply etching the substrate and burying the insulating film, and the PMOS and NMOS transistors can be completely isolated from the substrate. Since they are separated, there is no need to form a P-well and an N-well, which greatly simplifies the process.

Further, according to the method of manufacturing a semiconductor memory device according to claim 3, the step of forming an insulating film layer at a certain depth within a semiconductor substrate, and the step of forming an insulating film layer at a certain depth from the surface of the substrate. a step of forming a groove that reaches the substrate and has a flat interface with the insulating film layer; a step of covering the inner wall of the groove with an insulating film, leaving only a part of the inner wall; forming a storage electrode on the inner wall on the insulating film, which is electrically insulated and electrically contacts the substrate only through the partially exposed inner wall; and covering the surface of the storage electrode. a step of forming an insulating capacitor insulating film; a step of forming a plate electrode on the surface of the capacitor insulating film to hold charge between the capacitor insulating film and the storage electrode; and a MOS transistor. one of the source or drain diffusion layers is in electrical contact with the storage electrode via the partially exposed inner wall;
forming in the substrate adjacent to the groove,
Further, according to the semiconductor memory device according to claim 4, an insulating film layer formed at a certain depth within the semiconductor substrate and a part that reaches the insulating film at the certain depth from the surface and is connected to the insulating film layer. a groove with a flat boundary surface; an insulating film that covers an inner wall of the groove with only a portion remaining; and an inner wall that is electrically insulated from the substrate via the insulating film and is exposed with a portion of the inner wall remaining. a storage electrode that electrically contacts the substrate only through the storage electrode; an insulating capacitor insulating film that covers the surface of the storage electrode; and a plate that holds charges between the storage electrode and the capacitor insulation film. an MO in which one of a source or drain diffusion layer is in electrical contact with the storage electrode through the partially exposed inner wall in the substrate adjacent to the electrode and the groove;
Since the S transistor is provided, it is possible to easily manufacture a semiconductor memory device that does not cause deterioration of the capacitor breakdown voltage inside the trench and can suppress the occurrence of leakage current to a minimum.

[Brief explanation of the drawing]

FIG. 1 is a plan view and a cross-sectional view showing an embodiment of a DRAM according to claim 1.

FIG. 2 is an explanatory diagram showing a manufacturing process of the DRAM shown in FIG. 1;

FIG. 3 is an explanatory diagram showing a manufacturing process of the DRAM shown in FIG. 1;

FIG. 4 is an explanatory diagram showing a manufacturing process of the DRAM shown in FIG. 1;

5 is an explanatory diagram showing a manufacturing process of the DRAM shown in FIG. 1. FIG.

6 is an explanatory diagram showing a manufacturing process of the DRAM shown in FIG. 1. FIG.

7 is an explanatory diagram showing a manufacturing process of the DRAM shown in FIG. 1. FIG.

8 is an explanatory diagram showing a manufacturing process of the DRAM shown in FIG. 1. FIG.

9 is an explanatory diagram showing a manufacturing process of the DRAM shown in FIG. 1. FIG.

FIG. 10 is an explanatory diagram showing an example of a method for taking out a terminal of a plate electrode from the surface.

FIG. 11 is an explanatory diagram of another embodiment.

12 is an explanatory diagram showing a laminated substrate used in the embodiment shown in FIG. 1. FIG.

13 is an explanatory diagram showing a laminated substrate used in the embodiment shown in FIG. 1. FIG.

14 is an explanatory diagram showing a laminated substrate used in the embodiment shown in FIG. 1. FIG.

15(a) is a plan view showing two adjacent bits of an embodiment of the semiconductor memory device according to claim 4; FIG. 15(b) is a plan view showing two adjacent bits;
is a cross-sectional view taken along line A-A' of the semiconductor memory device shown in (a), and (c) is a cross-sectional view taken along line B-B' of the semiconductor memory device shown in (a).
FIG.

16 is an explanatory diagram showing an example of the manufacturing process of the semiconductor memory device shown in FIG. 15, according to an embodiment of the method for manufacturing a semiconductor memory device according to claim 3; FIG.

17 is an explanatory diagram showing an example of the manufacturing process of the semiconductor memory device shown in FIG. 15, according to an embodiment of the method for manufacturing a semiconductor memory device according to claim 3; FIG.

18 is an explanatory diagram showing an example of the manufacturing process of the semiconductor memory device shown in FIG. 15, according to an embodiment of the method for manufacturing a semiconductor memory device according to claim 3; FIG.

19 is an explanatory diagram showing an example of the manufacturing process of the semiconductor memory device shown in FIG. 15, according to an embodiment of the method for manufacturing a semiconductor memory device according to claim 3; FIG.

20 is an explanatory diagram showing an example of the manufacturing process of the semiconductor memory device shown in FIG. 15, according to an embodiment of the method for manufacturing a semiconductor memory device according to claim 3; FIG.

21 is an explanatory diagram showing an example of the manufacturing process of the semiconductor memory device shown in FIG. 15, according to an embodiment of the method for manufacturing a semiconductor memory device according to claim 3; FIG.

FIG. 22 is a sectional view showing a conventional DRAM.

FIG. 23 is a sectional view showing another conventional DRAM.

[Explanation of symbols]

1 N+ type Si substrate (common capacitor electrode, plate electrode) 2 Substrate isolation insulating film 3 MOS transistor forming substrate 4 Field insulating film 5 CVD insulating film 6 Groove 7 Capacitor insulating film 8 First polycrystalline silicon film 10 Second polycrystalline silicon film Crystalline silicon film 11 N-type diffusion layer 13 Gate insulating film 14 Gate electrode 15 Source/drain diffusion layer 18 Bit line 41 Semiconductor substrate 42 Insulating film layer 43 P-type Si substrate 44 SiO2 film 49 Insulating film 51 Storage electrode 53 Diffusion layer 54 Capacitor Insulating film 55 Plate electrode 56 Oxide film 57 Gate insulating film 58 Gate electrode 59 N-type layer 60 CVD insulating film 63 Bit line

Claims (4)

[Claims] 1. A second semiconductor substrate formed electrically isolated on the first semiconductor substrate, an element isolation region formed on the second semiconductor substrate, and a laminated substrate,
a groove provided to reach the first substrate; a capacitor electrode provided in the groove via an insulating thin film formed to expose a side surface of the second semiconductor substrate; What is claimed is: 1. A semiconductor memory device comprising: a MOS transistor; 2. A step of forming a laminated substrate consisting of a second semiconductor substrate provided electrically isolated on a first semiconductor substrate, and a step of forming an element isolation region in the second semiconductor substrate. a step of providing a groove in the laminated substrate so as to reach the first substrate; and a step of embedding a capacitor electrode in the groove through an insulating thin film formed so as to expose a side surface of the second semiconductor substrate. . A method of manufacturing a semiconductor memory device, comprising: forming a MOS transistor on the second semiconductor substrate. 3. A step of forming an insulating film layer at a certain depth in a semiconductor substrate, the step of forming an insulating film layer at a certain depth from the surface of the substrate, and having a flat interface with the insulating film layer. a step of forming a certain groove; a step of covering the inner wall of the groove with an insulating film, leaving a part of the inner wall; and a step of electrically insulating from the substrate via the insulating film, and leaving a part of the inner wall exposed. a step of forming a storage electrode on an inner wall on the insulating film, the storage electrode electrically contacting the substrate only through the inner wall thereof; a step of forming an insulating capacitor insulating film covering the surface of the storage electrode; forming a plate electrode on the surface of the insulating film to hold charge between the capacitor insulating film and the storage electrode; 1. A method of manufacturing a semiconductor memory device, comprising the step of: forming in the substrate adjacent to the groove so as to be in electrical contact with the storage electrode through an inner wall. 4. An insulating film layer formed at a certain depth in a semiconductor substrate, and a groove that reaches from the substrate surface to the insulating film layer at a certain depth and has a flat interface with the insulating film layer. an insulating film that covers the inner wall of the groove with a portion thereof remaining; and an insulating film that is electrically insulated from the substrate via the insulating film, and the substrate is electrically insulated only through the inner wall that is partially left and exposed. a storage electrode in electrical contact with the storage electrode; an insulating capacitor insulating film covering the surface of the storage electrode; a plate electrode that holds charges between the storage electrode and the capacitor through the capacitor insulating film; A semiconductor memory device comprising: a MOS transistor in the adjacent substrate, one of the source or drain diffusion layers electrically contacting the storage electrode via the partially exposed inner wall.