JPH05265658A - Analog output device - Google Patents

Abstract

PURPOSE:To change an output waveform at real time and to output the changed waveform synchronously with an external signal. CONSTITUTION:An analog output device for successively writing digital signals sampled and stored in a memory 24 in a digital/analog conversion part 20, converting the written digital signal into analog voltages by using an external signal as a reference and outputting the analog voltages is provided with a synchronism control means 21 for inputting an external signal into the conversion part 20, converting and outputting the written digital signals and then turning on an identification flag 22 and a writing means 23 for monitoring the identification flag 22, reading out the succeeding digital signal from the memory 24 when the identification flag is ON, writing the read signal in the conversion part 20 and then turning off the identification flag 22.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to improvements in analog output devices. BACKGROUND ART An analog output device for analog-converting digital-converted waveform data (hereinafter referred to as a digital signal) and outputting the same is often used in research and development fields, manufacturing fields, and the like using computers.

In this analog output device, when data is output in synchronization with a reference clock given from the outside, the timing at which a digital signal is read from a memory and written in a DAC (digital-analog converter), and the written digital signal is written. It is necessary to synchronize with the timing of analog conversion and output, and when changing the waveform, real-time property that can be changed immediately is required.

[0003]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional example. Figure 5
A configuration example in which an analog output unit (AO unit) 3 is added to a data processing device having a processor CPU1 and a memory 2 is shown. Digitally converted waveform data A and waveform data B (waveforms A and B in the figure). ) Is stored in the memory 2. When the waveform A is designated and an output command is issued from a keyboard (not shown), CP
U1 sets the address, data length, etc. of the head data of the waveform A in the DMA controller 6 of the AO unit 3 and activates the AO unit 3. As a result, the DMA control unit 6
The waveform data A is read one by one from the memory 2 by using the reference clock as a trigger, and the first-in first-out memory F is read.
Store in IFO4. On the other hand, in response to this DMA transfer, F
The data output from the IFO 4 is sequentially written into a register provided inside the DAC 5 (not shown) using the reference clock as a trigger, and is DA converted and output. The DMA control unit 6 is configured to repeatedly read one cycle of data stored in the memory 2, and the waveform A is output at a repetition frequency according to the reference clock.

In this state, for example, when the operator designates the waveform B, the CPU 1 terminates the DMA transfer of the waveform data A, instructs the DMA controller 6 to transfer the waveform data B, and the DMA controller 6 causes the memory 2 to operate. The waveform data B is read out and transferred to the FIFO 4. This allows the DAC5
Output is changed from waveform A to waveform B.

[0005]

In the above-mentioned conventional method of transferring one data by one data to the AO unit by DMA transfer using the reference clock as a trigger and DA conversion, when the output waveform is changed, the DMA transfer is temporarily terminated, The DMA transfer procedure for the next waveform output must be performed. Therefore, as shown in FIG. 5, the DMA transfer is suspended and the FIFO
An idle time occurs in which the output of 4 is constant. This idle time cannot be ignored especially in the case of high-speed output, and the real-time property such as delay in waveform change is lost.

Therefore, in FIG. 5, data is read from the memory 2 in the program mode by the CPU 1 and DA
A method of writing to C5 is conceivable, but there is a problem that the CPU 1 that performs other processing in parallel is burdened, or that the output waveform is distorted because writing cannot be performed in synchronization with the reference clock.

In view of the above problems, it is an object of the present invention to provide an analog output device that is synchronized with an external signal and has a real-time property that does not cause an idle time such as a delay when changing a waveform.

[0008]

In the principle diagram of the present invention shown in FIG. 1, reference numeral 24 is a memory in which sampled digital signals such as waveform data are stored. Reference numeral 20 denotes a digital-analog converter, which converts the written digital signal into an analog voltage based on an external signal and outputs the analog voltage. Reference numeral 21 denotes a synchronization control means, which inputs an external signal to the digital-analog converter 20 to convert and output the written digital signal, and then turns on the identification flag 22. A writing means 23 monitors the identification flag 22, and when the identification flag is on, the next digital signal is read from the memory 24 and written in the digital-analog converter 20, and the identification flag 22 is turned off.

[0009]

The synchronizing control means 21 inputs the external signal to the digital-analog converter 20, converts the written digital signal into an analog signal and outputs it, and then turns on the identification flag 22. The writing means 23 monitors the identification flag, and if the identification flag 22 is turned on, after writing the next digital signal stored in the memory 24 to the digital-analog converter 20, the identification flag 22 is turned off.

As described above, the analog signal can be output in synchronization with the external signal, and since the DMA method is not used, the idle time does not occur and the waveform is continuously changed, so that the real time property is obtained. Be improved.

[0011]

FIG. 2 is a block diagram of an embodiment, FIG. 3 is an operation time chart, and FIG. 4 is a process flowchart.

In the AO unit 10 shown in FIG. 2, 11 is a synchronization control section (corresponding to the synchronization control means 21), which inputs a received external signal (hereinafter referred to as a reference clock) to the digital-analog converter DAC5, and then an identification flag FLAG12. Turn on (corresponding to identification FLAG22, which is composed of a register, for example). A microprocessor unit MPU (corresponding to the writing means 23) 13 monitors the FLAG 12 at a predetermined cycle faster than the reference clock, and if ON, reads the next data from the memory 2 and writes it in the DAC 5. Throughout all the other drawings, the same reference numerals denote the same objects.

With the above configuration, the following analog output operation is performed. See FIGS. 3 and 4. It is assumed that the waveform data is stored in the memory 2, the storage address, the data length, etc. are stored in another area of the memory 2, and the MPU 13 can recognize the storage address. (S1) The synchronization control unit 11 passes the reference clock received after the conversion instruction to the DAC 5. As a result, the DAC 5 DA-converts the digital signal stored in the register (not shown) at the falling edge of the reference clock (see FIG. 3) and outputs it. The synchronization control unit 11 uses the falling edge of the reference clock (DA
After a predetermined time from (after conversion), FLAG12 is turned on. Note that the DAC 5 is cleared at the beginning of conversion and the "0" voltage is initially output. (S2) MPU13 constantly monitors FLAG12 at a time interval shorter than the reference clock. (S3) When FLAG12 is turned on,
Of the designated waveform data, the next data is read and written in the DAC 5, and (S4) FLAG12 is turned off.

As described above, the M provided in the AO unit 10
Since the data read from the memory 2 is directly written into the DAC 5 according to the program mode by the PU 13, unlike the DMA method in which the data is written into the FIFO having at least two stages of registers, idle time does not occur when changing the waveform.

Further, in FIG. 1, the conversion output and the writing are synchronized by the FLAG 12 as compared with the method according to the program mode of the CPU 1, so that waveform distortion or the like does not occur.

[0016]

As described above, the present invention provides an analog output device that outputs an external signal as a trigger.
The identification flag is turned on after output by an external signal, and the next data is written to the digital-to-analog converter when this identification flag is turned on. An analog signal synchronized with the external signal can be output and the DMA transfer method is used. Therefore, when changing the output waveform, there is an effect that it can be changed in real time without delay time.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

[Fig. 3] Operation time chart

[Fig. 4] Process flow chart

FIG. 5 is a block diagram of a conventional example

[Explanation of symbols]

 1 processor CPU 2 memory 3 AO unit 4 first-in first-out memory FIFO 5 digital-analog converter DAC 6 DMA control unit 10 AO unit 11 synchronization control unit 12 identification flag FLAG 13 microprocessor MPU 20 digital-analog converter DAC 21 synchronization control means 22 identification flag 23 Writing means 24 Memory

Claims (1)

[Claims] 1. A digital signal sampled and stored in a memory (24) is sequentially written into a digital-analog converter (20), and each written digital signal is converted into an analog voltage based on an external signal and output. An analog output device for inputting the external signal to the digital-analog converter (20) to convert and output the written digital signal, and then to turn on an identification flag (22). Means (21)
The identification flag (22) is monitored, and when the identification flag is on, the next digital signal is read from the memory (24) and written to the digital-analog converter (20), and the identification flag is turned off. An analog output device, comprising: a writing means (23).