JPS62168220A - Data input device - Google Patents

Abstract

PURPOSE:To obtain data which are arranged in terms of time by storing the data digitized by an A/D converter temporarily into an FIFO circuit set at the preceding stage. CONSTITUTION:A/D converters 2a-2c digitize the analog signals by the start timing signals S1-S3 for A/D conversion and output them to the FIFO circuits 4a-4c of the preceding stage together with A/D conversion end signals E1-E3. In this case, the end timings of signals E1-E3 are different among converters 2a-2c. The circuits 4a-4c deliver the output enable signals OR1-OR3 when the input data reach an output part DO. While an AND circuit 8 delivers the coincidence signal G to a control circuit when the output enable signals of circuits 4a-4c are obtained. Thus the control circuit supplies the reading shift- out pulses SO to the circuits 4a-4c in response to the signal G and in order of the starts of A/D conversions and at the same time switches successively the multiplexers 6 to send successively data to an FIFO circuit 10 of the next stage.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a data input device used for converting analog signals into digital data and importing this data into a computer or the like.

(b) Prior art and its problems When digitizing a large amount of analog signals obtained by various measuring instruments, it is necessary to perform A/D conversion at high speed.

In such cases, if you use a high-speed A/D converter,
Although it becomes possible to convert large amounts of analog signals into digital data, such high-speed A/D converters are technically difficult and expensive, and their peripheral circuits also require high speed. This increases the cost of the entire circuit.

The present invention has been made in view of these circumstances, and uses a relatively low-speed A/D converter to convert a large amount of analog signals into high-speed and well-aligned digital data for external transmission. The purpose is to make it possible to import data into an arithmetic processing device such as a storage device or a computer by making full use of direct memory access (DMA).

(c) Means for Solving the Problems In order to achieve the above object, the present invention provides a point-by-point comparison type A/D converter arranged in parallel to analog signal input, and each A/D converter. A pre-stage FIFO circuit individually connected to the converter, an AND circuit that outputs a coincidence signal in response to an output enable signal indicating a data output enable state is output from each pre-stage FIFO circuit, and this AND circuit. In response to a match signal from the circuit, each pre-FIFO
The data input device includes a subsequent FIFO circuit that stores data sequentially read out from the circuit in the order in which A/D conversion is started.

(D) Function In the data input device of the present invention, analog signals inputted by the successive comparison type A/D converters arranged in parallel are sequentially digitized.

In this case, the start of A/D conversion is performed periodically and with a time shift for each A/D converter.

Therefore, each A/D converter converts A/D at a relatively low speed.
A/D conversion is started for the analog signal at high speed.

Since the A/D conversion time is related to the analog signal level to be digitized, the conversion end timing differs for each A/D converter. Therefore, the data digitized by each A/D converter is temporarily stored in the pre-stage FIFO circuit to adjust the delay time for completion of A/D conversion.

When data is stored in the pre-stage FIFO circuit, each pre-stage FIFO
The FO circuit outputs output enable signals indicating the data output enable state, and these output enable signals are applied to the AND circuit. Then, in response to this, a match signal is output from the AND circuit, so that in response to the match signal from the AND circuit, the subsequent FIFO circuit sequentially reads data from each previous stage FMFO circuit at the start of A/D conversion. Store data.

This allows the temporally aligned data to be transferred to the subsequent FIFO.
stored in the circuit.

Therefore, this data input device can obtain data that is digitized and aligned at high speed.

(e) Embodiment FIG. 1 is a block diagram of a data input device according to an embodiment of the present invention. In the figure, reference numeral 1 indicates the entire data input device, and 2a to 2C indicate a plurality of (three in this example) successive approximation type A/D converters arranged in parallel to the analog signal input; 4a to 4C are pre-stage FTFO circuits individually connected to each A/D converter 2a to 2C. Each of the preceding stage FrFo circuits 4a to 4C is set to have a storage capacity sufficient to compensate for the delay in A/D conversion time. Further, 6 is a multiplexer that sequentially switches and outputs the data stored in each of the pleural FIFO circuits 4a to 4C, and 8 is a multiplexer that outputs the data stored in each of the pre-stage FIFO circuits 4a to 4C when all output enable signals indicating the data output enable state are output. an AND circuit that outputs a match signal in response;
Reference numeral 10 designates a rear-stage F'lF'O circuit that stores data sequentially read out from each of the front-stage FIFO circuits 4a to 4c in the order of A/D conversion start in response to the match signal from the AND circuit 8.

Next, the operation of this data human-powered device 1 will be explained.

In this data input device I, each A/
Start signals S1 to S3 that set the start timing of A/D conversion are given to the D converters 2a to 2C, respectively, so each A/D converter 2a to 2C performs A/D conversion in response to these start signals S, to S3. /Start D conversion. In this case, each of the start signals SI to S3 is a signal whose period T is constant and whose phase is shifted every predetermined time T2, as shown in FIG. Therefore, each A/D converter 2a to 2c performs A/D conversion every fixed period T, but for analog signals, it performs 1/1/1 of the period T1.
A/D conversion will start at time 3 (=T 2).

When the A/D conversion of the sampled analog signal is completed, each A/D converter 2a to 2c outputs an A/D signal.
End signals E and -E3 indicating the end of D conversion are output. This end signal El-E3 is applied to the pre-stage FIFO circuits 4a to 4C.
is input as a shift impulse. Therefore, A
/D conversion is completed, the digitized data is transferred to each of the preceding stage FrFO circuits 4a to 4c1. :
Stored. In this case, in the successive approximation type A/D converters 2a to 2C, the A/D conversion time differs depending on the analog signal level to be digitized, so the timing of data stored in the preceding stage FIFO circuits 4a to 4c also differs. .

When the data input to the input section DI of each pre-stage FIFO circuit 4a to 4C reaches its output section Do, each pre-stage FIFO circuit
The FO circuits 4a to 4C output enable signals OR, -OR3 indicating the data output enable state, and these output enable signals OR, -ORs are applied to the AND circuit 8.

Output enable signal OR from each pre-stage FIFO circuit 4a to 4c
, ~OR, are output, the AND circuit 8 outputs a match signal G. This coincidence signal G is output to a control circuit (not shown).

In response to the match signal G from the AND circuit 8, the control circuit applies shift-out pulses for data reading to each of the pre-stage FIFO circuits 4a to 4C in the order of A/D conversion start, and sequentially switches the multiplexer 6. As a result, data is output from the pre-stage FIFO circuits 4a to 4c in the order in which A/D conversion is started. At this time, the control circuit is
Sequentially give shift impulses for data storage control to rear stage FIF○ circuit ①0. In this way, each data is input to the subsequent FIFO circuit IO via the multiplexer 6. Therefore, even if the end timing of A/D conversion is reversed, the second stage FIFO circuit 1G has no A/D conversion end timing.
The data arranged in the start class of /D conversion will be stored.

Therefore, even when data is subsequently transferred to an external storage device or main memory, the aligned data can be taken in by reading out the data stored in the subsequent stage FrFO circuit 10 as is.

In this embodiment, three A/D converters 2a to 2C and three front-stage 1'l'lF'O circuits 4a to 4c are provided, but it goes without saying that the present invention is not limited to this. .

(F) Effects As described above, according to the present invention, a relatively low-speed A/D converter is used to convert a large amount of analog signals into high-speed and well-aligned digital data, which is then processed by computers, etc. Excellent effects such as being able to be incorporated into devices are exhibited.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data input device according to an embodiment of the present invention, and FIG. 2 is a timing chart showing the start and end of A/D conversion. l...Data input device, 4a-4c...front stage FIF
O circuit, 8...AND circuit, 0...second stage FIFO
circuit.

Claims (1)

[Claims] (1) A successive approximation type A/D converter placed in parallel with the analog signal input, and a pre-stage FIFO connected individually to each A/D converter.
an AND circuit that outputs a match signal in response to an output enable signal that indicates a data output enable state from each pre-stage FIFO circuit; A rear-stage FIF that stores data sequentially read out from the front-stage FIFO circuit in the order of A/D conversion start.
A data input device comprising: an O circuit.