JPH03269371A - Waveform storage device - Google Patents

Abstract

PURPOSE:To constitute a slow and inexpensive circuit by detecting a maximum value and minimum value furthermore out of plural maximum values and minimum values successively outputted from size comparators, storing successively inputted data in a memory, and at the time of reading out the data from the memory, detecting the maximum value and the minimum value. CONSTITUTION:A digital signal analog/digital converted from an analog signal by a sampling clock is distributed to plural size comparators 26, 27, 29, 30 by a distributer 25 to compare the digital data from the distributer 25 in stages. The maximum value and the minimum value are detected out of plural maximum values and minimum values successively outputted from the comparators 26, 27, 29 30 and the digital data obtained by analog/digital conversion are successively stored in the memory 33 and the maximum value and the minimum value are detected from plural output data of the memory 33.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital waveform storage device used in measurement devices such as recorders, digital oscilloscopes, and waveform analyzers.

BACKGROUND OF THE INVENTION Conventionally, this type of waveform storage device, as shown in FIG.
It is equipped with a sample clock generator 1, an analog/digital converter 2, a data latch 3, a digital comparator 4, a control logic 5, an operation mode register 6, a recording clock generator 7, an address counter 8, and a memory 9. 58
(Refer to Publication No.-47661). 10 surrounded by a broken line is a data latch 3, a digital comparator 4, and a data bus 11.1.
2 and a control signal 13.

The analog signal is input from the analog input terminal 14 to the analog/
The digital converter 2 converts the digital data into n-bit digital data at the cycle of the sample pulse generated by the sample clock generator 1, and outputs it to the data latch 3. This digital data is compared with two previously fetched digital data recorded in two latches in the data latch 3 by two comparators in the digital comparator 4. The two previously captured digital data are the maximum value and the minimum value, and if the new digital data output from the analog/digital converter 2 is larger than the already recorded maximum value or smaller than the minimum value, The digital comparators 4 each communicate to the control logic 5 that a new value has been detected.

This causes the control logic 5 to strobe the latch to be updated and transfer the new maximum or minimum value to the data latch 3.
to be recorded. This operation is repeated at the cycle of the sample pulse, and the recorded contents in the data latch 3 are updated every time a new maximum or minimum value is detected. The recording clock generator 7 updates the address counter 8 with the generated clock pulse, and records the maximum and minimum values recorded in the data latch 3 in the memory 9 at the memory address indicated by the address counter 8. At the same time, the control logic is also updated, two latches in the data latch 3 are reset, and maximum and minimum value detection is started anew.

FIG. 4 shows the operation timing of the conventional device, and shows recorded data when no peak detection is performed using the sample clock, analog signal, and recording clock, and maximum and minimum value recorded data when peak detection is performed. There is.

In this way, even with the conventional waveform storage device, an analog signal can be converted into a digital signal, and its maximum and minimum values can be detected and stored.

Problems to be Solved by the Invention However, in the conventional waveform storage device, the digital peak detector 10 must operate with a sample clock at the same speed as the analog/digital converter 2.
When the sample clock is high speed, there is a problem that the digital peak detector 10 becomes expensive.

The present invention solves these conventional problems, and even when the sample clock is high-speed, it is possible to detect digital peaks at the same speed as the sample clock using a low-speed, inexpensive digital peak detector. The objective is to provide an excellent waveform storage device that can achieve equivalent resolution.

Means for Solving the Problems In order to achieve the above object, the present invention distributes a digital signal obtained by converting an analog signal from analog to digital using a sample clock to n magnitude comparators (n is a natural number), and each distributor The digital data from the digital data is compared in multiple stages, and the maximum and minimum values are detected from among the multiple maximum and minimum values sequentially output from each magnitude comparator, and the digital data converted from analog to digital is sequentially The data is stored in a memory, and the maximum and minimum values are detected from among a plurality of output data from the memory.

Operation The present invention has the following effects due to the above configuration. In other words, when detecting the maximum value and minimum value from n integer multiples of data, the data converted from analog to digital using the sample clock is distributed to multiple magnitude comparators,
Since digital peak detection is performed after finding the maximum and minimum values from n pieces of data using a tournament method, each magnitude comparator and digital peak detector must operate at a speed of 1/n of the sample clock. good. Furthermore, when detecting the maximum and minimum values from data other than an integral multiple of n, digital peak detection is performed after storing analog/digital converted data in memory.
It is sufficient that the digital peak detector operates at a speed at most equivalent to the memory read speed. Therefore, with a low-speed and inexpensive circuit configuration, it is possible to detect digital peaks with the same resolution as when digital peaks are detected at the same speed as the sample clock.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, 21 is an analog input terminal, which is connected to an analog/digital converter 23. 22 is a sample clock generator, and the sample clock outputted from this is input to the analog/digital converter 23 and the control logic 24. Analog/digital converter 2
The output of No. 3 is inputted to a four-phase distributor 25, and four pieces of data are inputted to two magnitude comparators 26, 27 and data selector A of the data selector 28. The output data of the magnitude comparators 26.27 is inputted to another two magnitude comparators 29.30 and compared in magnitude, and then input to a digital peak detector 31.32. Output data from the digital peak detectors 31, 32 is input to data selector 28 B. The output of the data selector 28 is input manually as data in the memory 33. On the other hand, the output of the address counter 34 is input as an address of the memory 33. The data read from the memory 33 is input to the data selector 35 A and the digital peak detector 36 , and the output of the digital peak detector 36 is input to the data selector 35 B.

The output of the data selector 35 is input to the display section 37. The distributor 25, the magnitude comparators 26, 27, 29.30 and the digital peak detectors 31.32 are controlled by the control logic 2.
Controlled by 4. Digital peak detector 36 is controlled by readout controller 38. The address counter 34 is connected to the control logic 24 and the read controller 3.
8.

Next, the operation of the above embodiment will be explained. In the embodiment described above, the analog signal inputted from the analog input terminal 21 is converted into bits of digital data by converting the instantaneous value of the analog signal into bits of digital data in the analog/digital converter 23 with a period T determined by the output of the sample clock generator 22. Convert to

When the four bits of digital data are input to the distributor 25, the four bits of digital data are simultaneously output to the magnitude comparators 26, 27 and the data selector A of the data selector 28. During this time, the next bit of digital data is input to the distributor 25, and when four pieces of data have been input, four pieces of digital data are simultaneously output as in the previous case. That is, four pieces of digital data are output from the distributor 25 at a rate of period 4T. The magnitude comparators 26 and 27 respectively output the larger digital data of the two digital data to the magnitude comparator 29 and output the smaller digital data to the magnitude comparator 30. Furthermore, size comparator 2
9 inputs the larger digital data of the two manual inputs to the digital peak detector 31, and the magnitude comparator 30 inputs the smaller digital data of the two manual inputs to the digital peak detector 32.
Output to. In the digital peak detector 31, m pieces of data are manually inputted one after another every cycle of peak detection, the maximum value is detected from the data, and is output to B of the data selector 28. Similarly, the digital peak detector 32 detects the minimum value and outputs it to B of the data selector 28. In this way, the data output to B of the data selector 28 is determined when the number of digital data manually input to the distributor 25 for each peak detection period is an integer m times the number of data 4 simultaneously output from the distributor 25. The maximum and minimum values of

FIG. 2 shows the relationship between the peak detection period and the number of data manually input to the distributor 25 within that period when the sample clock period T is 5 nsec. As is clear from this figure, the peak detection period is 20nSeC and 1QQ
At nsec or more, the number of digital data input to the distributor 25 for each peak detection period is an integral multiple of 4. At this time, the data input to B of the data selector 28 is output to the memory 33, and the memory 33 writes these data to an address determined by the output of the address counter 34 controlled by the control logic 24. After the necessary data has been loaded into the memory 33, the data is read from the address determined by the output of the address counter 34 controlled by the read controller 38, passed through the data selector 35, and is output to the display section 37. Ru.

Peak detection period is 5 n5ec, 10 n5ec,
50 n5eC, the number of digital data input to the distributor 25 for each peak detection period is not an integral multiple of 4. At this time, eight data of the data selector 28 are written into the memory 33. After the necessary data has been loaded into the memory 33, the data read out from the memory 33 is input to a digital peak detector 306 controlled by a readout controller 38. In the digital peak detector 36, the second
The maximum value and the minimum value are detected from among the number of data shown in the figure, and outputted to the display unit 37 through eight data selectors 35 .

As described above, according to the embodiment, the output data of the analog-to-digital converter 23 is divided into four parts by the distributor 25, so when the peak detection period is 2Qnsee and 1QQnsec or more, the sampling period is 5nsec.
This has the advantage that it is possible to construct an inexpensive circuit that calculates the maximum and minimum values with a period of 20 n see, which is four times the period of 20 n see. Furthermore, since the digital peak detector 36 only needs to operate at the same speed as the reading speed of the memory, it can be configured with a low-speed and inexpensive circuit.

Effects of the Invention As is clear from the embodiments described above, the present invention provides a plurality of large and small values in which n pieces of digital data taken in sequentially are input to a distributor and the maximum and minimum values are detected from among the n pieces of digital data. Since it is equipped with a comparator and a means for further detecting the maximum value and minimum value from among the plurality of maximum values and minimum values sequentially output from the magnitude comparator, In order to detect the value and the minimum value, the operating speed is 1/n of the sample clock, allowing a low-speed and inexpensive circuit configuration. In addition, since it is equipped with a means for storing sequentially captured data in memory and detecting the maximum and minimum values when reading from the memory, it is possible to detect the maximum and minimum values from digital data other than an integral multiple of n. can be as fast as reading from memory,
Therefore, with a low-speed and inexpensive circuit configuration, it is possible to realize an excellent waveform storage device that has a resolution equivalent to that obtained when digital peak detection is performed at the same speed as the sample clock.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data acquisition section in a waveform storage device showing an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between the peak detection period and the number of data in an embodiment of the present invention, and FIG. A block diagram of a data acquisition section in a conventional waveform storage device, 1 2 FIG. 4 is an operation timing chart in the conventional device. 21... Analog input terminal, 22... Sample clock generator, 23... Analog/digital converter, 2
4... Control logic, 25... Distributor, 26°27
．． 29.30... Magnitude comparator, 28... Data selector, 31.32... Digital peak detector, 33.
...Memory, 34...Address counter, 35...
Data selector, 36...Digital peak detector, 3
7... Display section, 38... Readout controller.

Claims (1)

[Claims] an analog/digital converter that samples an analog signal using a sample clock and converts it into digital data; a distributor that distributes the digital data sequentially output from the analog/digital converter into n pieces; A multi-stage magnitude comparator that detects the maximum and minimum values from among the data, and a multi-stage magnitude comparator that detects the maximum and minimum values from among the multiple maximum and minimum values sequentially output from the multi-stage magnitude comparator. A waveform memory comprising: a means for detecting, a memory for storing digital data output from the analog/digital converter, and a means for detecting a maximum value and a minimum value from a plurality of digital data read from the memory. Device.