JP2011058986A - Electric current difference circuit and maximum electric current detecting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a maximum electric current detecting circuit with the superposition of noises prevented by a simple structure. <P>SOLUTION: This maximum electric current detecting circuit includes a difference electric current circuit 10A and a fifth P-channel MOS transistor P5. The current circuit 10A is equipped with: a first MOS transistor P1 with a first current input terminal Tin1 connected to a drain, a gate connected to the drain, and a source connected to a power supply line La; a second MOS transistor P2 with a second current input terminal Tin2 connected to a drain, a gate connected to the gate of the MOS transistor P1, and a source connected to the supply line La; a third MOS transistor P3 with the input terminal Tin2 connected to a drain, a gate connected to a drain, and a source connected to the supply line La; and a fourth MOS transistor P4 with a gate connected to the gate of the third MOS transistor, a source connected to the supply line, and a current from a drain supplied to an electric current output terminal Tout. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a current difference circuit that detects a difference in current and a technical field of a maximum current detection circuit that detects a maximum current using the current difference circuit.

Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique for determining the magnitude of a current by converting two currents into voltages and comparing the converted voltages.
To apply the above-described technique to the maximum current detection circuit that outputs the larger current when two currents are input, the magnitude of the current is determined by the above-described technique, and the two currents are determined according to the determination result. A selection circuit that outputs one of them may be used.

JP 2007-258243 A (see FIG. 1)

  However, since the conventional maximum current detection circuit requires a selection circuit, the circuit configuration is complicated. In addition, there is a problem that discontinuities occur when the current is switched in the selection circuit.

  The present invention has been made in view of the above-described problems, and an object thereof is to provide a maximum current detection circuit that does not require a current selection circuit and a differential current circuit used therefor.

  In order to solve the above-described problem, an amplifying device according to the present invention includes a first current input terminal, a second current input terminal, a current output terminal, a power supply line, the first current input terminal, and a drain. The first MOS transistor whose gate is connected to the drain, the source is connected to the power supply line, the second current input terminal and the drain are connected, and the gate is connected to the gate of the first MOS transistor. A second MOS transistor having a source connected to the power supply line, a second MOS input terminal connected to the drain, a gate connected to the drain, and a third MOS transistor connected to the power supply line. A transistor, a gate is connected to the gate of the third MOS transistor, a source is connected to the power supply line, and a current from the drain is supplied to the current output terminal. That and a fourth MOS transistor, and wherein the.

  According to this invention, when the current supplied from the first current input terminal is the first current I1 and the current supplied from the second current input terminal is the second current I2, the second input current I2 is the first input. When the current I1 exceeds the current I1, "I2-I1" is output as an output current from the current output terminal, whereas when the second input current I2 is equal to or less than the first input current I1, the output current becomes zero. Here, the MOS transistor may be either a P-channel type or an N-channel type.

Next, the maximum current detection circuit has the above-described current difference circuit, the gate is connected to the gate of the first MOS transistor, the source is connected to the power supply line, and the current from the drain is supplied to the current output terminal. And a fifth MOS transistor.
According to the present invention, the first MOS transistor and the fifth MOS transistor constitute a current mirror circuit. For this reason, the current output from the current output terminal is obtained by adding the first input current I1 to the output current of the current difference circuit. As a result, when the second input current I2 is larger than the first input current I1, “I2” is output as the output current from the current output terminal, while the second input current I2 is less than or equal to the first input current I1. In this case, the output current becomes “I1”.
According to this configuration, since the current is converted into a voltage and not compared, the current-voltage conversion circuit can be made unnecessary. Also, no comparator is required for comparison. Furthermore, a switch circuit for selecting a current is not necessary. Moreover, switching noise at the time of switching is not superimposed on the output current. Therefore, according to the present invention, it is possible to output a maximum current in which noise superposition is suppressed while greatly simplifying the circuit configuration.

  In the maximum current detection circuit described above, a sixth MOS transistor is provided between the current output terminal and the fourth MOS transistor, and a seventh MOS transistor is provided between the current output terminal and the fifth MOS transistor. A fixed potential may be supplied to the gates of the sixth MOS transistor and the seventh MOS transistor. In this case, it is possible to employ a cosplay code connection and reduce the influence of the mirror effect.

Further, the current difference circuit and the maximum current detection circuit according to the present invention can be configured by bipolar transistors instead of MOS transistors. A specific mode of the current difference circuit includes a first current input terminal, a second current input terminal, a current output terminal, a power supply line, the first current input terminal and a collector, and a base connected to the collector. A first bipolar transistor having an emitter connected to the power supply line; a second current input terminal connected to the collector; a base connected to a base of the first bipolar transistor; and an emitter connected to the power supply line A second bipolar transistor connected to the second current input terminal, a second current input terminal connected to the collector, a base connected to the collector, an emitter connected to the power line, and a base connected to the power supply line. The emitter of the third bipolar transistor is connected to the power supply line, and the current from the collector is applied to the current output terminal. Characterized in that a feed is the fourth bipolar transistor are.
In the maximum current detection circuit, the current difference circuit, the base is connected to the base of the first bipolar transistor, the emitter is connected to the power supply line, and the current from the collector is supplied to the current output terminal. And a fifth bipolar transistor. Here, the bipolar transistor may be a PNP transistor or an NPN transistor.

  Further, N (N is an integer of 2 or more) maximum current detection circuits described above are provided, and the N maximum current detection circuits are cascade-connected via a current mirror circuit, and the current mirror circuit has a certain maximum current detection The current output terminal and input terminal of the circuit may be connected, and one of the first current input terminal or the second current input terminal of another maximum current detection circuit and the output terminal may be connected. In this case, the number of input currents can be expanded to N + 1.

It is a circuit diagram of 1 A of maximum current detection apparatuses which concern on this embodiment. It is a circuit diagram which shows the other structural example of 1 A of maximum current detection apparatuses which concern on this embodiment. It is a block diagram which shows the structural example of 100 A of maximum current detection apparatuses which concern on this embodiment. It is a circuit diagram of maximum current detection device 1B concerning this embodiment. It is a block diagram which shows the structural example of the largest electric current detection apparatus 100B which concerns on this embodiment. It is a circuit diagram of 1 C of maximum current detection apparatuses which concern on a modification. It is a circuit diagram of maximum current detection device 1D concerning a modification. It is a circuit diagram of 2 A of maximum current detection apparatuses which concern on a modification. It is a circuit diagram of the maximum electric current detection apparatus 2B which concerns on a modification.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
<First Embodiment>
FIG. 1 shows a circuit diagram of a maximum current detection circuit 1A according to the first embodiment. The maximum current detection circuit 1A includes a current difference circuit 10A and a fifth P-channel MOS transistor P5.
The current difference circuit 10A outputs a first current input terminal Tin1 to which a first current I1 is supplied from the outside, a second current input terminal Tin2 to which a second current I2 is supplied from the outside, and an output current Iout to the outside. A current output terminal Tout and a power supply line La for supplying a high potential power supply are provided.

The current difference circuit 10A includes four P-channel MOS transistors P1 to P4.
In the first P-channel MOS transistor P1, the first current input terminal Tin1 and the drain are connected, the gate is connected to the drain, and the source is connected to the power supply line La.
The second P-channel MOS transistor P2 has a drain connected to the second current input terminal Tin2, a gate connected to the gate of the first P-channel MOS transistor P1, and a source connected to the power supply line La.
In the third P-channel MOS transistor P3, the second current input terminal Tin2 and the drain are connected, the gate is connected to the drain, and the source is connected to the power supply line La.
The fourth P-channel MOS transistor P4 has a gate connected to the gate of the third P-channel MOS transistor P3, a source connected to the power supply line La, and a current from the drain is supplied to the current output terminal Tout.

In addition to the above-described current difference circuit 10A, the maximum current detection circuit 1A has a gate connected to the gate of the first P-channel MOS transistor P1, a source connected to the power supply line La, and a current from the drain as a current output terminal. And a fifth P-channel MOS transistor P5 supplied to Tout.
As shown in FIG. 2, the direction of the second current I2 may be reversed by combining the current mirror circuit 11 and the current difference circuit 10A.

Next, the operation of the maximum current detection circuit 1A will be described. As shown in FIG. 1, the current flowing through the third P-channel MOS transistor P3 is I3.
First, when I2> I1, the third P-channel MOS transistor P3 is turned on. For this reason, I3 becomes I3 = I2-I1.
On the other hand, when I2 ≦ I1, the third P-channel MOS transistor P3 is turned off. For this reason, I3 becomes I3 = 0.

Here, the third P-channel MOS transistor P3 and the fourth P-channel MOS transistor P4 constitute a current mirror circuit. Therefore, the current I4 flowing through the fourth P-channel MOS transistor P4 is as follows.
When I2> I1 I4 = I2-I1
When I2 ≦ I1 I4 = 0
In other words, when considered as a single unit of the current difference circuit 10A excluding the fifth P-channel MOS transistor P5, when the second input current I2 is larger than the first input current I1, this circuit is “I2-I1”. Is output as the current I4, while the current I4 is set to zero when the second input current I2 is equal to or smaller than the first input current I1.

In the present embodiment, a maximum current detection circuit 1A is configured by adding a fifth P-channel MOS transistor P5 to the current difference circuit 10A. Since the gate of the fifth P-channel MOS transistor P5 is connected to the gate of the first P-channel MOS transistor P1, the current I5 flowing through the fifth P-channel MOS transistor P5 has the same magnitude as the first input current I1. Become. Here, since the output current Iout is Iout = I4 + I5, it is as follows.
When I2> I1 Iout = I4 + I5 = I2-I1 + I1 = I2
When I2 ≦ I1 Iout = I4 + I5 = I1

Thus, according to the maximum current detection circuit 1A, the larger one of the first input current I1 and the second input current I2 can be output as the output current Iout.
According to this configuration, since the current is converted into a voltage and not compared, the current-voltage conversion circuit can be made unnecessary. Also, no comparator is required for comparison. Furthermore, a switch circuit for selecting a current is not necessary. Moreover, switching noise at the time of switching is not superimposed on the output current.
Therefore, according to the maximum current detection circuit 1A, it is possible to output a maximum current in which noise superposition is suppressed while greatly simplifying the circuit configuration.

Second Embodiment
FIG. 3 shows a block diagram of a maximum current detection circuit 100A according to the second embodiment. The maximum current detection circuit 100A includes N (N is an integer of 2 or more) maximum current detection circuits 1A of the first embodiment, and includes N-1 current mirror circuits 20.
The maximum current detection circuit 1A is connected by a current mirror circuit 20. In the current mirror circuit 20, a current output terminal Tout and an input terminal of a certain maximum current detection circuit 1A are connected, and a first current input terminal Tin1 and an output terminal of another maximum current detection circuit 1A are connected. The output terminal may be connected to the second current input terminal Tin2 of the other maximum current detection circuit 1A. A specific configuration of the current mirror circuit 20 is, for example, the current mirror circuit 11 shown in FIG.

Thus, when the maximum current detection circuit 1A is cascade-connected using the current mirror circuit 20, the first stage maximum current counted from the left is the first current input terminal Tin1 of the second stage maximum current detection circuit 1A. Is compared with the current supplied to the second current input terminal Tin2, and the larger current is supplied to the first current input terminal Tin1 of the third stage maximum current detection circuit 1A. By repeating this comparison in sequence, the first current input terminal Tin1 of the N-th stage maximum current detection circuit 1A includes the current input from the first stage to the (N-1) th stage maximum current detection circuit 1A. The maximum current is supplied. For this reason, the maximum current among the currents input to the maximum current detection circuit 1A from the first stage to the N stage can be output from the output terminal Tout of the maximum current detection circuit 1A of the N stage.
As a result, the number of input currents to be compared can be increased. In this example, since N maximum current detection circuits 1A are used, the number of input currents to be compared is N + 1.

<Third Embodiment>
In the first and second embodiments described above, the current difference circuit 10A and the maximum current detection circuit 1A are configured by P-channel MOS transistors. In the third embodiment, an N-channel MOS transistor is used instead of the P-channel MOS transistor.
FIG. 4 shows a current difference circuit 10B and a maximum current detection circuit 1B configured by N-channel MOS transistors according to the third embodiment.

The current difference circuit 10B uses a power supply line Lb to which a low potential power supply Vss is supplied instead of the power supply line La, and first to fifth N-channel N transistors instead of the first to fourth P-channel MOS transistors P1 to P4. The difference from the current difference circuit 10A is that the channel MOS transistors N1 to N4 are used.
The maximum current detection circuit 1B uses a current difference circuit 10B instead of the current difference circuit 10A and uses a fifth N channel MOS transistor N5 instead of the fifth P channel MOS transistor P5. Different from the current detection circuit 1A.

The current difference circuit 10B includes four N channel MOS transistors N1 to N4.
The first N-channel MOS transistor N1 has a drain connected to the first current input terminal Tin1, a gate connected to the drain, and a source connected to the power supply line Lb. Second P-channel MOS transistor N2 has a drain connected to second current input terminal Tin2, a gate connected to the gate of first N-channel MOS transistor N1, and a source connected to power supply line Lb. In the third N-channel MOS transistor N3, the second current input terminal Tin2 and the drain are connected, the gate is connected to the drain, and the source is connected to the power supply line Lb. In the fourth N-channel MOS transistor N4, the gate is connected to the gate of the third N-channel MOS transistor N3, the source is connected to the power supply line Lb, and the current from the drain is supplied to the current output terminal Tout.

  In addition to the current difference circuit 10B described above, the maximum current detection circuit 1B has a gate connected to the gate of the first N-channel MOS transistor N1, a source connected to the power supply line Lb, and a current from the drain as a current output terminal. A fifth N-channel MOS transistor N5 supplied to Tout is provided.

Next, the operation of the maximum current detection circuit 1B will be described.
First, when I2> I1, the third N-channel MOS transistor N3 is turned on. For this reason, I3 becomes I3 = I2-I1.
On the other hand, when I2 ≦ I1, the third N-channel MOS transistor N3 is turned off. For this reason, I3 becomes I3 = 0.

Here, the third N-channel MOS transistor N3 and the fourth N-channel MOS transistor N4 constitute a current mirror circuit. Therefore, the current I4 flowing through the fourth N-channel MOS transistor N4 is as follows.
When I2> I1 I4 = I2-I1
When I2 ≦ I1 I4 = 0
In other words, when considered as a single unit of the current difference circuit 10B excluding the fifth N-channel MOS transistor N5, when the second input current I2 is larger than the first input current I1, this circuit is “I2-I1”. Is output as the current I4, while the current I4 is set to zero when the second input current I2 is equal to or smaller than the first input current I1.

In the present embodiment, a maximum current detection circuit 1B is configured by adding a fifth N-channel MOS transistor N5 to the current difference circuit 10B. Since the gate of fifth N-channel MOS transistor N5 is connected to the gate of first N-channel MOS transistor N1, current I5 flowing through fifth N-channel MOS transistor N5 has the same magnitude as first input current I1. Become. Here, since the output current Iout is Iout = I4 + I5, it is as follows.
When I2> I1 Iout = I4 + I5 = I2-I1 + I1 = I2
When I2 ≦ I1 Iout = I4 + I5 = I1

Thus, according to the maximum current detection circuit 1B, the larger one of the first input current I1 and the second input current I2 can be output as the output current Iout.
According to this configuration, since the current is converted into a voltage and not compared, the current-voltage conversion circuit can be made unnecessary. Also, no comparator is required for comparison. Furthermore, a switch circuit for selecting a current is not necessary. Moreover, switching noise at the time of switching is not superimposed on the output current. Therefore, according to the maximum current detection circuit 1B, it is possible to output the maximum current with suppressed noise superposition while greatly simplifying the circuit configuration.
Note that, similarly to the second embodiment, the maximum current detection circuit 100B may be configured by using N maximum current detection circuits 1B of the third embodiment. FIG. 5 shows the configuration of the maximum current detection circuit 100B.
In the maximum current detection circuit 100 </ b> B, N maximum current detection circuits 1 </ b> B are cascade-connected using N−1 current mirror circuits 30. Thereby, the number of input currents can be expanded to N + 1.

<Modification>
The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible.

(1) In the first and second embodiments described above, a maximum current detection circuit 1C shown in FIG. 6 may be used instead of the maximum current detection circuit 1A. The maximum current detection circuit 1C uses a current difference circuit 10C instead of the current difference circuit 10A, and a seventh P-channel MOS transistor P7 is provided between the fifth P-channel MOS transistor P5 and the current output terminal Tout. It is different in point. Furthermore, the current difference circuit 10C is configured in the same manner as the current difference circuit 10A except that a sixth P-channel MOS transistor P6 is provided between the fourth P-channel MOS transistor P4 and the current output terminal Tout. ing.
The fixed potential Vref1 is supplied to the gates of the sixth and seventh P-channel MOS transistors P6 and P7. By using the cascode connection in this way, the influence of the mirror effect can be reduced.

In the third embodiment described above, the maximum current detection circuit 1D shown in FIG. 7 may be used instead of the maximum current detection circuit 1B. The maximum current detection circuit 1D uses a current difference circuit 10D instead of the current difference circuit 10B, and a seventh N-channel MOS transistor N7 is provided between the fifth N-channel MOS transistor N5 and the current output terminal Tout. It is different in point. Furthermore, the current difference circuit 10D is configured in the same manner as the current difference circuit 10B except that a sixth N-channel MOS transistor N6 is provided between the fourth N-channel MOS transistor N4 and the current output terminal Tout. ing.
The fixed potential Vref2 is supplied to the gates of the sixth and seventh P-channel MOS transistors N6 and N7. By using the cascode connection in this way, the influence of the mirror effect can be reduced.

(2) In the first embodiment, the second embodiment, and the modification described above, the differential current circuits 10A and 10C and the maximum current detection circuits 1A and 1C are configured using P-channel MOS transistors. However, the present invention is not limited to this, and a PNP transistor may be used instead of the P-channel MOS transistor.
For example, the maximum current detection circuit 1A can be replaced with the maximum current detection circuit 2A shown in FIG. In the current difference circuit 20A of the maximum current detection circuit 2A, the first PNP transistor Trp1 has a collector connected to the first current input terminal Tin1, a base connected to the collector, and an emitter connected to the power supply line La. The second PNP transistor Trp2 has a collector connected to the second current input terminal Tin2, a base connected to the base of the first PNP transistor Trp1, and an emitter connected to the power supply line La. The third PNP transistor Trp3 has a collector connected to the second current input terminal Tin2, a base connected to the collector, and an emitter connected to the power supply line La. The base of the fourth PNP transistor Trp4 is connected to the base of the third PNP transistor Trp3, the emitter is connected to the power supply line La, and the current from the collector is supplied to the current output terminal Tout.
Further, the maximum current detection circuit 2A has a base connected to the base of the first PNP transistor Trp1, an emitter connected to the power supply line La, and a fifth PNP transistor in which the current from the collector is supplied to the current output terminal Tout. Trp5.

In the third embodiment and the modification described above, the differential current circuits 10B and 10D and the maximum current detection circuits 1B and 1D are configured using N-channel MOS transistors, but the present invention is limited to this. Instead of an N channel MOS transistor, an NPN transistor may be used instead.
For example, the maximum current detection circuit 1B can be replaced with the maximum current detection circuit 2B shown in FIG. In the current difference circuit 20B of the maximum current detection circuit 2B, the first NPN transistor Trn1 has a first current input terminal Tin1 connected to the collector, a base connected to the collector, and an emitter connected to the power supply line La. The second NPN transistor Trn2 has a collector connected to the second current input terminal Tin2, a base connected to the base of the first NPN transistor Trn1, and an emitter connected to the power supply line La. The third NPN transistor Trn3 has a second current input terminal Tin2 and a collector connected, a base connected to the collector, and an emitter connected to the power supply line La. The base of the fourth NPN transistor Trn4 is connected to the base of the third NPN transistor Trn3, the emitter is connected to the power supply line La, and the current from the collector is supplied to the current output terminal Tout.
Further, the maximum current detection circuit 2A has a base connected to the base of the first NPN transistor Trn1, an emitter connected to the power supply line La, and a fifth NPN transistor in which the current from the collector is supplied to the current output terminal Tout. Trn5.
In this way, the MOS transistor may be replaced with a bipolar transistor.

  The present invention can be used for a circuit that determines the magnitude of current and outputs the maximum current.

10A, 10B, 10C, 10D ... current difference circuit, 1A, 1B, 1C, 1D, 100A, 100B ... maximum current detection circuit, P1-P7 ... P-channel MOS transistor, N1-N7 ... N-channel MOS transistor, Trp1-Trp5 ... PNP transistors, Trn1 to Trn5... NPN transistors, La and Lb... Power line, Tin1... First current input terminal, Tin2.

Claims (6)

A first current input terminal, a second current input terminal, a current output terminal, a power line,
A first MOS transistor having a drain connected to the first current input terminal, a gate connected to the drain, and a source connected to the power line;
A second MOS transistor having a drain connected to the second current input terminal, a gate connected to the gate of the first MOS transistor, and a source connected to the power line;
A third MOS transistor in which the second current input terminal and the drain are connected, the gate is connected to the drain, and the source is connected to the power line;
A fourth MOS transistor having a gate connected to the gate of the third MOS transistor, a source connected to the power supply line, and a current from the drain supplied to the current output terminal;
A current difference circuit. A current difference circuit according to claim 1;
A fifth MOS transistor having a gate connected to the gate of the first MOS transistor, a source connected to the power supply line, and a current from the drain supplied to the current output terminal;
A maximum current detection circuit. A sixth MOS transistor is provided between the current output terminal and the fourth MOS transistor;
A seventh MOS transistor is provided between the current output terminal and the fifth MOS transistor;
The maximum current detection circuit according to claim 2, wherein a fixed potential is supplied to gates of the sixth MOS transistor and the seventh MOS transistor. A first current input terminal, a second current input terminal, a current output terminal, a power line,
A first bipolar transistor having a first current input terminal connected to a collector, a base connected to the collector, and an emitter connected to the power line;
A second bipolar transistor having a second current input terminal connected to the collector, a base connected to the base of the first bipolar transistor, and an emitter connected to the power line;
A third bipolar transistor having a second current input terminal and a collector connected, a base connected to the collector, and an emitter connected to the power line;
A fourth bipolar transistor having a base connected to the base of the third bipolar transistor, an emitter connected to the power supply line, and a current from a collector supplied to the current output terminal;
A current difference circuit. A current difference circuit according to claim 4;
A fifth bipolar transistor having a base connected to the base of the first bipolar transistor, an emitter connected to the power supply line, and a current from a collector supplied to the current output terminal;
A maximum current detection circuit. N (where N is an integer of 2 or more) maximum current detection circuits according to any one of claims 2, 3, and 5,
N maximum current detection circuits are cascade-connected through a current mirror circuit,
In the current mirror circuit, a current output terminal and an input terminal of a certain maximum current detection circuit are connected, and one of the first current input terminal or the second current input terminal of another maximum current detection circuit and an output terminal are connected.
A maximum current detection circuit.

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