JPH0423518A - Digital/analog conversion circuit - Google Patents

Abstract

PURPOSE:To input plural data simultaneously in a parallel processing analog arithmetic unit by receiving a digital data by each digital/analog(D/A) converting part in timing shifted with each other and sample-holding an analog data from the each D/A converting part in a prescribed sample-hold cycle. CONSTITUTION:A D/A conversion circuit 13 is equipped with first - third D/A converting parts 15a-15c, first - third sample and hold(S/H) parts 16a-16c and first - third buffer memories 17a-17c. The first - third D/A conversion parts 15a-15c receive the digital data in the different timing with each other and the first - third S/H parts 16a-16c sample and hold the first - third analog data in the prescribed sample-hold cycle. Thus, it is possible to input the plural sample-hold data simultaneously in the parallel processing analog arithmetic unit.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a digital-to-analog conversion circuit, and in particular,
The present invention relates to a digital-to-analog conversion circuit used when connecting a digital arithmetic device that processes data sequentially and an analog arithmetic device that processes data in parallel.

(Prior Art) Generally, when a sequential processing arithmetic device and a parallel processing arithmetic device are connected, each input to the parallel processing arithmetic device needs to be applied to the parallel processing arithmetic device at the same time. In particular, in order to provide digital data from a sequential processing digital arithmetic device to a parallel processing analog arithmetic device, a digital-to-analog conversion circuit that takes the above-mentioned points into consideration is required.

Incidentally, in recent years, control based on fuzzy theory has been adopted in injection molding machines and the like. In a control device using fuzzy theory, an analog parallel calculation method is adopted in order to ensure signal continuity and increase calculation speed. Further, all input values such as command values in a control device using fuzzy theory are set using digital values. For this reason, sequential processing digital arithmetic devices are used.

(Problem to be Solved by the Invention) By the way, when connecting a control device using fuzzy theory to a digital arithmetic device for sequential processing, it is necessary to use a digital-to-analog conversion circuit that simply converts digital data into multiple analog data. Therefore, there is a problem in that it is not possible to simultaneously provide multiple analog data to a control device using fuzzy theory.

One object of the present invention is to provide a digital-to-analog conversion circuit that can simultaneously provide a plurality of analog data to a control device using fuzzy theory.

(Means for Solving the Problems) In the present invention, a digital arithmetic device having one output port for sequentially processing data and outputting the digital data, and a first to Nth (N is an integer of 2 or more) It is used when connecting an analog computing device (e.g., a control device using fuzzy theory) that has an input port and receives input from the first to Nth ports (for example, a control device using fuzzy theory), and corresponds to the number of input ports. A first output terminal is connected to the output port and receives the digital data at different timings.
first to Nth digital-to-analog converters for converting into the first to Nth analog data; a plurality of first to Nth sample and hold sections that sample and hold analog data at a predetermined sample and hold period and output first to Nth sample and hold data as the first to Nth data; A digital-to-analog conversion circuit is obtained.

At this time, the first to Nth digital-to-analog conversion circuits are configured to convert data at different timings and at predetermined intervals when the first to Nth analog data is held in the first to Nth sample and hold sections. It is desirable to receive digital data at

(Operation) In the present invention, digital data from the digital arithmetic device is received at mutually different timings by the first to Nth digital-to-analog converters, and the digital data is received by the first to Nth digital-analog converters, respectively.
output as analog data. This reception timing is set during the hold period in the first to Nth sample and hold sections. The first to Nth analog data are sampled and held at a predetermined sample and hold period in the first to Nth sample and hold sections, respectively, and output as first to Nth sample and hold data. The first to Nth sample and hold data are given to a parallel processing analog arithmetic unit.

In this way, the first to Nth digital/analog sections receive digital data at mutually different timings,
Since the first to Nth sample and hold sections sample and hold the first to Nth analog data, it is possible to simultaneously input the first to Nth sample and hold data to the parallel processing analog processing device.

(Example) The present invention will be explained below with reference to Examples.

Referring to FIG. 1, a digital arithmetic unit 11 is connected to the input side of a digital-to-analog conversion circuit 13 via a digital bus 12, and the output side of the digital-to-analog conversion circuit 13 is connected to an analog type parallel fuzzy arithmetic unit 14. It is connected.

The digital arithmetic unit 11 has one output photo 11a.
On the other hand, a parallel fuzzy operation unit 1
4 has the first to third input capo-I.]-4a to 14c.
is provided.

Digital-to-analog conversion circuit] 3 is the first to third digital-to-analog (D/A) conversion sections 15a to 15;
C1 first to third sample hold (S/H) section 1
6a to 16c1 and first to third buffer memories 17a to 1.7c.

Also with reference to FIG. 2, the first to third D/A converters 15a
First to fourth control lines 18a to 18c are connected to 15c.
The first to third data write clocks are applied from the digital arithmetic unit 11 at mutually different timings and at predetermined cycles. Further, the first to third S/H sections 16a to 16 are connected via the fourth control line 18d.
A sample and hold clock is provided for c. As shown in FIG. 2, the first to third data write clocks are at high level while the sample hold clock is at low level.

Here, with reference to FIGS. 1 to 3, in FIG. The output of changes depending on the value of digital data. In this case,
At the rise of the first pulse, it changes as shown by the broken line. Moreover, it changes as shown by the broken line at the rising edge of the second pulse of the first data write clock.

Similarly, at the rise of the second data write clock, the output of the second D/A converter 15b changes as shown by the broken line, and at the rise of the third data write clock, the output of the third D/A converter 15b changes. The output of 15c changes as shown by the broken line. In this way, the first to third D/A converters 1
The first to third analog pigs are outputted from 5a to 15c, respectively, and the first to third S/H sections 16a to 16
given to c.

The first to third S/H units 16a to 16c repeatedly sample and hold the first to third analog data using sample and hold clockers, respectively. In other words, the third
As shown by solid lines in the figure, the first to third analog data are sampled at the rising edge of the sample bold clock, and this sampled state is held until the next rising edge of the sample and hold clock. In this way,
The first to third S/H sections 16a to 16c output first to third sample and hold data, respectively. These first to third sample-and-hold data have the same rising and falling parts as shown by solid lines in FIG.

The first to third sample hold data are
Once stored in the first to third buffer memories 17a to 17c, the first to third parallel fuzzy calculation units 14
is applied to input ports 14a to 14c of.

In the above embodiment, N=3 was explained, but N=2,
And it can be carried out in the same manner also in the case of N-4 or more.

(Effects of the Invention) As explained above, in the present invention, each D/A converter receives digital data at different timings, and each D/A converter receives digital data at different timings.
Since the analog data from the /A converter is sampled and held at a predetermined sample and hold period, a plurality of data can be simultaneously input to the parallel processing analog processing device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the digital-to-analog conversion circuit according to the present invention together with a digital arithmetic unit and a parallel fuzzy arithmetic unit, and FIG. 2 is a diagram showing the timing of a sample hold clock and first to third data write clocks. 3 are diagrams showing the outputs of the first to third digital-to-analog conversion sections and the first to third sample and hold sections. 1]...Digital arithmetic unit, 12...Digital bus, ]3...Digital-to-analog conversion circuit,
14...Parallel fuzzy operation unit. Procedure Japanese official book (method) August 1990 S? 7th day

Claims (2)

[Claims] 1. A digital arithmetic device that processes data sequentially and has one output port for outputting the digital data, and has first to Nth input ports (N is an integer of 2 or more) and outputs the first to Nth data. The first to Nth ports are used when connecting analog processing devices that receive input data and perform parallel processing, are provided in correspondence with the number of input ports, are connected to the output ports, and receive the digital data at different timings. 1st to Nth data to be converted into analog data of
a digital-to-analog converter and a digital-to-analog converter for sampling and holding the first to Nth analog data at a predetermined sample and hold period, respectively. 1st
A digital-to-analog conversion circuit comprising: a plurality of first to Nth sample and hold sections that output sample and hold data of the first to Nth data as the first to Nth data. 2. In the digital-to-analog conversion circuit as set forth in claim 1, the first to N-th digital-to-analog conversion circuits include the first to the Nth sample-hold sections. A digital-to-analog converter circuit, characterized in that when the Nth analog data is held, the digital data is received at different timings and at a predetermined cycle.