JPS61122741A - Data acquisition system - Google Patents

Abstract

PURPOSE:To increase sampling frequency by connecting plural data acqusition systems in parallel and A/D converting sampled data with the delay of sampling time. CONSTITUTION:Sampling and holding circuits 11, 12 are connected to an analog input signal SA in parallel and a timing control circuit 10 outputs sampling and holding command signals SC1, SC2 alternately. During the period that an analog value SB1 held by the signal SC1 is being converted by an A/D converter 21, the circuit 12 holds the succeeding analog value SB2 by the signal SC2. Digital values alternately outputted from the A/D converters 21, 22 are alternately connected to an output bus by a digital multiplexer 30 and outputted at a sampling speed apparatus twice the actual speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data acquisition system for converting analog signals into digital processing.

[Conventional technology]

FIG. 4 is a block diagram of a conventional data acquisition system, and FIG. 5 is a timing chart thereof.

The timing control circuit 3 converts the analog input signal S1 into an A/D
A hold signal Sc is output to the sample & hold circuit 1 to hold it at a constant value during conversion. Further, the timing control circuit 3 outputs an A/D conversion start signal S11 to the A/D converter 2 after one aperture time (settling time) Tc has elapsed to the sample & hold circuit 1. A/D
The converter 2 converts the analog input signal SA into a digital signal, while converting the A/D conversion status signal S1. : output and
Notify the timing control circuit 3 that A/D conversion is currently in progress (conversion time T1). Timing control circuit 3 is A
After waiting for the completion of the conversion by the /D converter 2, the sample signal Sc is output, and the sample & hold circuit 1 is put into the sample state.

After the acquisition time Ts (time until the output voltage settles down) of the sample & hold circuit 1, the timing control circuit 3 outputs the A/D start signal S1. The operation of outputting 0 or more is repeated, and the analog input signals S and A are converted into digital signals.

However, in order to convert the analog input signal SA at one point into a digital signal, as mentioned above, at least (
Ts+Tc+TA) is required, this time is determined by the circuit, and the sample interval cannot be made shorter than this value.

[Problem that the invention seeks to solve]

In this way, in conventional data acquisition systems, the settling time of the sample and hold circuit, A
It is difficult to perform data acquisition at a higher speed than the time interval depending on circuit elements such as the conversion time of a /D converter.

However, analog signal frequencies handled in signal processing tend to be higher frequencies, and it is necessary to realize a high-speed data acquisition system.

Therefore, one object of the present invention is to have a simple configuration.

An object of the present invention is to provide a data acquisition system that can perform data acquisition at high speed.

[Means for solving problems]

According to the present invention, a plurality of data acquisition systems are connected in parallel, and sampling times are shifted to perform A/D conversion, thereby apparently shortening the sampling frequency.

That is, the data acquisition system of the present invention:
n (≧2) sets of sample & hold circuits and A/D converters connected in parallel to an analog signal input terminal, and a plurality of A/D converters.
A multiplexer that selects and outputs one of the outputs of the A/D converter, a sample signal shifted by a predetermined time to each set of A/D converters in the sample & hold circuit, an A/D conversion start command signal, and a multiplexer. A timing control circuit is provided for outputting control signals to the respective terminals.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a data acquisition system according to the present invention, and FIG. 2 is a time chart of signals of various parts in FIG.

The data acquisition system of this embodiment is as follows.

Channel l sample and hold circuit 11 and A/
It includes a D converter 21, a sample & hold circuit 12 of channel 2, an A/D converter 22, and two sets of a sample & hold circuit and an A/D converter. The digital multiplexer 30 selects and outputs one of the outputs of these channels 1.2. The timing control circuit/D is (dc+
The sample and hold command signal sG, , So2. After the aperture time Tc has elapsed, the A/D conversion start command signal SII+
l5I)2 is output to each channel 1.2, and as a result, an A/D conversion status output signal S, boat is input from the A/D conversion $21.22 of each channel 1.2, and the timing control circuit /D is during the conversion time TA,
Channel control signal S,,S that is “invalid” and “valid” from the start of sampling to the next A/mouth conversion start command signal
2 to the digital multiplexer 30, and as a result, the A/D converted values of the sample & hold outputs S, S, 2 are output from the digital signal multiplexer 30 as (Tc+T,
, are output alternately at intervals of 1/2 (7). In other words, in this embodiment, a conventional data acquisition system (
This means that the sampling frequency for the analog input signal S1 has been doubled compared to FIG. 4).

Generally, if n stages of data acquisition systems are connected in parallel, the sample interval can be shortened to l/n.
It is possible to have performance n times higher in sampling frequency than in one stage.

In addition, complex timing control is performed using a timing control circuit/
D can be realized by using a high-speed microprocessor.

FIG. 3 is a diagram showing a conversion output waveform of an input analog signal by the data acquisition system of the present invention in comparison with a conventional example.

The more the number of stages N is increased compared to the conventional (N=1) (N=2.N
= 3), it can be seen that the input analog signal is closer to the input analog signal.

Note that the sample interval does not have to be l/n.

However, in the case of current flow, there is no way to process wasted conversion time, so when processing data after accumulating data such as FFT or matrix calculation.

It becomes more effective.

〔Effect of the invention〕

As explained above, in the present invention, multiple sets of sample and hold circuits and A/D converters are provided, and the sampling frequencies of these circuits are shifted, so that it is possible to easily improve the sampling frequency and improve signal processing. Data input for FFT and matrix calculations can be processed at high speed.

The present invention can realize high speed and high precision by connecting commercially available general-purpose high precision and low speed A/ports in parallel.

Commercially available high-precision types have a resolution of 12 bits and conversion time.
1.5g, s (Burr-Brown) is the highest speed.

It seems to be effective even in two stages.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the data acquisition system according to the present invention, Fig. 2 is a time chart of the signals of each part in Fig. 1, and Fig. 3 is a comparison of the conversion output for the input analog signal according to the present invention with the conventional example. FIG. 4 is a block diagram of a conventional data acquisition system, and FIG. 5 is a time chart of each part of FIG. 4. /D: Timing control circuit 11.12: Sample color hole 1 circuit 21, 22: A/D converter 30: Digital multiplexer S7,: Analog input signal 5 ports, sB2: Sample & hold output s,,
, so2: Sample & bold command signal S, , , S: A/D conversion start command signal s, s, □: A/D conversion status output signal E. S, , S2: Channel control signal Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] In a data acquisition system that converts an analog signal into a digital signal, a sample &
n (≧2) sets of hold circuits and A/D converters, a multiplexer that selects and outputs one of the outputs of the plurality of A/D converters, and an A/D converter of the sample and hold circuit. Sample signals shifted by a predetermined time for each set, A/D
A data acquisition system comprising a timing control circuit that outputs a conversion command signal and a control signal to the multiplexer.