JPH05152955A - Data processor - Google Patents

Abstract

PURPOSE:To digitize an analog signal inputted for a prescribed period with a low sampling frequency, to apply serial conversion to obtained data and to transfer the result in real time. CONSTITUTION:A multiplexer 11 selects data obtained by each sampling clock and the output timing is matched with output data of the latches 3A-3C by shift register 12 and whether the data from the latches 3A-3C or the data from the shift register 12 are selectively sent by the multiplexers 13A-13C and the result is serially transferred from a shift register 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for converting an analog signal such as a reception signal of a radar into a digital signal by using a low sampling frequency and then serially transferring the digital signal.

[0002]

2. Description of the Related Art A conventional data processor of this type uses an N-phase clock having an I / N (N is a natural number) sampling frequency necessary to quantize an analog input signal, The configuration is such that the timing is changed for each of the reception cycles to perform analog-digital conversion, all sampling is completed after N cycles, and then the acquired data is serially transferred.

FIG. 2 is a block diagram of the above-mentioned conventional data processing apparatus, in which N = 3. A sampling clock obtained by dividing a clock having a sampling frequency necessary for quantization into three and three phases, and acquired data are set to an A series, a B series, and a C series in the order of phase. As shown in FIG. 3, the first received signal is quantized by the A-sequence clock and the data is stored in the random access memory (RAM) 2A. In the quantization of the next reception cycle, the B series clock whose phase is delayed by one cycle of the sampling clock having the originally required frequency from the A series clock is used and similarly stored in the RAM 2B. In this way C
When the storage of the data up to the series is completed, the data of the A series, B series, and C series are simultaneously stored in the RAMs 2A, 2B, and 2C.
After being read from the latches 3A, 3B, 3C,
The shift register 4 performs serial conversion and transfers.

[0004]

In this conventional data processing apparatus, since data transfer is performed only once every N cycles, there is a drawback that transfer delay becomes large and real-time transfer cannot be performed.

[0005]

According to the data processing apparatus of the present invention, an analog signal input at a constant cycle is sequentially digitized at a low sampling frequency of a plurality of series, and sampling data of one series is cyclically selected. A first multiplexer, a first shift register that matches the timing of the selection data of the first multiplexer and the timing of the data of another series, and the transmission data of the first shift register or the data of another series A second multiplexer for selecting a plurality of streams and a data select controller for controlling the selecting operation of the first and second multiplexers.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 4 is a signal timing diagram illustrating the operation of this embodiment. Analog-to-digital (A / D) converter 1
Performs A / D conversion of the input reception signal using sampling clocks of three series of A, B, and C. The digital data obtained by the A-series clock is written to the RAM 2A (W), and the data obtained by the B-series clock is written in the RAM 2B in the next cycle. In the next cycle, the data obtained by the C series clock is RAM
At the same time as writing to 2C, the C-sequence data is selectively transmitted by the control signal output from the data select controller 14 by the multiplexer 11 of the three-choice format (W /
D). In parallel with this, the data is simultaneously read from the RAMs 2A and 2B (R), and the three series of data are latched by the latch 3A.
And 3B and the shift register 12 to match the output timing, and then the multiplexer 1 of the two-choice format, respectively.
Input to 3A, 13B, 13C. The data select controller 14 gives a control signal to the multiplexers 13A to 13C so that the multiplexers 13A and 13B receive the data of the latches 3A and 3B and the multiplexer 13A.
The data from the shift register 12 is selectively transmitted from C. These three series of data are simultaneously loaded into the shift register 4 for serial conversion, and are A series → B series → C.
Serial transfer is performed in the order of series (T). Hereinafter, as illustrated in FIG. 4, if the series passing through the shift register 12 is circulated in the order of C series → A series → B series, it is possible to transfer data continuously in real time.

[0008]

As described above, according to the present invention, a plurality of series of data obtained by each sampling clock are cyclically selected, and the timing of this selected output and the data of another series is adjusted. Serial transfer allows analog signals to be
It becomes possible to perform real-time transfer after D conversion.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional device.

3 is an operation timing chart of the apparatus of FIG.

4 is an operation timing chart of the embodiment of FIG.

[Explanation of symbols]

 1 A / D converter 2A to 2C Random access memory (RAM) 3A to 3C Latch 4,12 Shift register 11, 13A to 13C Multiplexer 14 Data select controller

Claims (1)

[Claims] 1. A first multiplexer for sequentially digitizing an analog signal input at a constant cycle by a plurality of series of low sampling frequencies, and cyclically selecting sampling data by one of the series, and a first multiplexer of the first multiplexer. A first shift register that matches the timing of the selected data with the timing of other series of data; and a second multiplexer for a plurality of series that selects either the data sent from this first shift register or the data of another series And a data select controller for controlling selection operations of the first and second multiplexers.