JPH05145418A - Low power type data transfer device - Google Patents

Abstract

PURPOSE:To realize the function of digitizing an input analog signal at a low sampling frequency and of serially transferring digital data with a low power consumption. CONSTITUTION:The device is provided with an A/D converter 1 sampling an analog input signal with a polyphase sampling clock respectively and converting the sampled signal into a digital signal, 1st shift registers 2, 12, 22 with a bit number of the digital signal converting the bit series of the digital signal into a parallel signal, buffer memories 4A, 4B, 4C by a phase number storing tentatively parallel output data with each phase of the polyphase clock from the 1st shift registers 2, 12, 22 and serial transfer means 5A-5C, 6, 7 converting serially parallel read data from the buffer memories 4A, 4B, 4C into serial data, multiplexing each bit, converting all the bits serially and transferring the serially converted data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power type data transfer system for digitally processing an analog signal and serially transferring it.

[0002]

2. Description of the Related Art A conventional data transfer device of this type is an EC
The L output type A / D converter is used to convert an analog input signal into a digital signal, the obtained digital data is once written into a bipolar RAM, the data is read, serially converted and transferred.

[0003]

In this conventional data transfer apparatus, since the sampling frequency required for quantization is high (for example, several tens of megahertz or more), an ACL output type with high power consumption is used as an A / D converter. However, the bipolar type RAM is also used as a buffer for temporarily storing the obtained digital data, and the power consumption of the entire device is considerably large.

[0004]

A data transfer apparatus of the present invention comprises an analog-digital converter for sampling an analog input signal with a multi-phase sampling clock and converting it into a digital signal, and an analog-digital converter for converting each bit of the digital signal. A first shift register for the number of bits for parallel-converting the sequence, and a buffer memory for the number of phases for temporarily storing the parallel output data of the first shift register for each phase of the multiphase clock, The parallel read data from the buffer memory is serial-converted, each bit is multiplexed, and serial conversion is performed for all the bits to be serially converted and transferred.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The quantization bit number 1 of the converted digital signal in the analog-to-digital (A / D) converter 1 of the present embodiment is a sampling clock of three series (generally k series) of analog input signals A, B and C. Using A / D
Convert. The obtained 3-bit digital data is thereafter processed individually for each bit in the same manner until it is loaded into the shift register 7 for data transfer. In Figure 1,
Only the processing path for bit 1 (MSB) is shown. The data obtained by the A-series sampling clock is input to the shift register 2 and converted into an 1-bit (l is a natural number) parallel signal, which is then latched by the latch 3 and is a 1-word 1-bit random access memory. (RAM) 4A is written. Next, the data A / D converted by the B series clock is written in the RAM 4B, and further written in the data RAM 4C A / D converted by the C series clock. The load speed of each series data to the transfer shift register 7 is 1 of the final transfer speed.
Since it is / 9 (generally 1 / kl), it is possible to reproduce the MSB data by supplying the data transfer clock and the load pulse once per 1 clock to the shift registers 5A to 5C. At this time, the addresses of the RAMs 4A to 4C are incremented in synchronization with the load pulse (see FIG. 3). The data serially converted by the shift registers 5A to 5C at the same time is input to the multiplexer 6, and the data in the shift register 5A is first selected.
At the same time, the bit 2 data is transmitted by the multiplexer 16 and the bit 3 data is transmitted by the multiplexer 26.
A series data is selected and loaded into the transfer shift register 7 together with bit 1 data. These 3-bit data are serially converted and transferred by the data transfer clock.

When the transfer of the A series data is completed, the B
If the multiplexers 6, 16 and 26 are selected in sequence in the order of sequence → C sequence → A sequence, desired data transfer can be performed.

[0008]

As described above, according to the present invention, the A / D conversion can be performed at the sampling frequency of 1 / k in the conventional device, and the memory operation can be performed at the cycle time of 1 / kl. Since the A / D converter used has a TTL output format and the memory can use a MOS type RAM, the overall power consumption of the device is about 5 times that of the conventional device.
It can be reduced by 0%.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a signal timing diagram according to the embodiment of the invention.

FIG. 3 is a signal timing diagram according to the embodiment of the invention.

FIG. 4 is a signal timing diagram according to the embodiment of the invention.

[Explanation of symbols]

 1 analog / digital (A / D) converter 2, 12, 22, 5A to 5C, 7 shift register 3 latch 4A to 4C RAM 6, 16, 26 multiplexer

Claims (1)

[Claims] 1. An analog-to-digital converter for sampling an analog input signal with a multi-phase sampling clock and converting it into a digital signal, and a first number corresponding to the number of bits for parallel-converting each bit sequence of the digital signal. Shift register, a buffer memory for storing the parallel output data of the first shift register for each phase of the multi-phase clock, and parallel read data from the buffer memory for serial conversion. And a serial transfer means for multiplexing each bit and serial-converting and transferring over all the bits.