JPH10123179A - Extended memory circuit system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an extended memory circuit system by which an extended memory board can be used so as to be divided into a plurality of data buses by a method wherein a plurality of memories which are mounted on the extended memory board are changed over so as to correspond to the plurality of data buses. SOLUTION: Data buses and address buses at a memory 5 and a memory 6 can be changed over to standard memory buses D, E, D2, E2 by using tristate buffers 51 to 58. The tristate buffers 51 to 58 are controlled by a control circuit 31, and their contents are instructed by an operating device 32. For example, when a memory 5 is used as the extended memory of a memory 3 and when a memory 6 is used as the extended memory of a memory 23, tristate buffers 52, 54, 55, 57 are set at a high impedance, and tristate buffers 53, 54, 56, 58 are enabled. A bus D is selected as a bus DX1, a bus E is selected as a bus EX1, a bus D2 is selected as a bus DX2, and a bus E2 is selected as a bus EX2 so as to achieve a purpose. In this manner, a storage capacity can be extended, and it can be used so as to be divided into many systems.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system, and more particularly to an improvement in a memory expansion method of a waveform storage device such as a digital oscilloscope.

[0002]

2. Description of the Related Art FIG. 2 shows a prior art example.

FIG. 1 is a block diagram showing a case where the memory in a standard waveform storage device is expanded by adding an optional additional memory board or the like.

[0004] 1 is an AD converter that converts an input signal A into a digital value at the timing of a sampling clock B,
Output to C. 2 and latches it and outputs D
Then, the data is stored in the address output from the address generation circuit 4 of the memory 3.

[0005] Reference numeral 10 denotes an extended memory board on which 5 and 6 memories are mounted, and a data bus D and an address bus E are connected. Here, the chip select signal of each memory is omitted, but it can be easily understood if the upper address of the address bus E performs its function. Conventionally, the memory capacity is expanded by connecting an address bus and a data bus of a standard memory.

[0006]

The above-mentioned prior art includes the following:
There is a drawback that the extension memory is limited to one data bus and cannot cope with another data bus.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a bus memory in which a plurality of memories mounted on an extended memory board can cope with a plurality of data buses instead of one data bus. The switching can be performed.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows a conventional example of FIG. 2 in which a plurality of AD converters are provided, that is, an input to an extended memory is made into two channels.

Reference numeral 100 denotes an extended memory circuit of the present invention.
The data buses and the address buses of the memories 5 and 6 are switched between the two standard memory buses D and E and D2 and E2 by the tri-state buffers 51 to 58. The tri-state buffer is controlled by the control circuit 31, and an instruction of the control content is issued from the operation unit 32.

For example, to make the memory 5 an extended memory of the memory 3 and the memory 6 an extended memory of the memory 23,
The tri-state buffers 52, 54, 55, and 57 are set to high impedance, and the tri-state buffers 53, 5
By enabling 4, 56 and 58, the D bus is selected as the DX1 bus, the E bus is selected as the EX1 bus, the D2 bus is selected as the DX2 bus, and the E2 bus is selected as the EX2 bus. Can be realized.

In order to make the memories 5 and 6 both extended memories of the memory 3, the tri-state buffers 52 and 5 are required.
The bus D is selected as the bus DX1 by setting the impedances of 4, 56 and 58 to high impedance and enabling the tri-state buffers 51, 53, 55 and 57, and the bus EX1
, The bus D is selected as the bus DX2, and the bus E is selected as the bus EX2.
Further, it is also possible to use both the memories 5 and 6 as extension memories of the memory 23.

In this example, when different signals are input to inputs A and A2 and the same sampling clock is input to B and B1, waveforms of two channels can be stored. At this time, the memory can be expanded for only one channel, or both channels can be expanded.

The same signal is input to inputs A and A2,
When sampling clocks having phases opposite to each other are input to B and B1, the waveform can be stored at a sampling rate twice that of the conventional example. At this time, memories 5 and 6 can operate at different timings. 23 can be expanded.

In this embodiment, two additional memories have been described. However, more than two additional memories can be used. Although the data to be stored in the memory is shown in two systems, it is needless to say that more data can be used.

[0016]

As described in the embodiments, when storing information of a multi-system data bus, the storage capacity of the additional memory can be used as one system to expand the storage capacity. To expand the storage capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

1: A / D converter, 2: Latch circuit, 3: Memory, 4: Address generation circuit, 5: Memory, 6: Memory, 10: Memory expansion board of conventional example, 21: AD converter, 22: Latch circuit, 23 : Memory, 24: address generation circuit, 51 to 51
58: tristate buffer circuit, 100: memory expansion board of the embodiment of the present invention A: analog input, B: sampling clock, C: A
Digital value after D conversion, D: waveform data bus, E: address bus, A2: analog input, B2: sampling clock, C2: digital value after AD conversion, D2: waveform data bus, E2: address bus.

Claims (2)

[Claims] 1. An additional memory circuit in a memory system for storing information, wherein a plurality of additional memories have means for switching and selecting inputs of multiple systems. 2. A waveform storage device comprising the additional memory circuit according to claim 1.