JP2755290B2 - Biological signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a biological signal processing apparatus for performing A / D conversion on signals such as body temperature, blood pressure, and electrocardiogram at different sampling periods, and performing processing.

[0002]

2. Description of the Related Art Conventionally, this type of biological signal processing apparatus performs A / D conversion at each sampling cycle, and the A / D converted data is transferred to a signal processing CPU for signal processing. The signal-processed data is transferred to a recorder for recording a waveform or a display unit for displaying a waveform.

[0003]

In this conventional biological signal processing device, A / D conversion is performed at the earliest sampling period even for a signal that is good at a slow sampling period.
Data transfer and interruption to the signal processing CPU also operate at the earliest sampling period. Therefore, it is necessary to perform useless processing, and there is a lot of overhead of the signal processing CPU due to the interruption, which lowers the efficiency of the signal processing.

An object of the present invention is to provide a signal processing CPU by simultaneously packetizing A / D conversion data having different sampling periods and transferring them at the minimum sampling period.
It is an object of the present invention to provide a biological signal processing device capable of reducing overhead.

[0005]

According to the present invention, first to N-th (N is an integer of 2 or more) analog input signals are respectively converted into first to N-th analog input signals at different sampling periods corresponding to the respective analog input signals. A first to an N-th A / D converter for converting the digital input signals into first to N-th packet data in a predetermined format as first to N-th packet data; Input means for storing packet multiplexed data, reading out the packet multiplexed data from the input means, performing signal processing on the packet multiplexed data in the unit of the slowest sampling cycle among the sampling cycles, and Signal processing means for storing multiplexed data, and the signal-processed packet multiplexed data from the signal processing means. An output CPU for converting the packet multiplexed data into the first to N-th packet data and transferring the packet multiplexed data at the corresponding sampling cycle, and a first to N-th packet data respectively transferred from the output CPU. A biological signal processing apparatus is provided that includes first to N-th D / A converters that convert an analog output signal at the sampling period.

Further, according to the present invention, the input means includes an input CPU for multiplexing the digital input signals as first to N-th packet data in a predetermined format, and an input CPU for multiplexing the packet-multiplexed packets. A biological signal processing device characterized by comprising an input data transfer memory for storing multiplexed data is obtained.

Further, according to the present invention, the signal processing means reads out the packet multiplexed data from the input data transfer memory and outputs the signal of the packet multiplexed data in the unit of the slowest sampling period among the sampling periods. A biological signal processing apparatus comprising a signal processing CPU for performing processing and an output data transfer memory for storing the signal-processed packet multiplexed data is obtained.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, A /
The D converter 1, A / D converter 2, and A / D converter 3 A / D convert the input signal at different sampling periods. The input CPU 4 multiplexes the A / D converted data into packets and writes the multiplexed data into the input data transfer memory 7. The signal processing CPU 5 reads the data transferred to the input data transfer memory 7, performs signal processing, and writes the result to the output data transfer memory 8. The output CPU 6 is a CPU for outputting signal-processed data. D /
A converter 10, D / A converter 11, D / A converter 12
Is used to output signal-processed data in analog form, and is mainly used for recorder output. The real-time clock 9 generates sampling clocks having different periods.

Next, the operation of FIG. 1 will be described. The input signal is input to the A / D converter 1, the A / D converter 2, and the A / D converter 3. In the real-time clock 9, sampling clocks 13, 14, and 15 having different periods are generated. As an example of FIG. 1, the sampling clock 13 is 1 kHz, the sampling clock 14 is 500 H
z, the sampling clock 15 is 100 Hz, and FIG.
Shows the timing. The input CPU synchronizes with the sampling clock 13 as shown in the timing of FIG.
The data converted by the / D converter 1 is taken. Similarly, the data converted by the A / D converter 2 is taken in synchronization with the sampling clock 14. Sampling clock 15
The data converted by the A / D converter 3 is fetched in synchronization with. A1 to A10, B1 to B5, and C1 in FIG. 2 are data that have been A / D converted in synchronization with the respective sampling clocks. The input CPU creates one packet in the format shown in FIG. . The packet-multiplexed data is written to the input data transfer memory 7.

The signal processing CPU 5 reads the packetized data, and processes ten pieces of data A1 to A10 taken in by the sampling clock 13. Similarly, the data B1 to B1 captured by the sampling clock 14
B5 is processed in batches of five and the sampling clock 15
The data C1 fetched in step 1 is processed by one piece. Here, each of the above processes is performed at the latest sampling clock 15 (100
Hz). The processed data is packetized in the same manner as the input data, and written into the output data transfer memory 8. The format at that time is shown in FIG. 4, and the result of processing A1 to A10 in FIG.
a10, the result of processing B1 to B5 is b1 to b5,
The result of processing 1 is c1.

The output CPU 6 reads the data written in the output data transfer memory 8 and transfers the data to a D / A converter for recorder output. At this time, the data a1 to a10 that have been A / D converted and signal processed by the sampling clock 13 are transferred to the D / A changer 10 at the same timing. Similarly, b1 to b5 transfer data to the D / A converter 11 and D / A converter 12, respectively, at the same timing as the sampling clock 14, and c1 at the same timing as the sampling clock 15. FIG.
Is the output timing.

[0012]

As described above, according to the present invention, A / D conversion data having different sampling periods are packetized to form A / D conversion data having different sampling periods.
Conversion data can be sent at the same time with the minimum sampling period.

Further, by transferring packets at the minimum sampling period, the overhead of the CPU can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a timing of a sampling clock for A / D conversion shown in FIG. 1;

FIG. 3 is a format diagram of a packet of A / D conversion data shown in FIG. 1;

FIG. 4 is a format diagram of a data packet processed by the signal processing CPU of FIG. 1;

FIG. 5 is a diagram showing the timing of a sampling clock for D / A conversion shown in FIG. 1;

[Explanation of symbols]

 1, 2, 3 A / D converter 4 Input CPU 5 Signal processing CPU 6 Output CPU 7 Input data transfer memory 8 Output data transfer memory 10, 11, 12 D / A converter

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-7-281808 (JP, A) JP-A-5-3859 (JP, A) JP-A-2-253746 (JP, A) JP-A-2- 109539 (JP, A) JP-A-2-200246 (JP, A) JP-A-63-87090 (JP, A) JP-A-56-52034 (JP, A) JP-A-9-44782 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) A61B 5/00

Claims (3)

(57) [Claims] The first to Nth (N is an integer of 2 or more) analog input signals are converted into first to Nth digital input signals at different sampling periods corresponding to the respective analog input signals. An N-th A / D converter, input means for packet-multiplexing each of the digital input signals as first to N-th packet data in a predetermined format, and storing the packet-multiplexed packet-multiplexed data; Signal processing means for reading the packet multiplexed data from the input means and performing signal processing of the packet multiplexed data in the slowest sampling cycle unit among the respective sampling cycles, and storing the signal-processed packet multiplexed data; Reading the signal-processed packet multiplexed data from the signal processing means, To output the first to N-th packet data at the corresponding sampling period, and the first to N-th packet data transferred from the output CPU to an analog output signal at the sampling period. First to Nth D / A to be converted
A biological signal processing device comprising a converter. 2. An input CPU for multiplexing the digital input signals as first to N-th packet data in a predetermined format in a predetermined format, and an input for storing the packet multiplexed packet multiplexed data. 2. The biological signal processing device according to claim 1, further comprising a data transfer memory. 3. A signal processing CPU for reading out the packet multiplexed data from the input data transfer memory and performing signal processing on the packet multiplexed data in a unit of the slowest sampling cycle among the sampling cycles. 3. The biological signal processing apparatus according to claim 2, further comprising: an output data transfer memory for storing the signal-processed packet multiplexed data.