JPH04248779A - Automatic audio/video signal synthesizer - Google Patents

Abstract

PURPOSE: To provide an automatic audio/video signal synthesizer in which a static image and an audio output synchronizing with it can be obtained. CONSTITUTION: This device is constituted of converters 1 and 2 which convert an audio signal and a video signal into digital signals, memory 3 which stores the digital-converted video signals for one frame, processor 5 which receives the input of the audio data and the video data, and operates the synthetic signal processing of one byte recording signal, and part 4 which operates automatic addressing so that the video data stored in the memory 3 can be inputted to the processor 5 when the processor 5 reads the audio data.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to an audio/video signal synthesis recording device for a digital audio tape recorder (hereinafter referred to as DAT).
Picture cell of video signal and R of the picture cell
- This relates to an automatic audio/video signal synthesis device that synchronizes G and B signal addresses with audio signals by automatic addressing and synthesizes them by dividing bits.

0002

[Prior Art and Problems to be Solved by the Invention] Generally, DAT converts audio signals into digital signals and records them to obtain high quality sound. The DAT technology has been improved to include a recording/playback function and to have a laser disc-like function that displays a background screen and music at the same time. That is, there is a trend toward recording audio data that is synthesized in real time with still image data corresponding to one frame while maintaining the high sound quality characteristics of DAT. However, because the video data compression methods of video systems are diverse and their timing relationships are complicated, the video recording function of DAT is limited, and it is extremely difficult to accurately synchronize audio and video signals and record them together. The disadvantage was that it became difficult.

[0003] In order to solve these problems, the present invention aims to provide an automatic audio/video signal synthesis device that can synthesize and record audio signals and video signals in accurate synchronization. purpose.

0004

[Means for Solving the Problems] FIG. 1 is a basic configuration diagram of a DAT audio/video signal synthesis device according to the first invention, in which a first an analog/digital converter 1 and a second analog/digital converter 2; a frame memory 3 for storing video signal data output from the second analog/digital converter 2; and a frame memory 3 for storing video signal data output from the second analog/digital converter 2; A digital signal processing processor 5 receives input of audio signal data from the digital converter 1 and also receives input of video signal data from the frame memory 3 and performs synthesis processing. and an automatic addressing section 4 that controls the output of the frame memory 3 and controls the second analog/digital converter 2 so that the signal data is synchronized with the audio signal data and sequentially input to the digital signal processing processor 5. Ru.

In the second invention, the automatic addressing section 4 stores the video signals outputted from the frame memory 3 in registers 16a, 16b, and 16c, and the outputs of the registers 16a, 16b, and 16c, respectively, bit by bit. OR gates OR12 to OR16 and O
A latch 17 that inputs the outputs of the R gates OR12 to OR16 to the digital signal processing processor 5, and an output of an AND gate AN11 that combines the enable signal EN2 of the second analog/digital converter 2 and the analog/digital conversion clock signal A/DCK. OR the signal and the input enable signal IE of the digital signal processing processor 5.
The enable signal EN11 of the registers 16a, 16b, 16c is synthesized by the gate OR11 and the synthesized signal is generated.
The selector 15 sequentially outputs ~EN13 and its overflow signal OF, and the picture cell address of the frame memory 3 is increased by the overflow output signal OF of the selector 15, and is automatically reset when one horizontal line address specification is completed. A picture cell counter 11, a horizontal synchronization counter 12 that counts the horizontal lines of the frame memory 3 based on the output of the picture cell counter 11, and a horizontal synchronization counter that outputs the count output signal of the horizontal synchronization counter 12 as a horizontal line address signal of the frame memory 3. a selector 14 and an address comparator that resets the horizontal synchronization counter 12 and the horizontal synchronization selector 14 when one frame horizontal line count of the frame memory 3 is completed, and outputs an enable signal EN2 to the second analog/digital converter 2. 13.

Furthermore, in the third invention, the digital signal processing processor 5 is arranged such that the digital signal processing processor 5 is supplied with a 10-bit audio signal, a 5-bit video signal, and a 1-bit control signal. configured.

[0007]

According to the present invention, after converting the audio signal and the video signal into digital data, the video data is stored in the frame memory, and after the audio data is input to the digital signal processing processor, the automatic addressing section controls the frame memory. , the video data is input to the digital signal processor, and the digital signal processor combines the audio data and video data together with the control signal into a one-byte composite signal.

[0008]

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings. As shown in Figure 2, the audio signal A
a first analog/digital converter 1 and a second analog/digital converter 2 that convert the still image video signal Vi into a digital signal, respectively, and one frame digitally converted through the second analog/digital converter 2. a frame memory 3 for storing digital video signals, and a frame memory 3 for encoding and interleaving the digitally converted audio signal and video signal, and for encoding and interleaving the digitally converted audio signal and video signal, and for controlling the audio signal (10 bits), the video signal (5 bits), and the control signal by the selection switch SW1. The digital audio signal is divided into 10 bits by the DAT digital signal processing processor 5 which synthesizes (1 bit) byte by byte using a bit division method and performs signal processing for recording on tape, and the input enable signal IE of the digital signal processing processor 5. The automatic audio/video signal according to the present invention includes an automatic addressing unit 4 that automatically increases the address so that the digital video signal stored in the frame memory 3 is inputted sequentially in R, G, and B order of 5 bits at a time. A video signal synthesis device is configured.

As shown in FIG. 3, the automatic addressing section 4 also includes a picture cell counter 11 for storing 512 picture cell addresses in the frame memory 3.
, a horizontal synchronization counter 12 that counts the overflow signal OFI of the picture cell counter 11, and a horizontal synchronization selector 14 that outputs the counter output of the horizontal synchronization counter 12 to the horizontal synchronization address of the frame memory 3.
and, when the count output signal of the horizontal synchronization counter 12 reaches the one-frame horizontal synchronization value (482), the reset signal r of the horizontal synchronization counter 12 and the horizontal synchronization selector 14
an address comparator 13 which generates st2*, rst3* and an enable signal EN2 for the second analog/digital converter 2 through an inverter I13, and the R, G, and B output signals of the frame memory 3 in 5 bits each. The storage registers 16a, 16b, 16c and the second
Enable signal EN2 of analog/digital converter 2
and analog/digital conversion clock signal A/DCL
After combining K with the AND gate AN11, the input enable signal IE of the digital signal processing processor 5 is combined again through the OR gate OR11.
The bit output signals Q0, Q1, and Q2 that receive the output signal of 1 as the clock signal CLK are sent to the registers 16a, 16b, and 1.
6c enable signals EN11, EN12, EN13
A selector 15 outputs the overflow signal OF to the output enable signal OEI of the frame memory 3 and the clock signal CLK1 of the picture cell counter 11, and the 5-bit R, G, and B signals of the registers 16a, 16b, and 16c, respectively. OR gate OR to OR ring
12 to OR16 and digital signal processing processor 5
The input enable signal IE of
2 and a latch 17 which receives the output enable signal OE through the digital signal processor 5 and inputs the 5-bit signal output from the OR gates OR12 to OR16 to the digital signal processor 5.

[0010]The operation of the automatic audio/video signal synthesis apparatus according to the present invention constructed as described above will be explained as follows. In order to record still image information on the DAT, 10 bits are allocated to the audio signal, 5 bits to the video signal, and 1 bit to the control signal for synthesis. Next, the data converted into digital data through the analog/digital converters 1 and 2 may be synchronized by the assigned number of bits and input to the digital signal processor 5, but the control bits are used when recording signals. This control bit is used to distinguish between whether only an audio signal or a combined audio/video signal should be recorded in the 16-bit recording data of the DAT standard, and the control bit is set by the user. Record “1” or “0” in the last bit by controlling it through the selection switch SW1,
During playback, the playback system uses this control bit as a reference to control playback. In addition, since the amount of the signal obtained by digitally converting one frame video signal Vi is several seconds larger than the signal amount obtained by digitally converting the audio signal Au, the video signal Vi is digitally converted once every several seconds and stored in the frame memory 3. Automatic addressing control is performed on the frame memory 3 so that the R, G, and B signals on the frame memory 3 are input to the digital signal processor 5 in synchronization with the audio signal Au. Furthermore, as shown in FIGS. 4 and 5, in the video signal for one frame, 512 picture cells form one horizontal line, and one horizontal line of 512 picture cells forms 482 horizontal lines to form one frame screen. However, since one picture cell has R, G, and B information as shown in FIG. 4, the total digital unit data amount of the video signal required for one frame is 512 x 482 x 3 = 740K. . In other words, the video signal for one frame is the audio signal 7.
Since the size is almost the same as a 40K data unit, the frame memory 3 has a size of 15 bits×250K to store one frame of video signal data.

First, the digital signal processor 5
When the input enable signal IE is output from the input enable signal IE, the audio signal Au passes through the first analog/digital converter 1 and is converted into a digital signal to input a 10-bit signal, and the input enable signal IE passes through the OR gate OR11 to the selector 15. is applied to the clock signal CLK of the output signal Q
0 to Q2 are determined, delayed through inverters I11 and I12, and input to the output enable signal OE of the latch 17. Therefore, R of registers 16a to 16c
The G and B outputs are ORed through OR gates OR12 to OR16, respectively, and latched in latch 17.
The 5-bit digital data signal of the video signal latched is input to the digital signal processing processor 5. That is, a 10-bit audio signal and a 5-bit video signal are input to the digital signal processor 5 at the same timing. In addition, the selector 15 whose output signals Q0 to Q2 are determined by the input enable signal IE of the digital signal processor 5 is connected to each register 1.
Enable 6a, 16b, 16c sequentially from EN11 to E
Since the 5-bit R, G, and B data stored in the registers 16a to 16c pass through OR gates OR12 to OR16, the 5-bit R data, 5
Bits of G data and 5 bits of B data are sequentially latched into the latch 17. At this time, inverter gate I
The output enable signal OE of the latch 17 is activated by the input enable signal IE of the digital signal processing processor 5 delayed by the propagation delay time through I11 and I12, and the latched 5-bit data is input to the digital signal processing processor 5. be done. That is, when the digital signal processor 5 activates the input enable signal IE, 10 bits of audio data is input, and after the propagation delay time of the inverter gates I11 and I12, 5 bits of video data is input from the latch 17 and is input together with 1 control bit. 1 byte of composite data is created, and the video data is divided into 5 bits of R, G,
B data is input sequentially. In this case, the first analog/
The digital converter 1 is for 10 bits, and the second analog/digital converter 2 is for R/G of 1 picture cell.
・5 so that each B is converted to 5 bits of data.
Use registers 16a, 16b, 16c for bits.
and latch 17 are also used for 5 bits.

On the other hand, the selector 15 outputs its output signals Q0 to Q.
2 are activated sequentially to generate an overflow signal OF, which is activated by the output enable OE1 of the frame memory 3 and the picture cell counter 1.
1 clock signal CLK1, so when the picture cell counter 11 increments the address and specifies the next picture cell, each 5-bit R, G, and B data of the corresponding address is transferred from the frame memory 3 to the registers 16a to 16a.
16c. Next, when the picture cell counter 11 finishes addressing 512 picture cells of one horizontal line of the frame memory 3, it generates an overflow signal OF1 and applies it to the clock of the horizontal synchronization counter 12, and also feeds back the reset signal rst1* to the next signal. Counting is started again to specify the 512 picture cell address of the horizontal line. In this way, the picture cell counter 11 increases the picture cell address in the frame memory 3 by the overflow signal OF of the selector 15, counts 512 picture cells of one horizontal line, and generates the overflow signal OF1. Count the horizontal sync signal with
The horizontal synchronization selector 14 designates this as the horizontal synchronization address of the frame memory 3. When the count value of the horizontal synchronization counter 12 in the address comparator 13 reaches 482, which is the horizontal line value of one frame, the horizontal synchronization counter 12 and the horizontal synchronization selector 14 are reset, and the second analog/
Activate digital converter 2. Therefore, the still image video signal Vi passes through the second analog/digital converter 2, is converted into a digital signal, and is stored in the frame memory 3 as a digital signal.
Frame worth of data is stored, but in this case, AND
In order to apply the analog/digital conversion clock signal A/DCK to the clock signal of the selector 15 through the gate AN11,
482 from the first address while specifying the picture cell address of the frame memory 3 with the picture cell counter 11 in synchronization with the overflow signal OF of the selector 15.
One frame of still image video signal data is stored up to the 512 picture cell address of the horizontal line.

[0013]

As explained above, in the automatic audio/video signal synthesis apparatus according to the present invention, digitally converted audio signals and still image video signals are synchronized and input to the digital signal processing processor of the DAT for recording. Therefore, it is possible to realize a system having a recording/playback function using DAT. Furthermore, the digital audio and video signals are automatically synchronized through hardware, thereby facilitating the synthesis of the video and audio signals.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of a DAT audio/video signal synthesis device according to the present invention.

FIG. 2 is a block diagram of an embodiment of a DAT audio/video signal synthesis device according to the present invention.

FIG. 3 is a detailed circuit diagram of a DAT audio/video signal synthesis device according to the present invention.

FIG. 4 is a frame memory configuration diagram according to the present invention.

FIG. 5 is an explanatory diagram of a screen according to the present invention.

[Explanation of symbols]

1...First analog/digital converter 2...Second analog/digital converter 3...Frame memory 4...Automatic addressing section 5...Digital signal processing processor 11...Picture cell counter 12...Horizontal synchronization counter 13...Address comparator 14... Horizontal synchronization selector 15...Selectors 16a, 16b, 16c...Registers OR11, OR12, OR13, OR14, OR15,
OR16...OR gate

Claims (3)

[Claims] 1. A first analog/digital converter (1) and a second analog/digital converter (2) that convert an audio signal (Au) and a video signal (Vi) into digital data, respectively; /A frame memory (3) for storing video signal data output from the digital converter (2), and an input enable signal (IE)
a digital signal processing processor (5) which receives audio signal data from the first analog/digital converter (1) and receives and synthesizes video signal data from the frame memory (3); The video signal data in the frame memory (3) is synchronized with the audio signal data by an input enable signal (IE) of the digital signal processing processor (5), and the frame memory is sequentially input to the digital signal processing processor (5). It controls the output of the memory (3) and the second analog/digital converter (2).
); and an automatic addressing section (4) for controlling the automatic audio/video signal synthesis apparatus. 2. The automatic addressing unit (4) includes registers (16a), (16b), and (16) for storing video signals output from the frame memory (3), respectively.
c) and the registers (16a), (16b), (16
c) OR gates (OR12 to OR16) that OR the outputs of each bit, and the OR gates (OR12 to OR16)
The output of the OR16) is sent to the digital signal processing processor (
5) and the latch (17) input to the second analog/
Enable signal (EN2) of digital converter (2) and analog/digital conversion clock signal (A/D
CK) and the input enable signal (IE) of the digital signal processor (5) are combined by an OR gate (OR11), and the combined signal controls the register (16a).
・(16b)・(16c) enable signal (EN11
~EN13) and outputs its overflow signal (OF), and the selector (
a picture cell counter (11) which increases the picture cell address of the frame memory (3) by the overflow output signal (OF) of 15) and is automatically reset when one horizontal line address specification is completed; and the picture cell counter (11). a horizontal synchronization counter (12) that counts the horizontal lines of the frame memory (3) based on the output of the horizontal synchronization counter (12); and a horizontal counter that outputs the count output signal of the horizontal synchronization counter (12) as a horizontal line address signal of the frame memory (3). a synchronization selector (14);
When one frame horizontal line count of the frame memory (3) is completed, the horizontal synchronization counter (12) and the horizontal synchronization selector (14) are reset, and an enable signal (EN) is sent to the second analog/digital converter (2).
2. The automatic audio/video signal synthesizing device according to claim 1, further comprising: an address comparator (13) for outputting the address comparator (13). 3. The digital signal processing processor (5) is configured such that a 10-bit audio signal, a 5-bit video signal, and a 1-bit control signal are supplied to the digital signal processing processor (5). 2. The automatic audio/video signal synthesis apparatus according to claim 1.