JPH03196740A - Controller for first-in first-out buffer - Google Patents

Abstract

PURPOSE:To process a packet accurately by reducing the time from an end of data read till clearing so as to surely clear an FIFO even when the clearing enable period is short. CONSTITUTION:A data delay latch 4 delays a parallel data (a) from other station sequentially by one clock CK 1 and outputs a delay data (c) sequentially to a terminal D1 of the FIFO. A packet end detection circuit 5 checks the data (a) to detect an invalid data outputted next to a last data (n) and outputs an end flag (b) to an end flag terminal EF of the FIFO 1. As a result, the last data (n) of the delay data (c) and the end flag (b) are fetched simultaneously in the FIFO 1, in which the last data (n) of the delay data (c) and the end flag (b) are stored in pairs. Thus, the data and the end flag are outputted from the FIFO 1 in the same timing and a clear pulse generating means 3 immediately clears the FIFO buffer.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides a first-in, first-out FIFO (Plrst InFirs) that sequentially stores a series of asynchronous data strings and sequentially outputs the stored data in accordance with the storage order.
t Out ) Buffer control device, in particular, even when packets are input continuously at short intervals,
The present invention relates to a FIFO buffer control device that enables accurate processing.

(Prior Art) In a data exchange network such as a LAN, when receiving a series of asynchronous data strings (packets) transmitted between stations, the clock frequency of the received data, which is the output signal of another station, is It is necessary to absorb the frequency difference between the clock frequency of the station and the own station's clock frequency.

In recent years, as a means to absorb such frequency differences, first-in, first-out FIF, which is one of the so-called waiting methods, has been used.
O) Buffers are often used.

FIG. 2 is a diagram showing the configuration of a control circuit around a FIFO according to the prior art, and FIG. 3 is a timing chart thereof.

In the figure, received data (a) constituting a packet is sequentially input to the data input terminal DI of FIFOl, and a clock CLKI synchronized with the received data (a) is input to the clock input terminal CKI for data writing. .

The read ready terminal OR of the FIFOI is connected to the latch 2, the output of the latch 2 is output to the clear pulse generation circuit 3, and the output of the clear pulse generation circuit 3 is connected to the FIFO
It is connected to the clear terminal CL of I. A clock (f') synchronized with the read timing of the own station is input to the clock input terminal CK2 for reading data of the FIFOI,
Received data (S) is sequentially output from the data output terminal DO.

In a device with such a configuration, when received data (a) is input to the DI terminal and clock CLKI is manually input to the CKI terminal, the received data (a) is sequentially fetched into the FIFOI in synchronization with the clock CLKI and stored. be done.

At this point, the guarantee period for absorbing the frequency difference between the own station and other stations has ended, and the received data read clock (r) has changed to F.
When input to the CK2 terminal of the IFOI, the received data (S) stored in the FIFOI is sequentially output from the DO terminal at the timing shown in Figure 3, and at the same time, the F
A read ready signal (
p) is output.

At this time, the received data read pulse (k) synchronized with the clock (') is input to the latch 2, and the ready signal (p) is inputted to the latch 2 as shown in FIG.
The latch signal (q) is latched at the rising timing of signal (k), and the latch signal (q) is input to the clear pulse generation circuit 3.

When the last data stored in the FIFOI (last data) is output and all data output is completed, meaningless data (invalid data) is output from then on as shown in Figure 3. Also, the ready signal (p) falls, indicating that there is no data to be output in the FIFO1.

When the next received data read pulse (k) is inputted to the latch 2 while the ready signal (p) is at the "L" level, the latch signal (9) falls.

The clear pulse generation circuit 3 detects the fall of the latch signal (q) and outputs a clear pulse (X),
Clear FO1.

(Problem to be solved by the invention) F! The stored contents of the FO buffer must be cleared in preparation for the input of the next packet once all data constituting one packet has been sent, but there is a clear permission period during which clearing can be performed, that is, to the own station. The period from the end of data reading to the input of the next received data changes depending on the frequency difference between the frequency of the received data and the frequency of the local station.

FIG. 5(a) shows that the frequency of the received data is slightly lower than the frequency of the own station. In other words, the time t2 required to receive data for one packet of received data is the time required for reading out the data for one packet at the own station. This figure shows the manual timing of receiving data and the timing of reading data to the local station when the time required for
The frequency of the received data is much lower than the frequency of the own station,
In other words, the diagram shows the timing when the time t required to output one packet of received data is much longer than the time t1 at the own station.

When the frequency difference is small, the guaranteed period a1 for absorbing the frequency difference can be short, as shown in FIG. 4A, so the clear permission period b1 is relatively long.

However, if the frequency difference is large, the guarantee period a2 to absorb the frequency difference must be lengthened, as shown in Figure (b), so the data readout timing at the own station will be delayed accordingly. As a result, the clear permission period b2 becomes extremely short.

Further, even if the frequency difference is small, if the arrival times of packets are very close, the clear permission period will similarly become short.

Therefore, in order to completely clear the FIFO, it is desirable to output a clear pulse immediately after data reading to the local station is completed.

However, in the configuration of the conventional technology described above, after the last data is output, the clear pulse (X) is output at the falling timing of the ready signal (q) after the next data is determined to be invalid data. Therefore, the FIFOI ends up being cleared one clock after the last data is output.

In other words, there is one clock worth of wasted time between the end of outputting the received data and the generation of the clear pulse.

Therefore, as mentioned above, if the frequency difference is large,
Alternatively, if the clearing period is short because the packets arrive very close to each other, the next packet may be input before the clearing pulse is output due to this one clock worth of wasted time. There have been reports that accurate data transmission may not be possible.

An object of the present invention is to solve the above-mentioned problems, shorten the time from completion of data reading to data clearing, and ensure that the FIFO can be cleared even if the clearing permission period is short. An object of the present invention is to provide a FIFO buffer control device that allows accurate processing.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a data end detection means that detects the end of input data and outputs an end flag, and a data end detection means that detects the end of input data and outputs an end flag. a delay means for delaying and outputting input data in order to match the write timing of the end flag corresponding to the end flag, and a first-in, first-out system for storing the data output from the delay means together with the end flag output from the data end detection means. The apparatus includes a buffer, end flag detection means for detecting an end flag output together with data from the first-in first-out buffer, and clear pulse generation means for outputting a clear pulse to the buffer when the end flag signal is detected.

(effect) The technical means of the present invention works as follows.

The delay means works to delay the input data until the data end detection means detects the end of the human data and outputs the end flag, so the input data is associated with the end flag and stored in the first-in, first-out buffer. Can be memorized.

Therefore, the data and the end flag can be outputted from the first-in, first-out buffer at the same timing, so that when the last data is output, the clear pulse generating means immediately outputs the data and the end flag from the first-in, first-out buffer to the first-in, first-out buffer based on the end flag detected by the end flag detection means. will be able to clear.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a FIFO control device that is an embodiment of the present invention, and FIG. 4 is a timing chart thereof. The same reference numerals as in FIGS. 2 and 3 indicate the same or equivalent parts. represents.

In the figure, parallel data (a) and clock CLKI from another station are sequentially input to data delay latch 4, and data (a) delayed by data delay latch 4 is inputted sequentially to data delay latch 4.
) is output to the DI terminal of FIFOI. Data (a) from another station is input to the packet end detection circuit 5,
The output signal (b) of the packet end detection circuit 5 is FIF
It is output to the end flag terminal EF of OI.

The end flag detection circuit 6 receives FIFOI output data (
1) is input, and the output signal (j) of the end flag detection circuit 6 is output to the clear pulse generation circuit 3.

The output signal (X) of clear pulse generation circuit 3 is FIFOI
It is output to the clear terminal CL of.

In a device having such a configuration, the data delay latch 4 sequentially delays parallel data (a) from another station by one clock of the clock CLKI as shown in FIG. The data is sequentially output to the DI terminal of the FIFOI.

The packet end detection circuit 5 checks the parallel data (a), detects invalid data output next to the last data n of data (a), for example, an idle code sent between packets, and sets an end flag b. It is output to the end flag terminal EF of the FIFOI at the timing shown in FIG.

As a result, the last data n of the delayed data (C) and the end flag b are simultaneously captured into the FMFOI.

The FIFOI stores the last data n of data (c) and the end flag b in association with each other. For example, data (C
) is 8-bit parallel data, FIFO
I represents the storage area for one data in 9 bits (D (0) ~
D(8)), and its lower 8 bits (D(0) to D(
7)) is allocated to the storage area of data (c), and the most significant 1 bit (D(8)) is allocated to the storage area of end flag b. When end flag b is detected, the data (C) at that time is stored in the lower 8 bits and the most significant bit is set.

On the other hand, when the guarantee period for absorbing the frequency difference between the local station and other stations ends while inputting data (C), and the received data read clock (f) is input to the CK2 terminal of the FIFOI, the DO terminal From there, data (1) (9 bits in this embodiment) stored in FIFO1 is sequentially output.

The lower 8 bits of data (1), ie, the data (C), are transferred to and latched by latch means (not shown), and then output to the subsequent stage. The most significant bit of data (1) is output to the end flag detection circuit 6.

When the most significant bit is set to "1", the end flag detection circuit 6 outputs a detection signal (of the waveform shown in FIG. 4(j)).
D is output to the clear pulse generation circuit 3. The clear pulse generating circuit 3 detects the falling edge of the detection signal (j) and outputs a clear pulse (X) to clear the FIFOI.

Note that the timing for outputting the clear pulse (X) of the clear pulse generating circuit 3 is based on the last data n to the latch means.
(parallel data) are all latched.

According to this embodiment, since the last data and the end flag are output from the FIFOI at the same timing, the FIFOI
FIFO immediately after the last data is output from FOI
I can be cleared. Therefore, compared to the conventional technology, it is possible to clear the FIFO one clock earlier, and even if the clearing permission period is short, the FIFO can be reliably cleared, so the frequency difference between the clock frequency of the received data and the clock frequency of the local station can be Packets can be processed accurately even when the arrival times of the packets are large or the arrival times of the packets are very close to each other.

In the above embodiment, the end of data is detected by detecting invalid data, but an identification code indicating the end of data is provided at the end of data, and an end flag is created by detecting this. It is clear that it is okay to do so.

Further, although the data and the end flag are stored in the same FIFO, it is clear that they may be stored in association with separate FIFOs.

(Effects of the Invention) As is clear from the above explanation, according to the present invention, the FIFO can be reliably cleared even when the clearing permission period is short, so that the clock frequency of the received data and the clock frequency of the own station can be Packets can be processed accurately even if the frequency difference is large or the packets arrive at very close times.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the circuit configuration around the FIFO which is an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of the control circuit around the FIFO according to the prior art, and FIG. 3 is the timing diagram of FIG. 2. 4 is a timing chart of FIG. 1, and FIG. 5 is a diagram for explaining changes in the clear permission period due to the frequency difference between received data and the frequency of the own station.

Claims (1)

[Claims] (1) data end detection means for detecting the end of input data and outputting an end flag; and in order to match the writing timing of the input data with the writing timing of the corresponding end flag,
a delay means for delaying and outputting input data; a first-in, first-out buffer for storing the data output from the delay means together with an end flag output from the data end detection means; and an end flag output from the first-in, first-out buffer together with the data. 1. A control device for a first-in, first-out buffer, comprising: an end flag detection means for detecting an end flag signal; and a clear pulse generation means for outputting a clear pulse to the buffer when an end flag signal is detected.